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@@ -35,6 +35,15 @@ static int gicr_ns_access(GICv3CPUState *cs, int irq)
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return extract32(cs->gicr_nsacr, irq * 2, 2);
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return extract32(cs->gicr_nsacr, irq * 2, 2);
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}
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}
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+static void gicr_write_bitmap_reg(GICv3CPUState *cs, MemTxAttrs attrs,
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+ uint32_t *reg, uint32_t val)
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+{
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+ /* Helper routine to implement writing to a "set" register */
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+ val &= mask_group(cs, attrs);
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+ *reg = val;
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+ gicv3_redist_update(cs);
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+}
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+
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static void gicr_write_set_bitmap_reg(GICv3CPUState *cs, MemTxAttrs attrs,
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static void gicr_write_set_bitmap_reg(GICv3CPUState *cs, MemTxAttrs attrs,
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uint32_t *reg, uint32_t val)
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uint32_t *reg, uint32_t val)
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{
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{
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@@ -406,6 +415,10 @@ static MemTxResult gicr_readl(GICv3CPUState *cs, hwaddr offset,
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*data = value;
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*data = value;
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return MEMTX_OK;
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return MEMTX_OK;
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}
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}
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+ case GICR_INMIR0:
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+ *data = cs->gic->nmi_support ?
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+ gicr_read_bitmap_reg(cs, attrs, cs->gicr_inmir0) : 0;
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+ return MEMTX_OK;
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case GICR_ICFGR0:
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case GICR_ICFGR0:
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case GICR_ICFGR1:
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case GICR_ICFGR1:
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{
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{
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@@ -555,6 +568,12 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr offset,
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gicv3_redist_update(cs);
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gicv3_redist_update(cs);
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return MEMTX_OK;
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return MEMTX_OK;
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}
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}
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+ case GICR_INMIR0:
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+ if (cs->gic->nmi_support) {
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+ gicr_write_bitmap_reg(cs, attrs, &cs->gicr_inmir0, value);
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+ }
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+ return MEMTX_OK;
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+
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case GICR_ICFGR0:
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case GICR_ICFGR0:
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/* Register is all RAZ/WI or RAO/WI bits */
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/* Register is all RAZ/WI or RAO/WI bits */
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return MEMTX_OK;
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return MEMTX_OK;
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