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@@ -411,15 +411,15 @@ static void uart_read_rx_fifo(CadenceUARTState *s, uint32_t *c)
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uart_update_status(s);
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uart_update_status(s);
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}
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}
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-static void uart_write(void *opaque, hwaddr offset,
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- uint64_t value, unsigned size)
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+static MemTxResult uart_write(void *opaque, hwaddr offset,
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+ uint64_t value, unsigned size, MemTxAttrs attrs)
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{
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{
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CadenceUARTState *s = opaque;
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CadenceUARTState *s = opaque;
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DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value);
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DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value);
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offset >>= 2;
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offset >>= 2;
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if (offset >= CADENCE_UART_R_MAX) {
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if (offset >= CADENCE_UART_R_MAX) {
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- return;
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+ return MEMTX_DECODE_ERROR;
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}
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}
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switch (offset) {
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switch (offset) {
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case R_IER: /* ier (wts imr) */
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case R_IER: /* ier (wts imr) */
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@@ -466,30 +466,34 @@ static void uart_write(void *opaque, hwaddr offset,
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break;
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break;
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}
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}
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uart_update_status(s);
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uart_update_status(s);
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+
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+ return MEMTX_OK;
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}
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}
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-static uint64_t uart_read(void *opaque, hwaddr offset,
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- unsigned size)
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+static MemTxResult uart_read(void *opaque, hwaddr offset,
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+ uint64_t *value, unsigned size, MemTxAttrs attrs)
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{
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{
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CadenceUARTState *s = opaque;
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CadenceUARTState *s = opaque;
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uint32_t c = 0;
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uint32_t c = 0;
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offset >>= 2;
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offset >>= 2;
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if (offset >= CADENCE_UART_R_MAX) {
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if (offset >= CADENCE_UART_R_MAX) {
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- c = 0;
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- } else if (offset == R_TX_RX) {
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+ return MEMTX_DECODE_ERROR;
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+ }
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+ if (offset == R_TX_RX) {
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uart_read_rx_fifo(s, &c);
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uart_read_rx_fifo(s, &c);
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} else {
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} else {
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- c = s->r[offset];
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+ c = s->r[offset];
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}
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}
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DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)c);
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DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)c);
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- return c;
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+ *value = c;
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+ return MEMTX_OK;
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}
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}
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static const MemoryRegionOps uart_ops = {
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static const MemoryRegionOps uart_ops = {
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- .read = uart_read,
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- .write = uart_write,
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+ .read_with_attrs = uart_read,
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+ .write_with_attrs = uart_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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};
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