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@@ -31,7 +31,7 @@
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const FBRD_MASK: u32 = 0x3f;
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/// QEMU sourced constant.
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-pub const PL011_FIFO_DEPTH: usize = 16_usize;
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+pub const PL011_FIFO_DEPTH: u32 = 16;
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#[derive(Clone, Copy, Debug)]
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enum DeviceId {
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@@ -56,6 +56,32 @@ impl DeviceId {
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const PL011_ID_LUMINARY: [c_uchar; 8] = [0x11, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1];
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}
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+// FIFOs use 32-bit indices instead of usize, for compatibility with
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+// the migration stream produced by the C version of this device.
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+#[repr(transparent)]
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+#[derive(Debug, Default)]
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+pub struct Fifo([registers::Data; PL011_FIFO_DEPTH as usize]);
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+
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+impl Fifo {
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+ const fn len(&self) -> u32 {
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+ self.0.len() as u32
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+ }
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+}
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+
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+impl std::ops::IndexMut<u32> for Fifo {
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+ fn index_mut(&mut self, idx: u32) -> &mut Self::Output {
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+ &mut self.0[idx as usize]
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+ }
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+}
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+
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+impl std::ops::Index<u32> for Fifo {
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+ type Output = registers::Data;
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+
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+ fn index(&self, idx: u32) -> &Self::Output {
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+ &self.0[idx as usize]
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+ }
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+}
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+
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#[repr(C)]
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#[derive(Debug, qemu_api_macros::Object, qemu_api_macros::offsets)]
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/// PL011 Device Model in QEMU
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@@ -73,14 +99,14 @@ pub struct PL011State {
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pub dmacr: u32,
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pub int_enabled: u32,
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pub int_level: u32,
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- pub read_fifo: [registers::Data; PL011_FIFO_DEPTH],
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+ pub read_fifo: Fifo,
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pub ilpr: u32,
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pub ibrd: u32,
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pub fbrd: u32,
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pub ifl: u32,
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- pub read_pos: usize,
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- pub read_count: usize,
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- pub read_trigger: usize,
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+ pub read_pos: u32,
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+ pub read_count: u32,
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+ pub read_trigger: u32,
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#[doc(alias = "chr")]
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pub char_backend: CharBackend,
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/// QEMU interrupts
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@@ -480,7 +506,7 @@ pub fn loopback_enabled(&self) -> bool {
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}
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#[inline]
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- pub fn fifo_depth(&self) -> usize {
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+ pub fn fifo_depth(&self) -> u32 {
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// Note: FIFO depth is expected to be power-of-2
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if self.fifo_enabled() {
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return PL011_FIFO_DEPTH;
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