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@@ -286,7 +286,7 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts
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hwaddr start_addr,
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hwaddr start_addr,
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hwaddr rom_base, hwaddr rom_size,
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hwaddr rom_base, hwaddr rom_size,
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uint64_t kernel_entry,
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uint64_t kernel_entry,
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- uint64_t fdt_load_addr, void *fdt)
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+ uint64_t fdt_load_addr)
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{
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{
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int i;
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int i;
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uint32_t start_addr_hi32 = 0x00000000;
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uint32_t start_addr_hi32 = 0x00000000;
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@@ -326,8 +326,6 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts
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rom_base, &address_space_memory);
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rom_base, &address_space_memory);
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riscv_rom_copy_firmware_info(machine, rom_base, rom_size, sizeof(reset_vec),
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riscv_rom_copy_firmware_info(machine, rom_base, rom_size, sizeof(reset_vec),
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kernel_entry);
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kernel_entry);
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-
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- return;
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}
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}
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void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr)
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void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr)
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