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@@ -48,14 +48,18 @@ void cpu_check_irqs(CPUSPARCState *env)
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return;
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}
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cs = env_cpu(env);
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- /* check if TM or SM in SOFTINT are set
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- setting these also causes interrupt 14 */
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+ /*
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+ * check if TM or SM in SOFTINT are set
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+ * setting these also causes interrupt 14
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+ */
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if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
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pil |= 1 << 14;
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}
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- /* The bit corresponding to psrpil is (1<< psrpil), the next bit
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- is (2 << psrpil). */
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+ /*
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+ * The bit corresponding to psrpil is (1<< psrpil),
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+ * the next bit is (2 << psrpil).
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+ */
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if (pil < (2 << env->psrpil)) {
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if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
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trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index);
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