|
@@ -283,3 +283,34 @@ hwaddr cris_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
|
|
|
return phy;
|
|
|
}
|
|
|
#endif
|
|
|
+
|
|
|
+bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
|
|
|
+{
|
|
|
+ CPUClass *cc = CPU_GET_CLASS(cs);
|
|
|
+ CRISCPU *cpu = CRIS_CPU(cs);
|
|
|
+ CPUCRISState *env = &cpu->env;
|
|
|
+ bool ret = false;
|
|
|
+
|
|
|
+ if (interrupt_request & CPU_INTERRUPT_HARD
|
|
|
+ && (env->pregs[PR_CCS] & I_FLAG)
|
|
|
+ && !env->locked_irq) {
|
|
|
+ cs->exception_index = EXCP_IRQ;
|
|
|
+ cc->do_interrupt(cs);
|
|
|
+ ret = true;
|
|
|
+ }
|
|
|
+ if (interrupt_request & CPU_INTERRUPT_NMI) {
|
|
|
+ unsigned int m_flag_archval;
|
|
|
+ if (env->pregs[PR_VR] < 32) {
|
|
|
+ m_flag_archval = M_FLAG_V10;
|
|
|
+ } else {
|
|
|
+ m_flag_archval = M_FLAG_V32;
|
|
|
+ }
|
|
|
+ if ((env->pregs[PR_CCS] & m_flag_archval)) {
|
|
|
+ cs->exception_index = EXCP_NMI;
|
|
|
+ cc->do_interrupt(cs);
|
|
|
+ ret = true;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ return ret;
|
|
|
+}
|