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@@ -0,0 +1,111 @@
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+/*
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+ * QEMU PowerPC PowerNV ADU unit
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+ *
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+ * The ADU unit actually implements XSCOM, which is the bridge between MMIO
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+ * and PIB. However it also includes control and status registers and other
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+ * functions that are exposed as PIB (xscom) registers.
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+ *
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+ * To keep things simple, pnv_xscom.c remains the XSCOM bridge
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+ * implementation, and pnv_adu.c implements the ADU registers and other
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+ * functions.
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+ *
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+ * Copyright (c) 2024, IBM Corporation.
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+ *
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+ * SPDX-License-Identifier: GPL-2.0-or-later
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+ */
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+
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+#include "qemu/osdep.h"
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+#include "qemu/log.h"
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+
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+#include "hw/qdev-properties.h"
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+#include "hw/ppc/pnv.h"
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+#include "hw/ppc/pnv_adu.h"
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+#include "hw/ppc/pnv_chip.h"
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+#include "hw/ppc/pnv_xscom.h"
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+#include "trace.h"
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+
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+static uint64_t pnv_adu_xscom_read(void *opaque, hwaddr addr, unsigned width)
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+{
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+ uint32_t offset = addr >> 3;
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+ uint64_t val = 0;
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+
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+ switch (offset) {
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+ case 0x18: /* Receive status reg */
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+ case 0x12: /* log register */
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+ case 0x13: /* error register */
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+ break;
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+
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+ default:
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+ qemu_log_mask(LOG_UNIMP, "ADU Unimplemented read register: Ox%08x\n",
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+ offset);
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+ }
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+
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+ trace_pnv_adu_xscom_read(addr, val);
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+
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+ return val;
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+}
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+
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+static void pnv_adu_xscom_write(void *opaque, hwaddr addr, uint64_t val,
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+ unsigned width)
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+{
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+ uint32_t offset = addr >> 3;
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+
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+ trace_pnv_adu_xscom_write(addr, val);
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+
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+ switch (offset) {
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+ case 0x18: /* Receive status reg */
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+ case 0x12: /* log register */
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+ case 0x13: /* error register */
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+ break;
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+
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+ default:
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+ qemu_log_mask(LOG_UNIMP, "ADU Unimplemented write register: Ox%08x\n",
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+ offset);
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+ }
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+}
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+
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+const MemoryRegionOps pnv_adu_xscom_ops = {
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+ .read = pnv_adu_xscom_read,
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+ .write = pnv_adu_xscom_write,
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+ .valid.min_access_size = 8,
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+ .valid.max_access_size = 8,
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+ .impl.min_access_size = 8,
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+ .impl.max_access_size = 8,
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+ .endianness = DEVICE_BIG_ENDIAN,
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+};
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+
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+static void pnv_adu_realize(DeviceState *dev, Error **errp)
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+{
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+ PnvADU *adu = PNV_ADU(dev);
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+
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+ /* XScom regions for ADU registers */
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+ pnv_xscom_region_init(&adu->xscom_regs, OBJECT(dev),
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+ &pnv_adu_xscom_ops, adu, "xscom-adu",
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+ PNV9_XSCOM_ADU_SIZE);
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+}
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+
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+static void pnv_adu_class_init(ObjectClass *klass, void *data)
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+{
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+ DeviceClass *dc = DEVICE_CLASS(klass);
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+
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+ dc->realize = pnv_adu_realize;
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+ dc->desc = "PowerNV ADU";
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+ dc->user_creatable = false;
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+}
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+
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+static const TypeInfo pnv_adu_type_info = {
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+ .name = TYPE_PNV_ADU,
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+ .parent = TYPE_DEVICE,
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+ .instance_size = sizeof(PnvADU),
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+ .class_init = pnv_adu_class_init,
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+ .interfaces = (InterfaceInfo[]) {
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+ { TYPE_PNV_XSCOM_INTERFACE },
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+ { } },
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+};
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+
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+static void pnv_adu_register_types(void)
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+{
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+ type_register_static(&pnv_adu_type_info);
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+}
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+
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+type_init(pnv_adu_register_types);
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Nicholas Piggin