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@@ -528,7 +528,7 @@ vmxnet3_setup_tx_offloads(VMXNET3State *s)
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break;
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default:
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- assert(false);
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+ g_assert_not_reached();
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return false;
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}
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@@ -575,7 +575,7 @@ vmxnet3_on_tx_done_update_stats(VMXNET3State *s, int qidx,
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stats->ucastBytesTxOK += tot_len;
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break;
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default:
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- assert(false);
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+ g_assert_not_reached();
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}
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if (s->offload_mode == VMXNET3_OM_TSO) {
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@@ -599,7 +599,7 @@ vmxnet3_on_tx_done_update_stats(VMXNET3State *s, int qidx,
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break;
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default:
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- assert(false);
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+ g_assert_not_reached();
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}
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}
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@@ -634,7 +634,7 @@ vmxnet3_on_rx_done_update_stats(VMXNET3State *s,
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stats->ucastBytesRxOK += tot_len;
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break;
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default:
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- assert(false);
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+ g_assert_not_reached();
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}
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if (tot_len > s->mtu) {
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@@ -643,7 +643,7 @@ vmxnet3_on_rx_done_update_stats(VMXNET3State *s,
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}
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break;
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default:
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- assert(false);
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+ g_assert_not_reached();
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}
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}
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@@ -1106,7 +1106,7 @@ vmxnet3_io_bar0_read(void *opaque, hwaddr addr, unsigned size)
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{
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if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR,
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VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) {
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- assert(false);
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+ g_assert_not_reached();
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}
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VMW_CBPRN("BAR0 unknown read [%" PRIx64 "], size %d", addr, size);
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@@ -1651,7 +1651,7 @@ vmxnet3_io_bar1_write(void *opaque,
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case VMXNET3_REG_ICR:
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VMW_CBPRN("Write BAR1 [VMXNET3_REG_ICR] = %" PRIx64 ", size %d",
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val, size);
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- assert(false);
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+ g_assert_not_reached();
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break;
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/* Event Cause Register */
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@@ -1801,7 +1801,7 @@ vmxnet3_rx_filter_may_indicate(VMXNET3State *s, const void *data,
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break;
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default:
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- assert(false);
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+ g_assert_not_reached();
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}
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return true;
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