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@@ -70,44 +70,44 @@ static void test_reg_write_read(void)
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/* Test that non-reserved bits in xMR and xTSR can be set and cleared */
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/* Test that non-reserved bits in xMR and xTSR can be set and cleared */
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exti_writel(EXTI_IMR1, 0xFFFFFFFF);
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exti_writel(EXTI_IMR1, 0xFFFFFFFF);
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- g_assert_cmpuint(exti_readl(EXTI_IMR1), ==, 0xFFFFFFFF);
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+ g_assert_cmphex(exti_readl(EXTI_IMR1), ==, 0xFFFFFFFF);
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exti_writel(EXTI_IMR1, 0x00000000);
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exti_writel(EXTI_IMR1, 0x00000000);
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- g_assert_cmpuint(exti_readl(EXTI_IMR1), ==, 0x00000000);
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+ g_assert_cmphex(exti_readl(EXTI_IMR1), ==, 0x00000000);
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exti_writel(EXTI_EMR1, 0xFFFFFFFF);
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exti_writel(EXTI_EMR1, 0xFFFFFFFF);
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- g_assert_cmpuint(exti_readl(EXTI_EMR1), ==, 0xFFFFFFFF);
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+ g_assert_cmphex(exti_readl(EXTI_EMR1), ==, 0xFFFFFFFF);
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exti_writel(EXTI_EMR1, 0x00000000);
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exti_writel(EXTI_EMR1, 0x00000000);
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- g_assert_cmpuint(exti_readl(EXTI_EMR1), ==, 0x00000000);
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+ g_assert_cmphex(exti_readl(EXTI_EMR1), ==, 0x00000000);
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exti_writel(EXTI_RTSR1, 0xFFFFFFFF);
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exti_writel(EXTI_RTSR1, 0xFFFFFFFF);
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- g_assert_cmpuint(exti_readl(EXTI_RTSR1), ==, 0x007DFFFF);
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+ g_assert_cmphex(exti_readl(EXTI_RTSR1), ==, 0x007DFFFF);
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exti_writel(EXTI_RTSR1, 0x00000000);
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exti_writel(EXTI_RTSR1, 0x00000000);
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- g_assert_cmpuint(exti_readl(EXTI_RTSR1), ==, 0x00000000);
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+ g_assert_cmphex(exti_readl(EXTI_RTSR1), ==, 0x00000000);
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exti_writel(EXTI_FTSR1, 0xFFFFFFFF);
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exti_writel(EXTI_FTSR1, 0xFFFFFFFF);
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- g_assert_cmpuint(exti_readl(EXTI_FTSR1), ==, 0x007DFFFF);
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+ g_assert_cmphex(exti_readl(EXTI_FTSR1), ==, 0x007DFFFF);
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exti_writel(EXTI_FTSR1, 0x00000000);
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exti_writel(EXTI_FTSR1, 0x00000000);
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- g_assert_cmpuint(exti_readl(EXTI_FTSR1), ==, 0x00000000);
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+ g_assert_cmphex(exti_readl(EXTI_FTSR1), ==, 0x00000000);
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exti_writel(EXTI_IMR2, 0xFFFFFFFF);
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exti_writel(EXTI_IMR2, 0xFFFFFFFF);
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- g_assert_cmpuint(exti_readl(EXTI_IMR2), ==, 0x000000FF);
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+ g_assert_cmphex(exti_readl(EXTI_IMR2), ==, 0x000000FF);
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exti_writel(EXTI_IMR2, 0x00000000);
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exti_writel(EXTI_IMR2, 0x00000000);
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- g_assert_cmpuint(exti_readl(EXTI_IMR2), ==, 0x00000000);
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+ g_assert_cmphex(exti_readl(EXTI_IMR2), ==, 0x00000000);
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exti_writel(EXTI_EMR2, 0xFFFFFFFF);
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exti_writel(EXTI_EMR2, 0xFFFFFFFF);
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- g_assert_cmpuint(exti_readl(EXTI_EMR2), ==, 0x000000FF);
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+ g_assert_cmphex(exti_readl(EXTI_EMR2), ==, 0x000000FF);
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exti_writel(EXTI_EMR2, 0x00000000);
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exti_writel(EXTI_EMR2, 0x00000000);
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- g_assert_cmpuint(exti_readl(EXTI_EMR2), ==, 0x00000000);
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+ g_assert_cmphex(exti_readl(EXTI_EMR2), ==, 0x00000000);
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exti_writel(EXTI_RTSR2, 0xFFFFFFFF);
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exti_writel(EXTI_RTSR2, 0xFFFFFFFF);
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- g_assert_cmpuint(exti_readl(EXTI_RTSR2), ==, 0x00000078);
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+ g_assert_cmphex(exti_readl(EXTI_RTSR2), ==, 0x00000078);
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exti_writel(EXTI_RTSR2, 0x00000000);
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exti_writel(EXTI_RTSR2, 0x00000000);
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- g_assert_cmpuint(exti_readl(EXTI_RTSR2), ==, 0x00000000);
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+ g_assert_cmphex(exti_readl(EXTI_RTSR2), ==, 0x00000000);
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exti_writel(EXTI_FTSR2, 0xFFFFFFFF);
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exti_writel(EXTI_FTSR2, 0xFFFFFFFF);
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- g_assert_cmpuint(exti_readl(EXTI_FTSR2), ==, 0x00000078);
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+ g_assert_cmphex(exti_readl(EXTI_FTSR2), ==, 0x00000078);
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exti_writel(EXTI_FTSR2, 0x00000000);
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exti_writel(EXTI_FTSR2, 0x00000000);
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- g_assert_cmpuint(exti_readl(EXTI_FTSR2), ==, 0x00000000);
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+ g_assert_cmphex(exti_readl(EXTI_FTSR2), ==, 0x00000000);
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}
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}
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static void test_direct_lines_write(void)
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static void test_direct_lines_write(void)
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@@ -115,28 +115,28 @@ static void test_direct_lines_write(void)
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/* Test that direct lines reserved bits are not written to */
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/* Test that direct lines reserved bits are not written to */
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exti_writel(EXTI_RTSR1, 0xFF820000);
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exti_writel(EXTI_RTSR1, 0xFF820000);
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- g_assert_cmpuint(exti_readl(EXTI_RTSR1), ==, 0x00000000);
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+ g_assert_cmphex(exti_readl(EXTI_RTSR1), ==, 0x00000000);
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exti_writel(EXTI_FTSR1, 0xFF820000);
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exti_writel(EXTI_FTSR1, 0xFF820000);
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- g_assert_cmpuint(exti_readl(EXTI_FTSR1), ==, 0x00000000);
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+ g_assert_cmphex(exti_readl(EXTI_FTSR1), ==, 0x00000000);
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exti_writel(EXTI_SWIER1, 0xFF820000);
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exti_writel(EXTI_SWIER1, 0xFF820000);
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- g_assert_cmpuint(exti_readl(EXTI_SWIER1), ==, 0x00000000);
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+ g_assert_cmphex(exti_readl(EXTI_SWIER1), ==, 0x00000000);
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exti_writel(EXTI_PR1, 0xFF820000);
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exti_writel(EXTI_PR1, 0xFF820000);
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- g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
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+ g_assert_cmphex(exti_readl(EXTI_PR1), ==, 0x00000000);
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exti_writel(EXTI_RTSR2, 0x00000087);
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exti_writel(EXTI_RTSR2, 0x00000087);
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- g_assert_cmpuint(exti_readl(EXTI_RTSR2), ==, 0x00000000);
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+ g_assert_cmphex(exti_readl(EXTI_RTSR2), ==, 0x00000000);
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exti_writel(EXTI_FTSR2, 0x00000087);
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exti_writel(EXTI_FTSR2, 0x00000087);
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- g_assert_cmpuint(exti_readl(EXTI_FTSR2), ==, 0x00000000);
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+ g_assert_cmphex(exti_readl(EXTI_FTSR2), ==, 0x00000000);
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exti_writel(EXTI_SWIER2, 0x00000087);
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exti_writel(EXTI_SWIER2, 0x00000087);
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- g_assert_cmpuint(exti_readl(EXTI_SWIER2), ==, 0x00000000);
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+ g_assert_cmphex(exti_readl(EXTI_SWIER2), ==, 0x00000000);
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exti_writel(EXTI_PR2, 0x00000087);
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exti_writel(EXTI_PR2, 0x00000087);
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- g_assert_cmpuint(exti_readl(EXTI_PR2), ==, 0x00000000);
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+ g_assert_cmphex(exti_readl(EXTI_PR2), ==, 0x00000000);
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}
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}
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static void test_reserved_bits_write(void)
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static void test_reserved_bits_write(void)
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@@ -144,22 +144,22 @@ static void test_reserved_bits_write(void)
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/* Test that reserved bits stay are not written to */
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/* Test that reserved bits stay are not written to */
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exti_writel(EXTI_IMR2, 0xFFFFFF00);
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exti_writel(EXTI_IMR2, 0xFFFFFF00);
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- g_assert_cmpuint(exti_readl(EXTI_IMR2), ==, 0x00000000);
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+ g_assert_cmphex(exti_readl(EXTI_IMR2), ==, 0x00000000);
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exti_writel(EXTI_EMR2, 0xFFFFFF00);
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exti_writel(EXTI_EMR2, 0xFFFFFF00);
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- g_assert_cmpuint(exti_readl(EXTI_EMR2), ==, 0x00000000);
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+ g_assert_cmphex(exti_readl(EXTI_EMR2), ==, 0x00000000);
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exti_writel(EXTI_RTSR2, 0xFFFFFF00);
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exti_writel(EXTI_RTSR2, 0xFFFFFF00);
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- g_assert_cmpuint(exti_readl(EXTI_RTSR2), ==, 0x00000000);
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+ g_assert_cmphex(exti_readl(EXTI_RTSR2), ==, 0x00000000);
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exti_writel(EXTI_FTSR2, 0xFFFFFF00);
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exti_writel(EXTI_FTSR2, 0xFFFFFF00);
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- g_assert_cmpuint(exti_readl(EXTI_FTSR2), ==, 0x00000000);
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+ g_assert_cmphex(exti_readl(EXTI_FTSR2), ==, 0x00000000);
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exti_writel(EXTI_SWIER2, 0xFFFFFF00);
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exti_writel(EXTI_SWIER2, 0xFFFFFF00);
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- g_assert_cmpuint(exti_readl(EXTI_SWIER2), ==, 0x00000000);
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+ g_assert_cmphex(exti_readl(EXTI_SWIER2), ==, 0x00000000);
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exti_writel(EXTI_PR2, 0xFFFFFF00);
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exti_writel(EXTI_PR2, 0xFFFFFF00);
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- g_assert_cmpuint(exti_readl(EXTI_PR2), ==, 0x00000000);
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+ g_assert_cmphex(exti_readl(EXTI_PR2), ==, 0x00000000);
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}
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}
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static void test_software_interrupt(void)
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static void test_software_interrupt(void)
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@@ -180,7 +180,7 @@ static void test_software_interrupt(void)
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enable_nvic_irq(EXTI0_IRQ);
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enable_nvic_irq(EXTI0_IRQ);
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/* Check that there are no interrupts already pending in PR */
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/* Check that there are no interrupts already pending in PR */
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- g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
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+ g_assert_cmphex(exti_readl(EXTI_PR1), ==, 0x00000000);
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/* Check that this specific interrupt isn't pending in NVIC */
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/* Check that this specific interrupt isn't pending in NVIC */
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g_assert_false(check_nvic_pending(EXTI0_IRQ));
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g_assert_false(check_nvic_pending(EXTI0_IRQ));
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@@ -191,9 +191,9 @@ static void test_software_interrupt(void)
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exti_writel(EXTI_SWIER1, 0x00000001);
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exti_writel(EXTI_SWIER1, 0x00000001);
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/* Check that the write in SWIER was effective */
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/* Check that the write in SWIER was effective */
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- g_assert_cmpuint(exti_readl(EXTI_SWIER1), ==, 0x00000001);
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+ g_assert_cmphex(exti_readl(EXTI_SWIER1), ==, 0x00000001);
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/* Check that the corresponding pending bit in PR is set */
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/* Check that the corresponding pending bit in PR is set */
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- g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000001);
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+ g_assert_cmphex(exti_readl(EXTI_PR1), ==, 0x00000001);
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/* Check that the corresponding interrupt is pending in the NVIC */
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/* Check that the corresponding interrupt is pending in the NVIC */
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g_assert_true(check_nvic_pending(EXTI0_IRQ));
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g_assert_true(check_nvic_pending(EXTI0_IRQ));
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@@ -201,9 +201,9 @@ static void test_software_interrupt(void)
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exti_writel(EXTI_PR1, 0x00000001);
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exti_writel(EXTI_PR1, 0x00000001);
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/* Check that the write in PR was effective */
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/* Check that the write in PR was effective */
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- g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
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+ g_assert_cmphex(exti_readl(EXTI_PR1), ==, 0x00000000);
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/* Check that the corresponding bit in SWIER was cleared */
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/* Check that the corresponding bit in SWIER was cleared */
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- g_assert_cmpuint(exti_readl(EXTI_SWIER1), ==, 0x00000000);
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+ g_assert_cmphex(exti_readl(EXTI_SWIER1), ==, 0x00000000);
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/* Check that the interrupt is still pending in the NVIC */
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/* Check that the interrupt is still pending in the NVIC */
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g_assert_true(check_nvic_pending(EXTI0_IRQ));
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g_assert_true(check_nvic_pending(EXTI0_IRQ));
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@@ -214,7 +214,7 @@ static void test_software_interrupt(void)
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enable_nvic_irq(EXTI35_IRQ);
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enable_nvic_irq(EXTI35_IRQ);
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/* Check that there are no interrupts already pending */
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/* Check that there are no interrupts already pending */
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- g_assert_cmpuint(exti_readl(EXTI_PR2), ==, 0x00000000);
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+ g_assert_cmphex(exti_readl(EXTI_PR2), ==, 0x00000000);
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g_assert_false(check_nvic_pending(EXTI35_IRQ));
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g_assert_false(check_nvic_pending(EXTI35_IRQ));
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/* Enable interrupt line EXTI0 */
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/* Enable interrupt line EXTI0 */
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@@ -224,9 +224,9 @@ static void test_software_interrupt(void)
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exti_writel(EXTI_SWIER2, 0x00000008);
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exti_writel(EXTI_SWIER2, 0x00000008);
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/* Check that the write in SWIER was effective */
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/* Check that the write in SWIER was effective */
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- g_assert_cmpuint(exti_readl(EXTI_SWIER2), ==, 0x00000008);
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+ g_assert_cmphex(exti_readl(EXTI_SWIER2), ==, 0x00000008);
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/* Check that the corresponding pending bit in PR is set */
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/* Check that the corresponding pending bit in PR is set */
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- g_assert_cmpuint(exti_readl(EXTI_PR2), ==, 0x00000008);
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+ g_assert_cmphex(exti_readl(EXTI_PR2), ==, 0x00000008);
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/* Check that the corresponding interrupt is pending in the NVIC */
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/* Check that the corresponding interrupt is pending in the NVIC */
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g_assert_true(check_nvic_pending(EXTI35_IRQ));
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g_assert_true(check_nvic_pending(EXTI35_IRQ));
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@@ -234,9 +234,9 @@ static void test_software_interrupt(void)
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exti_writel(EXTI_PR2, 0x00000008);
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exti_writel(EXTI_PR2, 0x00000008);
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/* Check that the write in PR was effective */
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/* Check that the write in PR was effective */
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- g_assert_cmpuint(exti_readl(EXTI_PR2), ==, 0x00000000);
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+ g_assert_cmphex(exti_readl(EXTI_PR2), ==, 0x00000000);
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/* Check that the corresponding bit in SWIER was cleared */
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/* Check that the corresponding bit in SWIER was cleared */
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- g_assert_cmpuint(exti_readl(EXTI_SWIER2), ==, 0x00000000);
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+ g_assert_cmphex(exti_readl(EXTI_SWIER2), ==, 0x00000000);
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/* Check that the interrupt is still pending in the NVIC */
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/* Check that the interrupt is still pending in the NVIC */
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g_assert_true(check_nvic_pending(EXTI35_IRQ));
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g_assert_true(check_nvic_pending(EXTI35_IRQ));
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@@ -259,16 +259,16 @@ static void test_edge_selector(void)
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/* Test that an irq is raised on rising edge only */
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/* Test that an irq is raised on rising edge only */
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exti_set_irq(0, 0);
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exti_set_irq(0, 0);
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- g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
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+ g_assert_cmphex(exti_readl(EXTI_PR1), ==, 0x00000000);
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g_assert_false(check_nvic_pending(EXTI0_IRQ));
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g_assert_false(check_nvic_pending(EXTI0_IRQ));
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exti_set_irq(0, 1);
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exti_set_irq(0, 1);
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- g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000001);
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+ g_assert_cmphex(exti_readl(EXTI_PR1), ==, 0x00000001);
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g_assert_true(check_nvic_pending(EXTI0_IRQ));
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g_assert_true(check_nvic_pending(EXTI0_IRQ));
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/* Clean the test */
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/* Clean the test */
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exti_writel(EXTI_PR1, 0x00000001);
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exti_writel(EXTI_PR1, 0x00000001);
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- g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
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+ g_assert_cmphex(exti_readl(EXTI_PR1), ==, 0x00000000);
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unpend_nvic_irq(EXTI0_IRQ);
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unpend_nvic_irq(EXTI0_IRQ);
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g_assert_false(check_nvic_pending(EXTI0_IRQ));
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g_assert_false(check_nvic_pending(EXTI0_IRQ));
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@@ -280,16 +280,16 @@ static void test_edge_selector(void)
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/* Test that an irq is raised on falling edge only */
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/* Test that an irq is raised on falling edge only */
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exti_set_irq(0, 1);
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exti_set_irq(0, 1);
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- g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
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+ g_assert_cmphex(exti_readl(EXTI_PR1), ==, 0x00000000);
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g_assert_false(check_nvic_pending(EXTI0_IRQ));
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g_assert_false(check_nvic_pending(EXTI0_IRQ));
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exti_set_irq(0, 0);
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exti_set_irq(0, 0);
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- g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000001);
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+ g_assert_cmphex(exti_readl(EXTI_PR1), ==, 0x00000001);
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g_assert_true(check_nvic_pending(EXTI0_IRQ));
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g_assert_true(check_nvic_pending(EXTI0_IRQ));
|
|
|
|
|
|
/* Clean the test */
|
|
/* Clean the test */
|
|
exti_writel(EXTI_PR1, 0x00000001);
|
|
exti_writel(EXTI_PR1, 0x00000001);
|
|
- g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
|
|
|
|
|
|
+ g_assert_cmphex(exti_readl(EXTI_PR1), ==, 0x00000000);
|
|
unpend_nvic_irq(EXTI0_IRQ);
|
|
unpend_nvic_irq(EXTI0_IRQ);
|
|
g_assert_false(check_nvic_pending(EXTI0_IRQ));
|
|
g_assert_false(check_nvic_pending(EXTI0_IRQ));
|
|
|
|
|
|
@@ -300,23 +300,23 @@ static void test_edge_selector(void)
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|
|
|
|
/* Test that an irq is raised on rising edge */
|
|
/* Test that an irq is raised on rising edge */
|
|
exti_set_irq(0, 1);
|
|
exti_set_irq(0, 1);
|
|
- g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000001);
|
|
|
|
|
|
+ g_assert_cmphex(exti_readl(EXTI_PR1), ==, 0x00000001);
|
|
g_assert_true(check_nvic_pending(EXTI0_IRQ));
|
|
g_assert_true(check_nvic_pending(EXTI0_IRQ));
|
|
|
|
|
|
/* Clean the test */
|
|
/* Clean the test */
|
|
exti_writel(EXTI_PR1, 0x00000001);
|
|
exti_writel(EXTI_PR1, 0x00000001);
|
|
- g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
|
|
|
|
|
|
+ g_assert_cmphex(exti_readl(EXTI_PR1), ==, 0x00000000);
|
|
unpend_nvic_irq(EXTI0_IRQ);
|
|
unpend_nvic_irq(EXTI0_IRQ);
|
|
g_assert_false(check_nvic_pending(EXTI0_IRQ));
|
|
g_assert_false(check_nvic_pending(EXTI0_IRQ));
|
|
|
|
|
|
/* Test that an irq is raised on falling edge */
|
|
/* Test that an irq is raised on falling edge */
|
|
exti_set_irq(0, 0);
|
|
exti_set_irq(0, 0);
|
|
- g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000001);
|
|
|
|
|
|
+ g_assert_cmphex(exti_readl(EXTI_PR1), ==, 0x00000001);
|
|
g_assert_true(check_nvic_pending(EXTI0_IRQ));
|
|
g_assert_true(check_nvic_pending(EXTI0_IRQ));
|
|
|
|
|
|
/* Clean the test */
|
|
/* Clean the test */
|
|
exti_writel(EXTI_PR1, 0x00000001);
|
|
exti_writel(EXTI_PR1, 0x00000001);
|
|
- g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
|
|
|
|
|
|
+ g_assert_cmphex(exti_readl(EXTI_PR1), ==, 0x00000000);
|
|
unpend_nvic_irq(EXTI0_IRQ);
|
|
unpend_nvic_irq(EXTI0_IRQ);
|
|
g_assert_false(check_nvic_pending(EXTI0_IRQ));
|
|
g_assert_false(check_nvic_pending(EXTI0_IRQ));
|
|
|
|
|
|
@@ -327,11 +327,11 @@ static void test_edge_selector(void)
|
|
|
|
|
|
/* Test that no irq is raised */
|
|
/* Test that no irq is raised */
|
|
exti_set_irq(0, 1);
|
|
exti_set_irq(0, 1);
|
|
- g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
|
|
|
|
|
|
+ g_assert_cmphex(exti_readl(EXTI_PR1), ==, 0x00000000);
|
|
g_assert_false(check_nvic_pending(EXTI0_IRQ));
|
|
g_assert_false(check_nvic_pending(EXTI0_IRQ));
|
|
|
|
|
|
exti_set_irq(0, 0);
|
|
exti_set_irq(0, 0);
|
|
- g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
|
|
|
|
|
|
+ g_assert_cmphex(exti_readl(EXTI_PR1), ==, 0x00000000);
|
|
g_assert_false(check_nvic_pending(EXTI0_IRQ));
|
|
g_assert_false(check_nvic_pending(EXTI0_IRQ));
|
|
}
|
|
}
|
|
|
|
|
|
@@ -350,7 +350,7 @@ static void test_no_software_interrupt(void)
|
|
|
|
|
|
enable_nvic_irq(EXTI0_IRQ);
|
|
enable_nvic_irq(EXTI0_IRQ);
|
|
/* Check that there are no interrupts already pending in PR */
|
|
/* Check that there are no interrupts already pending in PR */
|
|
- g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
|
|
|
|
|
|
+ g_assert_cmphex(exti_readl(EXTI_PR1), ==, 0x00000000);
|
|
/* Check that this specific interrupt isn't pending in NVIC */
|
|
/* Check that this specific interrupt isn't pending in NVIC */
|
|
g_assert_false(check_nvic_pending(EXTI0_IRQ));
|
|
g_assert_false(check_nvic_pending(EXTI0_IRQ));
|
|
|
|
|
|
@@ -361,9 +361,9 @@ static void test_no_software_interrupt(void)
|
|
exti_writel(EXTI_SWIER1, 0x00000001);
|
|
exti_writel(EXTI_SWIER1, 0x00000001);
|
|
|
|
|
|
/* Check that the write in SWIER was effective */
|
|
/* Check that the write in SWIER was effective */
|
|
- g_assert_cmpuint(exti_readl(EXTI_SWIER1), ==, 0x00000001);
|
|
|
|
|
|
+ g_assert_cmphex(exti_readl(EXTI_SWIER1), ==, 0x00000001);
|
|
/* Check that the pending bit in PR wasn't set */
|
|
/* Check that the pending bit in PR wasn't set */
|
|
- g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
|
|
|
|
|
|
+ g_assert_cmphex(exti_readl(EXTI_PR1), ==, 0x00000000);
|
|
/* Check that the interrupt isn't pending in NVIC */
|
|
/* Check that the interrupt isn't pending in NVIC */
|
|
g_assert_false(check_nvic_pending(EXTI0_IRQ));
|
|
g_assert_false(check_nvic_pending(EXTI0_IRQ));
|
|
|
|
|
|
@@ -371,7 +371,7 @@ static void test_no_software_interrupt(void)
|
|
exti_writel(EXTI_IMR1, 0x00000001);
|
|
exti_writel(EXTI_IMR1, 0x00000001);
|
|
|
|
|
|
/* Check that the pending bit in PR wasn't set */
|
|
/* Check that the pending bit in PR wasn't set */
|
|
- g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
|
|
|
|
|
|
+ g_assert_cmphex(exti_readl(EXTI_PR1), ==, 0x00000000);
|
|
/* Check that the interrupt isn't pending in NVIC */
|
|
/* Check that the interrupt isn't pending in NVIC */
|
|
g_assert_false(check_nvic_pending(EXTI0_IRQ));
|
|
g_assert_false(check_nvic_pending(EXTI0_IRQ));
|
|
|
|
|
|
@@ -382,7 +382,7 @@ static void test_no_software_interrupt(void)
|
|
|
|
|
|
enable_nvic_irq(EXTI35_IRQ);
|
|
enable_nvic_irq(EXTI35_IRQ);
|
|
/* Check that there are no interrupts already pending in PR */
|
|
/* Check that there are no interrupts already pending in PR */
|
|
- g_assert_cmpuint(exti_readl(EXTI_PR2), ==, 0x00000000);
|
|
|
|
|
|
+ g_assert_cmphex(exti_readl(EXTI_PR2), ==, 0x00000000);
|
|
/* Check that this specific interrupt isn't pending in NVIC */
|
|
/* Check that this specific interrupt isn't pending in NVIC */
|
|
g_assert_false(check_nvic_pending(EXTI35_IRQ));
|
|
g_assert_false(check_nvic_pending(EXTI35_IRQ));
|
|
|
|
|
|
@@ -393,9 +393,9 @@ static void test_no_software_interrupt(void)
|
|
exti_writel(EXTI_SWIER2, 0x00000008);
|
|
exti_writel(EXTI_SWIER2, 0x00000008);
|
|
|
|
|
|
/* Check that the write in SWIER was effective */
|
|
/* Check that the write in SWIER was effective */
|
|
- g_assert_cmpuint(exti_readl(EXTI_SWIER2), ==, 0x00000008);
|
|
|
|
|
|
+ g_assert_cmphex(exti_readl(EXTI_SWIER2), ==, 0x00000008);
|
|
/* Check that the pending bit in PR wasn't set */
|
|
/* Check that the pending bit in PR wasn't set */
|
|
- g_assert_cmpuint(exti_readl(EXTI_PR2), ==, 0x00000000);
|
|
|
|
|
|
+ g_assert_cmphex(exti_readl(EXTI_PR2), ==, 0x00000000);
|
|
/* Check that the interrupt isn't pending in NVIC */
|
|
/* Check that the interrupt isn't pending in NVIC */
|
|
g_assert_false(check_nvic_pending(EXTI35_IRQ));
|
|
g_assert_false(check_nvic_pending(EXTI35_IRQ));
|
|
|
|
|
|
@@ -403,7 +403,7 @@ static void test_no_software_interrupt(void)
|
|
exti_writel(EXTI_IMR2, 0x00000008);
|
|
exti_writel(EXTI_IMR2, 0x00000008);
|
|
|
|
|
|
/* Check that the pending bit in PR wasn't set */
|
|
/* Check that the pending bit in PR wasn't set */
|
|
- g_assert_cmpuint(exti_readl(EXTI_PR2), ==, 0x00000000);
|
|
|
|
|
|
+ g_assert_cmphex(exti_readl(EXTI_PR2), ==, 0x00000000);
|
|
/* Check that the interrupt isn't pending in NVIC */
|
|
/* Check that the interrupt isn't pending in NVIC */
|
|
g_assert_false(check_nvic_pending(EXTI35_IRQ));
|
|
g_assert_false(check_nvic_pending(EXTI35_IRQ));
|
|
}
|
|
}
|
|
@@ -423,7 +423,7 @@ static void test_masked_interrupt(void)
|
|
|
|
|
|
enable_nvic_irq(EXTI1_IRQ);
|
|
enable_nvic_irq(EXTI1_IRQ);
|
|
/* Check that there are no interrupts already pending in PR */
|
|
/* Check that there are no interrupts already pending in PR */
|
|
- g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
|
|
|
|
|
|
+ g_assert_cmphex(exti_readl(EXTI_PR1), ==, 0x00000000);
|
|
/* Check that this specific interrupt isn't pending in NVIC */
|
|
/* Check that this specific interrupt isn't pending in NVIC */
|
|
g_assert_false(check_nvic_pending(EXTI1_IRQ));
|
|
g_assert_false(check_nvic_pending(EXTI1_IRQ));
|
|
|
|
|
|
@@ -437,7 +437,7 @@ static void test_masked_interrupt(void)
|
|
exti_set_irq(1, 1);
|
|
exti_set_irq(1, 1);
|
|
|
|
|
|
/* Check that the pending bit in PR wasn't set */
|
|
/* Check that the pending bit in PR wasn't set */
|
|
- g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
|
|
|
|
|
|
+ g_assert_cmphex(exti_readl(EXTI_PR1), ==, 0x00000000);
|
|
/* Check that the interrupt isn't pending in NVIC */
|
|
/* Check that the interrupt isn't pending in NVIC */
|
|
g_assert_false(check_nvic_pending(EXTI1_IRQ));
|
|
g_assert_false(check_nvic_pending(EXTI1_IRQ));
|
|
|
|
|
|
@@ -445,7 +445,7 @@ static void test_masked_interrupt(void)
|
|
exti_writel(EXTI_IMR1, 0x00000002);
|
|
exti_writel(EXTI_IMR1, 0x00000002);
|
|
|
|
|
|
/* Check that the pending bit in PR wasn't set */
|
|
/* Check that the pending bit in PR wasn't set */
|
|
- g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
|
|
|
|
|
|
+ g_assert_cmphex(exti_readl(EXTI_PR1), ==, 0x00000000);
|
|
/* Check that the interrupt isn't pending in NVIC */
|
|
/* Check that the interrupt isn't pending in NVIC */
|
|
g_assert_false(check_nvic_pending(EXTI1_IRQ));
|
|
g_assert_false(check_nvic_pending(EXTI1_IRQ));
|
|
}
|
|
}
|
|
@@ -469,7 +469,7 @@ static void test_interrupt(void)
|
|
|
|
|
|
enable_nvic_irq(EXTI1_IRQ);
|
|
enable_nvic_irq(EXTI1_IRQ);
|
|
/* Check that there are no interrupts already pending in PR */
|
|
/* Check that there are no interrupts already pending in PR */
|
|
- g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
|
|
|
|
|
|
+ g_assert_cmphex(exti_readl(EXTI_PR1), ==, 0x00000000);
|
|
/* Check that this specific interrupt isn't pending in NVIC */
|
|
/* Check that this specific interrupt isn't pending in NVIC */
|
|
g_assert_false(check_nvic_pending(EXTI1_IRQ));
|
|
g_assert_false(check_nvic_pending(EXTI1_IRQ));
|
|
|
|
|
|
@@ -483,7 +483,7 @@ static void test_interrupt(void)
|
|
exti_set_irq(1, 1);
|
|
exti_set_irq(1, 1);
|
|
|
|
|
|
/* Check that the pending bit in PR was set */
|
|
/* Check that the pending bit in PR was set */
|
|
- g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000002);
|
|
|
|
|
|
+ g_assert_cmphex(exti_readl(EXTI_PR1), ==, 0x00000002);
|
|
/* Check that the interrupt is pending in NVIC */
|
|
/* Check that the interrupt is pending in NVIC */
|
|
g_assert_true(check_nvic_pending(EXTI1_IRQ));
|
|
g_assert_true(check_nvic_pending(EXTI1_IRQ));
|
|
|
|
|
|
@@ -491,7 +491,7 @@ static void test_interrupt(void)
|
|
exti_writel(EXTI_PR1, 0x00000002);
|
|
exti_writel(EXTI_PR1, 0x00000002);
|
|
|
|
|
|
/* Check that the write in PR was effective */
|
|
/* Check that the write in PR was effective */
|
|
- g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
|
|
|
|
|
|
+ g_assert_cmphex(exti_readl(EXTI_PR1), ==, 0x00000000);
|
|
/* Check that the interrupt is still pending in the NVIC */
|
|
/* Check that the interrupt is still pending in the NVIC */
|
|
g_assert_true(check_nvic_pending(EXTI1_IRQ));
|
|
g_assert_true(check_nvic_pending(EXTI1_IRQ));
|
|
|
|
|
|
@@ -509,7 +509,7 @@ static void test_orred_interrupts(void)
|
|
*/
|
|
*/
|
|
enable_nvic_irq(EXTI5_9_IRQ);
|
|
enable_nvic_irq(EXTI5_9_IRQ);
|
|
/* Check that there are no interrupts already pending in PR */
|
|
/* Check that there are no interrupts already pending in PR */
|
|
- g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
|
|
|
|
|
|
+ g_assert_cmphex(exti_readl(EXTI_PR1), ==, 0x00000000);
|
|
/* Check that this specific interrupt isn't pending in NVIC */
|
|
/* Check that this specific interrupt isn't pending in NVIC */
|
|
g_assert_false(check_nvic_pending(EXTI5_9_IRQ));
|
|
g_assert_false(check_nvic_pending(EXTI5_9_IRQ));
|
|
|
|
|
|
@@ -522,11 +522,11 @@ static void test_orred_interrupts(void)
|
|
/* Raise GPIO line i, check that the interrupt is pending */
|
|
/* Raise GPIO line i, check that the interrupt is pending */
|
|
for (unsigned i = 5; i < 10; i++) {
|
|
for (unsigned i = 5; i < 10; i++) {
|
|
exti_set_irq(i, 1);
|
|
exti_set_irq(i, 1);
|
|
- g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 1 << i);
|
|
|
|
|
|
+ g_assert_cmphex(exti_readl(EXTI_PR1), ==, 1 << i);
|
|
g_assert_true(check_nvic_pending(EXTI5_9_IRQ));
|
|
g_assert_true(check_nvic_pending(EXTI5_9_IRQ));
|
|
|
|
|
|
exti_writel(EXTI_PR1, 1 << i);
|
|
exti_writel(EXTI_PR1, 1 << i);
|
|
- g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
|
|
|
|
|
|
+ g_assert_cmphex(exti_readl(EXTI_PR1), ==, 0x00000000);
|
|
g_assert_true(check_nvic_pending(EXTI5_9_IRQ));
|
|
g_assert_true(check_nvic_pending(EXTI5_9_IRQ));
|
|
|
|
|
|
unpend_nvic_irq(EXTI5_9_IRQ);
|
|
unpend_nvic_irq(EXTI5_9_IRQ);
|