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@@ -1161,6 +1161,9 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
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kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
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kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
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env->msr_ia32_misc_enable);
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env->msr_ia32_misc_enable);
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}
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}
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+ if (has_msr_bndcfgs) {
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+ kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs);
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+ }
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#ifdef TARGET_X86_64
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#ifdef TARGET_X86_64
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if (lm_capable_kernel) {
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if (lm_capable_kernel) {
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kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
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kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
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@@ -1224,9 +1227,6 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
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if (cpu->hyperv_vapic) {
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if (cpu->hyperv_vapic) {
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kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE, 0);
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kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE, 0);
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}
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}
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- if (has_msr_bndcfgs) {
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- kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs);
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- }
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/* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
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/* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
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* kvm_put_msr_feature_control. */
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* kvm_put_msr_feature_control. */
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