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@@ -248,11 +248,15 @@ void helper_ld_asi(int asi, int size, int sign)
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break;
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break;
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case 4: /* read MMU regs */
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case 4: /* read MMU regs */
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{
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{
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- int reg = (T0 >> 8) & 0xf;
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+ int reg = (T0 >> 8) & 0x1f;
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ret = env->mmuregs[reg];
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ret = env->mmuregs[reg];
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if (reg == 3) /* Fault status cleared on read */
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if (reg == 3) /* Fault status cleared on read */
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- env->mmuregs[reg] = 0;
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+ env->mmuregs[3] = 0;
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+ else if (reg == 0x13) /* Fault status read */
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+ ret = env->mmuregs[3];
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+ else if (reg == 0x14) /* Fault address read */
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+ ret = env->mmuregs[4];
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DPRINTF_MMU("mmu_read: reg[%d] = 0x%08x\n", reg, ret);
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DPRINTF_MMU("mmu_read: reg[%d] = 0x%08x\n", reg, ret);
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}
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}
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break;
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break;
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@@ -493,17 +497,18 @@ void helper_st_asi(int asi, int size)
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}
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}
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case 4: /* write MMU regs */
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case 4: /* write MMU regs */
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{
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{
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- int reg = (T0 >> 8) & 0xf;
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+ int reg = (T0 >> 8) & 0x1f;
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uint32_t oldreg;
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uint32_t oldreg;
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oldreg = env->mmuregs[reg];
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oldreg = env->mmuregs[reg];
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switch(reg) {
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switch(reg) {
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case 0:
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case 0:
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- env->mmuregs[reg] &= ~(MMU_E | MMU_NF | env->mmu_bm);
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- env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF | env->mmu_bm);
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+ env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
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+ (T1 & 0x00ffffff);
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// Mappings generated during no-fault mode or MMU
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// Mappings generated during no-fault mode or MMU
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// disabled mode are invalid in normal mode
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// disabled mode are invalid in normal mode
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- if (oldreg != env->mmuregs[reg])
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+ if ((oldreg & (MMU_E | MMU_NF | env->mmu_bm)) !=
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+ (env->mmuregs[reg] & (MMU_E | MMU_NF | env->mmu_bm)))
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tlb_flush(env, 1);
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tlb_flush(env, 1);
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break;
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break;
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case 2:
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case 2:
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@@ -517,6 +522,12 @@ void helper_st_asi(int asi, int size)
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case 3:
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case 3:
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case 4:
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case 4:
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break;
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break;
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+ case 0x13:
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+ env->mmuregs[3] = T1;
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+ break;
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+ case 0x14:
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+ env->mmuregs[4] = T1;
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+ break;
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default:
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default:
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env->mmuregs[reg] = T1;
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env->mmuregs[reg] = T1;
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break;
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break;
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