|
@@ -68,6 +68,7 @@
|
|
#define UCR2_RXEN (1<<1) /* Receiver enable */
|
|
#define UCR2_RXEN (1<<1) /* Receiver enable */
|
|
#define UCR2_SRST (1<<0) /* Reset complete */
|
|
#define UCR2_SRST (1<<0) /* Reset complete */
|
|
|
|
|
|
|
|
+#define UCR4_DREN BIT(0) /* Receive Data Ready interrupt enable */
|
|
#define UCR4_TCEN BIT(3) /* TX complete interrupt enable */
|
|
#define UCR4_TCEN BIT(3) /* TX complete interrupt enable */
|
|
|
|
|
|
#define UTS1_TXEMPTY (1<<6)
|
|
#define UTS1_TXEMPTY (1<<6)
|