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@@ -53,14 +53,20 @@ struct kvm_regs {
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struct user_fpsimd_state fp_regs;
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};
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-/* Supported Processor Types */
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+/*
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+ * Supported CPU Targets - Adding a new target type is not recommended,
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+ * unless there are some special registers not supported by the
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+ * genericv8 syreg table.
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+ */
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#define KVM_ARM_TARGET_AEM_V8 0
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#define KVM_ARM_TARGET_FOUNDATION_V8 1
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#define KVM_ARM_TARGET_CORTEX_A57 2
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#define KVM_ARM_TARGET_XGENE_POTENZA 3
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#define KVM_ARM_TARGET_CORTEX_A53 4
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+/* Generic ARM v8 target */
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+#define KVM_ARM_TARGET_GENERIC_V8 5
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-#define KVM_ARM_NUM_TARGETS 5
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+#define KVM_ARM_NUM_TARGETS 6
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/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
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#define KVM_ARM_DEVICE_TYPE_SHIFT 0
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@@ -100,12 +106,39 @@ struct kvm_sregs {
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struct kvm_fpu {
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};
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+/*
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+ * See v8 ARM ARM D7.3: Debug Registers
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+ *
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+ * The architectural limit is 16 debug registers of each type although
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+ * in practice there are usually less (see ID_AA64DFR0_EL1).
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+ *
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+ * Although the control registers are architecturally defined as 32
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+ * bits wide we use a 64 bit structure here to keep parity with
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+ * KVM_GET/SET_ONE_REG behaviour which treats all system registers as
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+ * 64 bit values. It also allows for the possibility of the
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+ * architecture expanding the control registers without having to
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+ * change the userspace ABI.
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+ */
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+#define KVM_ARM_MAX_DBG_REGS 16
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struct kvm_guest_debug_arch {
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+ __u64 dbg_bcr[KVM_ARM_MAX_DBG_REGS];
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+ __u64 dbg_bvr[KVM_ARM_MAX_DBG_REGS];
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+ __u64 dbg_wcr[KVM_ARM_MAX_DBG_REGS];
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+ __u64 dbg_wvr[KVM_ARM_MAX_DBG_REGS];
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};
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struct kvm_debug_exit_arch {
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+ __u32 hsr;
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+ __u64 far; /* used for watchpoints */
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};
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+/*
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+ * Architecture specific defines for kvm_guest_debug->control
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+ */
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+
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+#define KVM_GUESTDBG_USE_SW_BP (1 << 16)
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+#define KVM_GUESTDBG_USE_HW (1 << 17)
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+
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struct kvm_sync_regs {
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};
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