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+// Copyright 2024, Linaro Limited
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+// Author(s): Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
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+// SPDX-License-Identifier: GPL-2.0-or-later
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+//
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+// PL011 QEMU Device Model
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+//
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+// This library implements a device model for the PrimeCell® UART (PL011)
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+// device in QEMU.
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+//
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+#![doc = include_str!("../README.md")]
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+//! # Library crate
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+//!
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+//! See [`PL011State`](crate::device::PL011State) for the device model type and
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+//! the [`registers`] module for register types.
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+
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+#![deny(
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+ rustdoc::broken_intra_doc_links,
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+ rustdoc::redundant_explicit_links,
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+ clippy::correctness,
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+ clippy::suspicious,
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+ clippy::complexity,
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+ clippy::perf,
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+ clippy::cargo,
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+ clippy::nursery,
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+ clippy::style,
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+ // restriction group
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+ clippy::dbg_macro,
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+ clippy::as_underscore,
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+ clippy::assertions_on_result_states,
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+ // pedantic group
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+ clippy::doc_markdown,
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+ clippy::borrow_as_ptr,
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+ clippy::cast_lossless,
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+ clippy::option_if_let_else,
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+ clippy::missing_const_for_fn,
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+ clippy::cognitive_complexity,
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+ clippy::missing_safety_doc,
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+ )]
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+
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+extern crate bilge;
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+extern crate bilge_impl;
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+extern crate qemu_api;
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+
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+pub mod device;
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+pub mod device_class;
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+pub mod memory_ops;
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+
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+pub const TYPE_PL011: &::core::ffi::CStr = c"pl011";
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+
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+/// Offset of each register from the base memory address of the device.
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+///
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+/// # Source
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+/// ARM DDI 0183G, Table 3-1 p.3-3
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+#[doc(alias = "offset")]
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+#[allow(non_camel_case_types)]
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+#[repr(u64)]
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+#[derive(Debug)]
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+pub enum RegisterOffset {
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+ /// Data Register
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+ ///
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+ /// A write to this register initiates the actual data transmission
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+ #[doc(alias = "UARTDR")]
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+ DR = 0x000,
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+ /// Receive Status Register or Error Clear Register
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+ #[doc(alias = "UARTRSR")]
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+ #[doc(alias = "UARTECR")]
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+ RSR = 0x004,
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+ /// Flag Register
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+ ///
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+ /// A read of this register shows if transmission is complete
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+ #[doc(alias = "UARTFR")]
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+ FR = 0x018,
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+ /// Fractional Baud Rate Register
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+ ///
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+ /// responsible for baud rate speed
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+ #[doc(alias = "UARTFBRD")]
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+ FBRD = 0x028,
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+ /// `IrDA` Low-Power Counter Register
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+ #[doc(alias = "UARTILPR")]
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+ ILPR = 0x020,
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+ /// Integer Baud Rate Register
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+ ///
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+ /// Responsible for baud rate speed
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+ #[doc(alias = "UARTIBRD")]
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+ IBRD = 0x024,
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+ /// line control register (data frame format)
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+ #[doc(alias = "UARTLCR_H")]
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+ LCR_H = 0x02C,
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+ /// Toggle UART, transmission or reception
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+ #[doc(alias = "UARTCR")]
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+ CR = 0x030,
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+ /// Interrupt FIFO Level Select Register
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+ #[doc(alias = "UARTIFLS")]
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+ FLS = 0x034,
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+ /// Interrupt Mask Set/Clear Register
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+ #[doc(alias = "UARTIMSC")]
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+ IMSC = 0x038,
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+ /// Raw Interrupt Status Register
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+ #[doc(alias = "UARTRIS")]
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+ RIS = 0x03C,
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+ /// Masked Interrupt Status Register
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+ #[doc(alias = "UARTMIS")]
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+ MIS = 0x040,
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+ /// Interrupt Clear Register
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+ #[doc(alias = "UARTICR")]
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+ ICR = 0x044,
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+ /// DMA control Register
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+ #[doc(alias = "UARTDMACR")]
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+ DMACR = 0x048,
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+ ///// Reserved, offsets `0x04C` to `0x07C`.
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+ //Reserved = 0x04C,
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+}
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+
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+impl core::convert::TryFrom<u64> for RegisterOffset {
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+ type Error = u64;
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+
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+ fn try_from(value: u64) -> Result<Self, Self::Error> {
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+ macro_rules! case {
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+ ($($discriminant:ident),*$(,)*) => {
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+ /* check that matching on all macro arguments compiles, which means we are not
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+ * missing any enum value; if the type definition ever changes this will stop
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+ * compiling.
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+ */
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+ const fn _assert_exhaustive(val: RegisterOffset) {
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+ match val {
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+ $(RegisterOffset::$discriminant => (),)*
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+ }
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+ }
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+
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+ match value {
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+ $(x if x == Self::$discriminant as u64 => Ok(Self::$discriminant),)*
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+ _ => Err(value),
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+ }
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+ }
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+ }
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+ case! { DR, RSR, FR, FBRD, ILPR, IBRD, LCR_H, CR, FLS, IMSC, RIS, MIS, ICR, DMACR }
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+ }
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+}
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+
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+pub mod registers {
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+ //! Device registers exposed as typed structs which are backed by arbitrary
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+ //! integer bitmaps. [`Data`], [`Control`], [`LineControl`], etc.
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+ //!
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+ //! All PL011 registers are essentially 32-bit wide, but are typed here as
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+ //! bitmaps with only the necessary width. That is, if a struct bitmap
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+ //! in this module is for example 16 bits long, it should be conceived
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+ //! as a 32-bit register where the unmentioned higher bits are always
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+ //! unused thus treated as zero when read or written.
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+ use bilge::prelude::*;
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+
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+ // TODO: FIFO Mode has different semantics
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+ /// Data Register, `UARTDR`
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+ ///
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+ /// The `UARTDR` register is the data register.
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+ ///
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+ /// For words to be transmitted:
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+ ///
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+ /// - if the FIFOs are enabled, data written to this location is pushed onto
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+ /// the transmit
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+ /// FIFO
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+ /// - if the FIFOs are not enabled, data is stored in the transmitter
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+ /// holding register (the
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+ /// bottom word of the transmit FIFO).
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+ ///
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+ /// The write operation initiates transmission from the UART. The data is
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+ /// prefixed with a start bit, appended with the appropriate parity bit
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+ /// (if parity is enabled), and a stop bit. The resultant word is then
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+ /// transmitted.
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+ ///
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+ /// For received words:
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+ ///
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+ /// - if the FIFOs are enabled, the data byte and the 4-bit status (break,
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+ /// frame, parity,
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+ /// and overrun) is pushed onto the 12-bit wide receive FIFO
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+ /// - if the FIFOs are not enabled, the data byte and status are stored in
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+ /// the receiving
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+ /// holding register (the bottom word of the receive FIFO).
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+ ///
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+ /// The received data byte is read by performing reads from the `UARTDR`
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+ /// register along with the corresponding status information. The status
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+ /// information can also be read by a read of the `UARTRSR/UARTECR`
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+ /// register.
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+ ///
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+ /// # Note
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+ ///
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+ /// You must disable the UART before any of the control registers are
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+ /// reprogrammed. When the UART is disabled in the middle of
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+ /// transmission or reception, it completes the current character before
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+ /// stopping.
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+ ///
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+ /// # Source
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+ /// ARM DDI 0183G 3.3.1 Data Register, UARTDR
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+ #[bitsize(16)]
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+ #[derive(Clone, Copy, DebugBits, FromBits)]
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+ #[doc(alias = "UARTDR")]
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+ pub struct Data {
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+ _reserved: u4,
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+ pub data: u8,
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+ pub framing_error: bool,
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+ pub parity_error: bool,
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+ pub break_error: bool,
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+ pub overrun_error: bool,
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+ }
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+
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+ // TODO: FIFO Mode has different semantics
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+ /// Receive Status Register / Error Clear Register, `UARTRSR/UARTECR`
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+ ///
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+ /// The UARTRSR/UARTECR register is the receive status register/error clear
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+ /// register. Receive status can also be read from the `UARTRSR`
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+ /// register. If the status is read from this register, then the status
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+ /// information for break, framing and parity corresponds to the
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+ /// data character read from the [Data register](Data), `UARTDR` prior to
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+ /// reading the UARTRSR register. The status information for overrun is
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+ /// set immediately when an overrun condition occurs.
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+ ///
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+ ///
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+ /// # Note
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+ /// The received data character must be read first from the [Data
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+ /// Register](Data), `UARTDR` before reading the error status associated
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+ /// with that data character from the `UARTRSR` register. This read
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+ /// sequence cannot be reversed, because the `UARTRSR` register is
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+ /// updated only when a read occurs from the `UARTDR` register. However,
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+ /// the status information can also be obtained by reading the `UARTDR`
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+ /// register
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+ ///
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+ /// # Source
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+ /// ARM DDI 0183G 3.3.2 Receive Status Register/Error Clear Register,
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+ /// UARTRSR/UARTECR
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+ #[bitsize(8)]
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+ #[derive(Clone, Copy, DebugBits, FromBits)]
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+ pub struct ReceiveStatusErrorClear {
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+ pub framing_error: bool,
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+ pub parity_error: bool,
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+ pub break_error: bool,
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+ pub overrun_error: bool,
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+ _reserved_unpredictable: u4,
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+ }
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+
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+ impl ReceiveStatusErrorClear {
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+ pub fn reset(&mut self) {
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+ // All the bits are cleared to 0 on reset.
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+ *self = 0.into();
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+ }
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+ }
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+
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+ impl Default for ReceiveStatusErrorClear {
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+ fn default() -> Self {
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+ 0.into()
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+ }
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+ }
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+
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+ #[bitsize(16)]
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+ #[derive(Clone, Copy, DebugBits, FromBits)]
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+ /// Flag Register, `UARTFR`
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+ #[doc(alias = "UARTFR")]
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+ pub struct Flags {
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+ /// CTS Clear to send. This bit is the complement of the UART clear to
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+ /// send, `nUARTCTS`, modem status input. That is, the bit is 1
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+ /// when `nUARTCTS` is LOW.
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+ pub clear_to_send: bool,
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+ /// DSR Data set ready. This bit is the complement of the UART data set
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+ /// ready, `nUARTDSR`, modem status input. That is, the bit is 1 when
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+ /// `nUARTDSR` is LOW.
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+ pub data_set_ready: bool,
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+ /// DCD Data carrier detect. This bit is the complement of the UART data
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+ /// carrier detect, `nUARTDCD`, modem status input. That is, the bit is
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+ /// 1 when `nUARTDCD` is LOW.
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+ pub data_carrier_detect: bool,
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+ /// BUSY UART busy. If this bit is set to 1, the UART is busy
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+ /// transmitting data. This bit remains set until the complete
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+ /// byte, including all the stop bits, has been sent from the
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+ /// shift register. This bit is set as soon as the transmit FIFO
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+ /// becomes non-empty, regardless of whether the UART is enabled
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+ /// or not.
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+ pub busy: bool,
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+ /// RXFE Receive FIFO empty. The meaning of this bit depends on the
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+ /// state of the FEN bit in the UARTLCR_H register. If the FIFO
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+ /// is disabled, this bit is set when the receive holding
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+ /// register is empty. If the FIFO is enabled, the RXFE bit is
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+ /// set when the receive FIFO is empty.
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+ pub receive_fifo_empty: bool,
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+ /// TXFF Transmit FIFO full. The meaning of this bit depends on the
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+ /// state of the FEN bit in the UARTLCR_H register. If the FIFO
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+ /// is disabled, this bit is set when the transmit holding
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+ /// register is full. If the FIFO is enabled, the TXFF bit is
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+ /// set when the transmit FIFO is full.
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+ pub transmit_fifo_full: bool,
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+ /// RXFF Receive FIFO full. The meaning of this bit depends on the state
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+ /// of the FEN bit in the UARTLCR_H register. If the FIFO is
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+ /// disabled, this bit is set when the receive holding register
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+ /// is full. If the FIFO is enabled, the RXFF bit is set when
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+ /// the receive FIFO is full.
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+ pub receive_fifo_full: bool,
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+ /// Transmit FIFO empty. The meaning of this bit depends on the state of
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+ /// the FEN bit in the [Line Control register](LineControl),
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+ /// `UARTLCR_H`. If the FIFO is disabled, this bit is set when the
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+ /// transmit holding register is empty. If the FIFO is enabled,
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+ /// the TXFE bit is set when the transmit FIFO is empty. This
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+ /// bit does not indicate if there is data in the transmit shift
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+ /// register.
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+ pub transmit_fifo_empty: bool,
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+ /// `RI`, is `true` when `nUARTRI` is `LOW`.
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+ pub ring_indicator: bool,
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+ _reserved_zero_no_modify: u7,
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+ }
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+
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+ impl Flags {
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+ pub fn reset(&mut self) {
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+ // After reset TXFF, RXFF, and BUSY are 0, and TXFE and RXFE are 1
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+ self.set_receive_fifo_full(false);
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+ self.set_transmit_fifo_full(false);
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+ self.set_busy(false);
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+ self.set_receive_fifo_empty(true);
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+ self.set_transmit_fifo_empty(true);
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+ }
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+ }
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+
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+ impl Default for Flags {
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+ fn default() -> Self {
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+ let mut ret: Self = 0.into();
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+ ret.reset();
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+ ret
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+ }
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+ }
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+
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+ #[bitsize(16)]
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+ #[derive(Clone, Copy, DebugBits, FromBits)]
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+ /// Line Control Register, `UARTLCR_H`
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+ #[doc(alias = "UARTLCR_H")]
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+ pub struct LineControl {
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+ /// 15:8 - Reserved, do not modify, read as zero.
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+ _reserved_zero_no_modify: u8,
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+ /// 7 SPS Stick parity select.
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+ /// 0 = stick parity is disabled
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+ /// 1 = either:
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+ /// • if the EPS bit is 0 then the parity bit is transmitted and checked
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+ /// as a 1 • if the EPS bit is 1 then the parity bit is
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+ /// transmitted and checked as a 0. This bit has no effect when
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+ /// the PEN bit disables parity checking and generation. See Table 3-11
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+ /// on page 3-14 for the parity truth table.
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+ pub sticky_parity: bool,
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+ /// WLEN Word length. These bits indicate the number of data bits
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+ /// transmitted or received in a frame as follows: b11 = 8 bits
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+ /// b10 = 7 bits
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+ /// b01 = 6 bits
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+ /// b00 = 5 bits.
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+ pub word_length: WordLength,
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+ /// FEN Enable FIFOs:
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+ /// 0 = FIFOs are disabled (character mode) that is, the FIFOs become
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+ /// 1-byte-deep holding registers 1 = transmit and receive FIFO
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+ /// buffers are enabled (FIFO mode).
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+ pub fifos_enabled: Mode,
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+ /// 3 STP2 Two stop bits select. If this bit is set to 1, two stop bits
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+ /// are transmitted at the end of the frame. The receive
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+ /// logic does not check for two stop bits being received.
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+ pub two_stops_bits: bool,
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+ /// EPS Even parity select. Controls the type of parity the UART uses
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+ /// during transmission and reception:
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+ /// - 0 = odd parity. The UART generates or checks for an odd number of
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+ /// 1s in the data and parity bits.
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+ /// - 1 = even parity. The UART generates or checks for an even number
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+ /// of 1s in the data and parity bits.
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+ /// This bit has no effect when the `PEN` bit disables parity checking
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+ /// and generation. See Table 3-11 on page 3-14 for the parity
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+ /// truth table.
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+ pub parity: Parity,
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+ /// 1 PEN Parity enable:
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+ ///
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+ /// - 0 = parity is disabled and no parity bit added to the data frame
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+ /// - 1 = parity checking and generation is enabled.
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+ ///
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+ /// See Table 3-11 on page 3-14 for the parity truth table.
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+ pub parity_enabled: bool,
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+ /// BRK Send break.
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+ ///
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+ /// If this bit is set to `1`, a low-level is continually output on the
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+ /// `UARTTXD` output, after completing transmission of the
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+ /// current character. For the proper execution of the break command,
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+ /// the software must set this bit for at least two complete
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+ /// frames. For normal use, this bit must be cleared to `0`.
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+ pub send_break: bool,
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+ }
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+
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+ impl LineControl {
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+ pub fn reset(&mut self) {
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+ // All the bits are cleared to 0 when reset.
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+ *self = 0.into();
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|
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+ }
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|
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+ }
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+
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|
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+ impl Default for LineControl {
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+ fn default() -> Self {
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+ 0.into()
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|
|
+ }
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+ }
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+
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|
+ #[bitsize(1)]
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+ #[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)]
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+ /// `EPS` "Even parity select", field of [Line Control
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|
|
+ /// register](LineControl).
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|
+ pub enum Parity {
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+ /// - 0 = odd parity. The UART generates or checks for an odd number of
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|
+ /// 1s in the data and parity bits.
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+ Odd = 0,
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|
+ /// - 1 = even parity. The UART generates or checks for an even number
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|
+ /// of 1s in the data and parity bits.
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|
+ Even = 1,
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|
+ }
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+
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+ #[bitsize(1)]
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+ #[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)]
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+ /// `FEN` "Enable FIFOs" or Device mode, field of [Line Control
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|
+ /// register](LineControl).
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+ pub enum Mode {
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+ /// 0 = FIFOs are disabled (character mode) that is, the FIFOs become
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+ /// 1-byte-deep holding registers
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|
+ Character = 0,
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|
+ /// 1 = transmit and receive FIFO buffers are enabled (FIFO mode).
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+ FIFO = 1,
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|
|
+ }
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+
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+ impl From<Mode> for bool {
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|
+ fn from(val: Mode) -> Self {
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|
|
+ matches!(val, Mode::FIFO)
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|
|
+ }
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|
+ }
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|
+
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|
|
+ #[bitsize(2)]
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+ #[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)]
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|
+ /// `WLEN` Word length, field of [Line Control register](LineControl).
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|
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+ ///
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|
+ /// These bits indicate the number of data bits transmitted or received in a
|
|
|
+ /// frame as follows:
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|
|
+ pub enum WordLength {
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|
|
+ /// b11 = 8 bits
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|
+ _8Bits = 0b11,
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|
+ /// b10 = 7 bits
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|
+ _7Bits = 0b10,
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|
+ /// b01 = 6 bits
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+ _6Bits = 0b01,
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|
+ /// b00 = 5 bits.
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|
+ _5Bits = 0b00,
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|
|
+ }
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|
|
+
|
|
|
+ /// Control Register, `UARTCR`
|
|
|
+ ///
|
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|
+ /// The `UARTCR` register is the control register. All the bits are cleared
|
|
|
+ /// to `0` on reset except for bits `9` and `8` that are set to `1`.
|
|
|
+ ///
|
|
|
+ /// # Source
|
|
|
+ /// ARM DDI 0183G, 3.3.8 Control Register, `UARTCR`, Table 3-12
|
|
|
+ #[bitsize(16)]
|
|
|
+ #[doc(alias = "UARTCR")]
|
|
|
+ #[derive(Clone, Copy, DebugBits, FromBits)]
|
|
|
+ pub struct Control {
|
|
|
+ /// `UARTEN` UART enable: 0 = UART is disabled. If the UART is disabled
|
|
|
+ /// in the middle of transmission or reception, it completes the current
|
|
|
+ /// character before stopping. 1 = the UART is enabled. Data
|
|
|
+ /// transmission and reception occurs for either UART signals or SIR
|
|
|
+ /// signals depending on the setting of the SIREN bit.
|
|
|
+ pub enable_uart: bool,
|
|
|
+ /// `SIREN` `SIR` enable: 0 = IrDA SIR ENDEC is disabled. `nSIROUT`
|
|
|
+ /// remains LOW (no light pulse generated), and signal transitions on
|
|
|
+ /// SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is
|
|
|
+ /// transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH,
|
|
|
+ /// in the marking state. Signal transitions on UARTRXD or modem status
|
|
|
+ /// inputs have no effect. This bit has no effect if the UARTEN bit
|
|
|
+ /// disables the UART.
|
|
|
+ pub enable_sir: bool,
|
|
|
+ /// `SIRLP` SIR low-power IrDA mode. This bit selects the IrDA encoding
|
|
|
+ /// mode. If this bit is cleared to 0, low-level bits are transmitted as
|
|
|
+ /// an active high pulse with a width of 3/ 16th of the bit period. If
|
|
|
+ /// this bit is set to 1, low-level bits are transmitted with a pulse
|
|
|
+ /// width that is 3 times the period of the IrLPBaud16 input signal,
|
|
|
+ /// regardless of the selected bit rate. Setting this bit uses less
|
|
|
+ /// power, but might reduce transmission distances.
|
|
|
+ pub sir_lowpower_irda_mode: u1,
|
|
|
+ /// Reserved, do not modify, read as zero.
|
|
|
+ _reserved_zero_no_modify: u4,
|
|
|
+ /// `LBE` Loopback enable. If this bit is set to 1 and the SIREN bit is
|
|
|
+ /// set to 1 and the SIRTEST bit in the Test Control register, UARTTCR
|
|
|
+ /// on page 4-5 is set to 1, then the nSIROUT path is inverted, and fed
|
|
|
+ /// through to the SIRIN path. The SIRTEST bit in the test register must
|
|
|
+ /// be set to 1 to override the normal half-duplex SIR operation. This
|
|
|
+ /// must be the requirement for accessing the test registers during
|
|
|
+ /// normal operation, and SIRTEST must be cleared to 0 when loopback
|
|
|
+ /// testing is finished. This feature reduces the amount of external
|
|
|
+ /// coupling required during system test. If this bit is set to 1, and
|
|
|
+ /// the SIRTEST bit is set to 0, the UARTTXD path is fed through to the
|
|
|
+ /// UARTRXD path. In either SIR mode or UART mode, when this bit is set,
|
|
|
+ /// the modem outputs are also fed through to the modem inputs. This bit
|
|
|
+ /// is cleared to 0 on reset, to disable loopback.
|
|
|
+ pub enable_loopback: bool,
|
|
|
+ /// `TXE` Transmit enable. If this bit is set to 1, the transmit section
|
|
|
+ /// of the UART is enabled. Data transmission occurs for either UART
|
|
|
+ /// signals, or SIR signals depending on the setting of the SIREN bit.
|
|
|
+ /// When the UART is disabled in the middle of transmission, it
|
|
|
+ /// completes the current character before stopping.
|
|
|
+ pub enable_transmit: bool,
|
|
|
+ /// `RXE` Receive enable. If this bit is set to 1, the receive section
|
|
|
+ /// of the UART is enabled. Data reception occurs for either UART
|
|
|
+ /// signals or SIR signals depending on the setting of the SIREN bit.
|
|
|
+ /// When the UART is disabled in the middle of reception, it completes
|
|
|
+ /// the current character before stopping.
|
|
|
+ pub enable_receive: bool,
|
|
|
+ /// `DTR` Data transmit ready. This bit is the complement of the UART
|
|
|
+ /// data transmit ready, `nUARTDTR`, modem status output. That is, when
|
|
|
+ /// the bit is programmed to a 1 then `nUARTDTR` is LOW.
|
|
|
+ pub data_transmit_ready: bool,
|
|
|
+ /// `RTS` Request to send. This bit is the complement of the UART
|
|
|
+ /// request to send, `nUARTRTS`, modem status output. That is, when the
|
|
|
+ /// bit is programmed to a 1 then `nUARTRTS` is LOW.
|
|
|
+ pub request_to_send: bool,
|
|
|
+ /// `Out1` This bit is the complement of the UART Out1 (`nUARTOut1`)
|
|
|
+ /// modem status output. That is, when the bit is programmed to a 1 the
|
|
|
+ /// output is 0. For DTE this can be used as Data Carrier Detect (DCD).
|
|
|
+ pub out_1: bool,
|
|
|
+ /// `Out2` This bit is the complement of the UART Out2 (`nUARTOut2`)
|
|
|
+ /// modem status output. That is, when the bit is programmed to a 1, the
|
|
|
+ /// output is 0. For DTE this can be used as Ring Indicator (RI).
|
|
|
+ pub out_2: bool,
|
|
|
+ /// `RTSEn` RTS hardware flow control enable. If this bit is set to 1,
|
|
|
+ /// RTS hardware flow control is enabled. Data is only requested when
|
|
|
+ /// there is space in the receive FIFO for it to be received.
|
|
|
+ pub rts_hardware_flow_control_enable: bool,
|
|
|
+ /// `CTSEn` CTS hardware flow control enable. If this bit is set to 1,
|
|
|
+ /// CTS hardware flow control is enabled. Data is only transmitted when
|
|
|
+ /// the `nUARTCTS` signal is asserted.
|
|
|
+ pub cts_hardware_flow_control_enable: bool,
|
|
|
+ }
|
|
|
+
|
|
|
+ impl Control {
|
|
|
+ pub fn reset(&mut self) {
|
|
|
+ *self = 0.into();
|
|
|
+ self.set_enable_receive(true);
|
|
|
+ self.set_enable_transmit(true);
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ impl Default for Control {
|
|
|
+ fn default() -> Self {
|
|
|
+ let mut ret: Self = 0.into();
|
|
|
+ ret.reset();
|
|
|
+ ret
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ /// Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC
|
|
|
+ pub const INT_OE: u32 = 1 << 10;
|
|
|
+ pub const INT_BE: u32 = 1 << 9;
|
|
|
+ pub const INT_PE: u32 = 1 << 8;
|
|
|
+ pub const INT_FE: u32 = 1 << 7;
|
|
|
+ pub const INT_RT: u32 = 1 << 6;
|
|
|
+ pub const INT_TX: u32 = 1 << 5;
|
|
|
+ pub const INT_RX: u32 = 1 << 4;
|
|
|
+ pub const INT_DSR: u32 = 1 << 3;
|
|
|
+ pub const INT_DCD: u32 = 1 << 2;
|
|
|
+ pub const INT_CTS: u32 = 1 << 1;
|
|
|
+ pub const INT_RI: u32 = 1 << 0;
|
|
|
+ pub const INT_E: u32 = INT_OE | INT_BE | INT_PE | INT_FE;
|
|
|
+ pub const INT_MS: u32 = INT_RI | INT_DSR | INT_DCD | INT_CTS;
|
|
|
+
|
|
|
+ #[repr(u32)]
|
|
|
+ pub enum Interrupt {
|
|
|
+ OE = 1 << 10,
|
|
|
+ BE = 1 << 9,
|
|
|
+ PE = 1 << 8,
|
|
|
+ FE = 1 << 7,
|
|
|
+ RT = 1 << 6,
|
|
|
+ TX = 1 << 5,
|
|
|
+ RX = 1 << 4,
|
|
|
+ DSR = 1 << 3,
|
|
|
+ DCD = 1 << 2,
|
|
|
+ CTS = 1 << 1,
|
|
|
+ RI = 1 << 0,
|
|
|
+ }
|
|
|
+
|
|
|
+ impl Interrupt {
|
|
|
+ pub const E: u32 = INT_OE | INT_BE | INT_PE | INT_FE;
|
|
|
+ pub const MS: u32 = INT_RI | INT_DSR | INT_DCD | INT_CTS;
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+// TODO: You must disable the UART before any of the control registers are
|
|
|
+// reprogrammed. When the UART is disabled in the middle of transmission or
|
|
|
+// reception, it completes the current character before stopping
|
Manos Pitsidianakis