serial: Remove ioregister parameter from serial_mm_init

All callers passed 1.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Avi Kivity <avi@redhat.com>

hw/mips_jazz.c

@@ -265,11 +265,11 @@ static void mips_jazz_init(MemoryRegion *address_space,
     /* Serial ports */
     if (serial_hds[0]) {
         serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0],
-                       1, DEVICE_NATIVE_ENDIAN);
+                       DEVICE_NATIVE_ENDIAN);
     }
     if (serial_hds[1]) {
         serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1],
-                       1, DEVICE_NATIVE_ENDIAN);
+                       DEVICE_NATIVE_ENDIAN);
     }
 
     /* Parallel port */

hw/mips_malta.c

@@ -447,7 +447,7 @@ static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space,
     s->display = qemu_chr_new("fpga", "vc:320x200", malta_fpga_led_init);
 
     s->uart = serial_mm_init(base + 0x900, 3, uart_irq, 230400, uart_chr,
-                             1, DEVICE_NATIVE_ENDIAN);
+                             DEVICE_NATIVE_ENDIAN);
 
     malta_fpga_reset(s);
     qemu_register_reset(malta_fpga_reset, s);

hw/musicpal.c

@@ -1487,11 +1487,11 @@ static void musicpal_init(ram_addr_t ram_size,
 
     if (serial_hds[0]) {
         serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000,
-                       serial_hds[0], 1, DEVICE_NATIVE_ENDIAN);
+                       serial_hds[0], DEVICE_NATIVE_ENDIAN);
     }
     if (serial_hds[1]) {
         serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000,
-                       serial_hds[1], 1, DEVICE_NATIVE_ENDIAN);
+                       serial_hds[1], DEVICE_NATIVE_ENDIAN);
     }
 
     /* Register flash */

hw/omap_uart.c

@@ -61,7 +61,7 @@ struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
     s->fclk = fclk;
     s->irq = irq;
     s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16,
-                               chr ?: qemu_chr_new(label, "null", NULL), 1,
+                               chr ?: qemu_chr_new(label, "null", NULL),
                                DEVICE_NATIVE_ENDIAN);
     return s;
 }
@@ -178,6 +178,6 @@ void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr)
     /* TODO: Should reuse or destroy current s->serial */
     s->serial = serial_mm_init(s->base, 2, s->irq,
                                omap_clk_getrate(s->fclk) / 16,
-                               chr ?: qemu_chr_new("null", "null", NULL), 1,
+                               chr ?: qemu_chr_new("null", "null", NULL),
                                DEVICE_NATIVE_ENDIAN);
 }

hw/pc.h

@@ -17,8 +17,7 @@ SerialState *serial_init(int base, qemu_irq irq, int baudbase,
                          CharDriverState *chr);
 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
                              qemu_irq irq, int baudbase,
-                             CharDriverState *chr, int ioregister,
-                             enum device_endian);
+                             CharDriverState *chr, enum device_endian);
 static inline bool serial_isa_init(int index, CharDriverState *chr)
 {
     ISADevice *dev;

hw/petalogix_ml605_mmu.c

@@ -185,7 +185,7 @@ petalogix_ml605_init(ram_addr_t ram_size,
     }
 
     serial_mm_init(UART16550_BASEADDR + 0x1000, 2, irq[5], 115200,
-                   serial_hds[0], 1, DEVICE_LITTLE_ENDIAN);
+                   serial_hds[0], DEVICE_LITTLE_ENDIAN);
 
     /* 2 timers at irq 2 @ 100 Mhz.  */
     xilinx_timer_create(TIMER_BASEADDR, irq[2], 2, 100 * 1000000);

hw/ppc405_uc.c

@@ -2150,11 +2150,11 @@ CPUState *ppc405cr_init (MemoryRegion ram_memories[4],
     /* Serial ports */
     if (serial_hds[0] != NULL) {
         serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
-                       serial_hds[0], 1, DEVICE_BIG_ENDIAN);
+                       serial_hds[0], DEVICE_BIG_ENDIAN);
     }
     if (serial_hds[1] != NULL) {
         serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
-                       serial_hds[1], 1, DEVICE_BIG_ENDIAN);
+                       serial_hds[1], DEVICE_BIG_ENDIAN);
     }
     /* IIC controller */
     ppc405_i2c_init(0xef600500, pic[2]);
@@ -2505,11 +2505,11 @@ CPUState *ppc405ep_init (MemoryRegion ram_memories[2],
     /* Serial ports */
     if (serial_hds[0] != NULL) {
         serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
-                       serial_hds[0], 1, DEVICE_BIG_ENDIAN);
+                       serial_hds[0], DEVICE_BIG_ENDIAN);
     }
     if (serial_hds[1] != NULL) {
         serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
-                       serial_hds[1], 1, DEVICE_BIG_ENDIAN);
+                       serial_hds[1], DEVICE_BIG_ENDIAN);
     }
     /* OCM */
     ppc405_ocm_init(env);

hw/ppc440.c

@@ -93,11 +93,11 @@ CPUState *ppc440ep_init(ram_addr_t *ram_size, PCIBus **pcip,
 
     if (serial_hds[0] != NULL) {
         serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
-                       serial_hds[0], 1, DEVICE_BIG_ENDIAN);
+                       serial_hds[0], DEVICE_BIG_ENDIAN);
     }
     if (serial_hds[1] != NULL) {
         serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
-                       serial_hds[1], 1, DEVICE_BIG_ENDIAN);
+                       serial_hds[1], DEVICE_BIG_ENDIAN);
     }
 
     return env;

hw/ppce500_mpc8544ds.c

@@ -276,13 +276,13 @@ static void mpc8544ds_init(ram_addr_t ram_size,
     if (serial_hds[0]) {
         serial_mm_init(MPC8544_SERIAL0_REGS_BASE,
                        0, mpic[12+26], 399193,
-                       serial_hds[0], 1, DEVICE_BIG_ENDIAN);
+                       serial_hds[0], DEVICE_BIG_ENDIAN);
     }
 
     if (serial_hds[1]) {
         serial_mm_init(MPC8544_SERIAL1_REGS_BASE,
                        0, mpic[12+26], 399193,
-                       serial_hds[0], 1, DEVICE_BIG_ENDIAN);
+                       serial_hds[0], DEVICE_BIG_ENDIAN);
     }
 
     /* General Utility device */

hw/pxa2xx.c

@@ -2117,7 +2117,7 @@ PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision)
         if (serial_hds[i]) {
             serial_mm_init(pxa270_serial[i].io_base, 2,
                            qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn),
-                           14857000 / 16, serial_hds[i], 1,
+                           14857000 / 16, serial_hds[i],
                            DEVICE_NATIVE_ENDIAN);
         } else {
             break;
@@ -2249,7 +2249,7 @@ PXA2xxState *pxa255_init(unsigned int sdram_size)
         if (serial_hds[i]) {
             serial_mm_init(pxa255_serial[i].io_base, 2,
                            qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn),
-                           14745600 / 16, serial_hds[i], 1,
+                           14745600 / 16, serial_hds[i],
                            DEVICE_NATIVE_ENDIAN);
         } else {
             break;

hw/serial.c

@@ -857,8 +857,7 @@ static const MemoryRegionOps serial_mm_ops[3] = {
 
 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
                              qemu_irq irq, int baudbase,
-                             CharDriverState *chr, int ioregister,
-                             enum device_endian end)
+                             CharDriverState *chr, enum device_endian end)
 {
     SerialState *s;
 
@@ -874,9 +873,8 @@ SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
 
     memory_region_init_io(&s->io, &serial_mm_ops[end], s,
                           "serial", 8 << it_shift);
-    if (ioregister) {
-        memory_region_add_subregion(get_system_memory(), base, &s->io);
-    }
+    memory_region_add_subregion(get_system_memory(), base, &s->io);
+
     serial_update_msl(s);
     return s;
 }

hw/sm501.c

@@ -1442,7 +1442,7 @@ void sm501_init(uint32_t base, uint32_t local_mem_bytes, qemu_irq irq,
     if (chr) {
         serial_mm_init(base + MMIO_BASE_OFFSET + SM501_UART0, 2,
                        NULL, /* TODO : chain irq to IRL */
-                       115200, chr, 1, DEVICE_NATIVE_ENDIAN);
+                       115200, chr, DEVICE_NATIVE_ENDIAN);
     }
 
     /* create qemu graphic console */

hw/sun4u.c

@@ -771,7 +771,7 @@ static void sun4uv_init(ram_addr_t RAM_size,
     i = 0;
     if (hwdef->console_serial_base) {
         serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200,
-                       serial_hds[i], 1, DEVICE_BIG_ENDIAN);
+                       serial_hds[i], DEVICE_BIG_ENDIAN);
         i++;
     }
     for(; i < MAX_SERIAL_PORTS; i++) {

hw/virtex_ml507.c

@@ -227,7 +227,7 @@ static void virtex_init(ram_addr_t ram_size,
     }
 
     serial_mm_init(0x83e01003ULL, 2, irq[9], 115200, serial_hds[0],
-                   1, DEVICE_LITTLE_ENDIAN);
+                   DEVICE_LITTLE_ENDIAN);
 
     /* 2 timers at irq 2 @ 62 Mhz.  */
     xilinx_timer_create(0x83c00000, irq[3], 2, 62 * 1000000);