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@@ -14,72 +14,202 @@
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#include "hw/registerfields.h"
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#include "qapi/error.h"
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-/* INTC Registers */
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-REG32(GICINT128_EN, 0x1000)
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-REG32(GICINT128_STATUS, 0x1004)
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-REG32(GICINT129_EN, 0x1100)
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-REG32(GICINT129_STATUS, 0x1104)
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-REG32(GICINT130_EN, 0x1200)
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-REG32(GICINT130_STATUS, 0x1204)
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-REG32(GICINT131_EN, 0x1300)
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-REG32(GICINT131_STATUS, 0x1304)
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-REG32(GICINT132_EN, 0x1400)
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-REG32(GICINT132_STATUS, 0x1404)
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-REG32(GICINT133_EN, 0x1500)
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-REG32(GICINT133_STATUS, 0x1504)
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-REG32(GICINT134_EN, 0x1600)
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-REG32(GICINT134_STATUS, 0x1604)
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-REG32(GICINT135_EN, 0x1700)
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-REG32(GICINT135_STATUS, 0x1704)
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-REG32(GICINT136_EN, 0x1800)
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-REG32(GICINT136_STATUS, 0x1804)
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-
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-#define GICINT_STATUS_BASE R_GICINT128_STATUS
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-
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-static void aspeed_intc_update(AspeedINTCState *s, int irq, int level)
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+/*
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+ * INTC Registers
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+ *
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+ * values below are offset by - 0x1000 from datasheet
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+ * because its memory region is start at 0x1000
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+ *
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+ */
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+REG32(GICINT128_EN, 0x000)
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+REG32(GICINT128_STATUS, 0x004)
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+REG32(GICINT129_EN, 0x100)
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+REG32(GICINT129_STATUS, 0x104)
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+REG32(GICINT130_EN, 0x200)
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+REG32(GICINT130_STATUS, 0x204)
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+REG32(GICINT131_EN, 0x300)
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+REG32(GICINT131_STATUS, 0x304)
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+REG32(GICINT132_EN, 0x400)
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+REG32(GICINT132_STATUS, 0x404)
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+REG32(GICINT133_EN, 0x500)
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+REG32(GICINT133_STATUS, 0x504)
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+REG32(GICINT134_EN, 0x600)
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+REG32(GICINT134_STATUS, 0x604)
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+REG32(GICINT135_EN, 0x700)
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+REG32(GICINT135_STATUS, 0x704)
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+REG32(GICINT136_EN, 0x800)
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+REG32(GICINT136_STATUS, 0x804)
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+REG32(GICINT192_201_EN, 0xB00)
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+REG32(GICINT192_201_STATUS, 0xB04)
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+
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+/*
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+ * INTCIO Registers
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+ *
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+ * values below are offset by - 0x100 from datasheet
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+ * because its memory region is start at 0x100
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+ *
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+ */
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+REG32(GICINT192_EN, 0x00)
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+REG32(GICINT192_STATUS, 0x04)
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+REG32(GICINT193_EN, 0x10)
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+REG32(GICINT193_STATUS, 0x14)
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+REG32(GICINT194_EN, 0x20)
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+REG32(GICINT194_STATUS, 0x24)
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+REG32(GICINT195_EN, 0x30)
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+REG32(GICINT195_STATUS, 0x34)
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+REG32(GICINT196_EN, 0x40)
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+REG32(GICINT196_STATUS, 0x44)
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+REG32(GICINT197_EN, 0x50)
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+REG32(GICINT197_STATUS, 0x54)
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+
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+static const AspeedINTCIRQ *aspeed_intc_get_irq(AspeedINTCClass *aic,
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+ uint32_t reg)
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+{
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+ int i;
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+
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+ for (i = 0; i < aic->irq_table_count; i++) {
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+ if (aic->irq_table[i].enable_reg == reg ||
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+ aic->irq_table[i].status_reg == reg) {
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+ return &aic->irq_table[i];
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+ }
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+ }
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+
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+ /*
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+ * Invalid reg.
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+ */
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+ g_assert_not_reached();
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+}
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+
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+/*
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+ * Update the state of an interrupt controller pin by setting
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+ * the specified output pin to the given level.
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+ * The input pin index should be between 0 and the number of input pins.
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+ * The output pin index should be between 0 and the number of output pins.
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+ */
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+static void aspeed_intc_update(AspeedINTCState *s, int inpin_idx,
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+ int outpin_idx, int level)
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{
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AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
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+ const char *name = object_get_typename(OBJECT(s));
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- if (irq >= aic->num_ints) {
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- qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n",
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- __func__, irq);
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- return;
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+ assert((outpin_idx < aic->num_outpins) && (inpin_idx < aic->num_inpins));
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+
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+ trace_aspeed_intc_update_irq(name, inpin_idx, outpin_idx, level);
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+ qemu_set_irq(s->output_pins[outpin_idx], level);
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+}
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+
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+static void aspeed_intc_set_irq_handler(AspeedINTCState *s,
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+ const AspeedINTCIRQ *intc_irq,
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+ uint32_t select)
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+{
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+ const char *name = object_get_typename(OBJECT(s));
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+ uint32_t status_reg;
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+ int outpin_idx;
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+ int inpin_idx;
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+
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+ status_reg = intc_irq->status_reg;
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+ outpin_idx = intc_irq->outpin_idx;
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+ inpin_idx = intc_irq->inpin_idx;
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+
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+ if (s->mask[inpin_idx] || s->regs[status_reg]) {
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+ /*
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+ * a. mask is not 0 means in ISR mode
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+ * sources interrupt routine are executing.
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+ * b. status register value is not 0 means previous
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+ * source interrupt does not be executed, yet.
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+ *
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+ * save source interrupt to pending variable.
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+ */
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+ s->pending[inpin_idx] |= select;
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+ trace_aspeed_intc_pending_irq(name, inpin_idx, s->pending[inpin_idx]);
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+ } else {
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+ /*
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+ * notify firmware which source interrupt are coming
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+ * by setting status register
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+ */
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+ s->regs[status_reg] = select;
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+ trace_aspeed_intc_trigger_irq(name, inpin_idx, outpin_idx,
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+ s->regs[status_reg]);
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+ aspeed_intc_update(s, inpin_idx, outpin_idx, 1);
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}
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+}
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+
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+static void aspeed_intc_set_irq_handler_multi_outpins(AspeedINTCState *s,
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+ const AspeedINTCIRQ *intc_irq, uint32_t select)
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+{
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+ const char *name = object_get_typename(OBJECT(s));
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+ uint32_t status_reg;
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+ int num_outpins;
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+ int outpin_idx;
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+ int inpin_idx;
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+ int i;
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- trace_aspeed_intc_update_irq(irq, level);
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- qemu_set_irq(s->output_pins[irq], level);
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+ num_outpins = intc_irq->num_outpins;
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+ status_reg = intc_irq->status_reg;
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+ outpin_idx = intc_irq->outpin_idx;
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+ inpin_idx = intc_irq->inpin_idx;
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+
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+ for (i = 0; i < num_outpins; i++) {
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+ if (select & BIT(i)) {
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+ if (s->mask[inpin_idx] & BIT(i) ||
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+ s->regs[status_reg] & BIT(i)) {
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+ /*
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+ * a. mask bit is not 0 means in ISR mode sources interrupt
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+ * routine are executing.
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+ * b. status bit is not 0 means previous source interrupt
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+ * does not be executed, yet.
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+ *
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+ * save source interrupt to pending bit.
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+ */
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+ s->pending[inpin_idx] |= BIT(i);
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+ trace_aspeed_intc_pending_irq(name, inpin_idx,
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+ s->pending[inpin_idx]);
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+ } else {
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+ /*
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+ * notify firmware which source interrupt are coming
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+ * by setting status bit
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+ */
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+ s->regs[status_reg] |= BIT(i);
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+ trace_aspeed_intc_trigger_irq(name, inpin_idx, outpin_idx + i,
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+ s->regs[status_reg]);
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+ aspeed_intc_update(s, inpin_idx, outpin_idx + i, 1);
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+ }
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+ }
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+ }
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}
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/*
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- * The address of GICINT128 to GICINT136 are from 0x1000 to 0x1804.
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- * Utilize "address & 0x0f00" to get the irq and irq output pin index
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- * The value of irq should be 0 to num_ints.
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- * The irq 0 indicates GICINT128, irq 1 indicates GICINT129 and so on.
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+ * GICINT192_201 maps 1:10 to input IRQ 0 and output IRQs 0 to 9.
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+ * GICINT128 to GICINT136 map 1:1 to input IRQs 1 to 9 and output
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+ * IRQs 10 to 18. The value of input IRQ should be between 0 and
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+ * the number of input pins.
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*/
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static void aspeed_intc_set_irq(void *opaque, int irq, int level)
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{
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AspeedINTCState *s = (AspeedINTCState *)opaque;
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AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
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- uint32_t status_addr = GICINT_STATUS_BASE + ((0x100 * irq) >> 2);
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+ const char *name = object_get_typename(OBJECT(s));
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+ const AspeedINTCIRQ *intc_irq;
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uint32_t select = 0;
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uint32_t enable;
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+ int num_outpins;
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+ int inpin_idx;
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int i;
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- if (irq >= aic->num_ints) {
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- qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n",
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- __func__, irq);
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- return;
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- }
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+ assert(irq < aic->num_inpins);
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- trace_aspeed_intc_set_irq(irq, level);
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- enable = s->enable[irq];
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+ intc_irq = &aic->irq_table[irq];
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+ num_outpins = intc_irq->num_outpins;
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+ inpin_idx = intc_irq->inpin_idx;
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+ trace_aspeed_intc_set_irq(name, inpin_idx, level);
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+ enable = s->enable[inpin_idx];
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if (!level) {
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return;
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}
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for (i = 0; i < aic->num_lines; i++) {
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- if (s->orgates[irq].levels[i]) {
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+ if (s->orgates[inpin_idx].levels[i]) {
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if (enable & BIT(i)) {
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select |= BIT(i);
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}
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@@ -90,45 +220,190 @@ static void aspeed_intc_set_irq(void *opaque, int irq, int level)
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return;
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}
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- trace_aspeed_intc_select(select);
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+ trace_aspeed_intc_select(name, select);
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+ if (num_outpins > 1) {
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+ aspeed_intc_set_irq_handler_multi_outpins(s, intc_irq, select);
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+ } else {
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+ aspeed_intc_set_irq_handler(s, intc_irq, select);
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+ }
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+}
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- if (s->mask[irq] || s->regs[status_addr]) {
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- /*
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- * a. mask is not 0 means in ISR mode
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- * sources interrupt routine are executing.
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- * b. status register value is not 0 means previous
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- * source interrupt does not be executed, yet.
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- *
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- * save source interrupt to pending variable.
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- */
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- s->pending[irq] |= select;
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- trace_aspeed_intc_pending_irq(irq, s->pending[irq]);
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+static void aspeed_intc_enable_handler(AspeedINTCState *s, hwaddr offset,
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+ uint64_t data)
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+{
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+ AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
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+ const char *name = object_get_typename(OBJECT(s));
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+ const AspeedINTCIRQ *intc_irq;
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+ uint32_t reg = offset >> 2;
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+ uint32_t old_enable;
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+ uint32_t change;
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+ int inpin_idx;
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+
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+ intc_irq = aspeed_intc_get_irq(aic, reg);
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+ inpin_idx = intc_irq->inpin_idx;
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+
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+ assert(inpin_idx < aic->num_inpins);
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+
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+ /*
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+ * The enable registers are used to enable source interrupts.
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+ * They also handle masking and unmasking of source interrupts
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+ * during the execution of the source ISR.
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+ */
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+
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+ /* disable all source interrupt */
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+ if (!data && !s->enable[inpin_idx]) {
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+ s->regs[reg] = data;
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+ return;
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+ }
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+
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+ old_enable = s->enable[inpin_idx];
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+ s->enable[inpin_idx] |= data;
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+
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+ /* enable new source interrupt */
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+ if (old_enable != s->enable[inpin_idx]) {
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+ trace_aspeed_intc_enable(name, s->enable[inpin_idx]);
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+ s->regs[reg] = data;
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+ return;
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+ }
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+
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+ /* mask and unmask source interrupt */
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+ change = s->regs[reg] ^ data;
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+ if (change & data) {
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+ s->mask[inpin_idx] &= ~change;
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+ trace_aspeed_intc_unmask(name, change, s->mask[inpin_idx]);
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} else {
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- /*
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- * notify firmware which source interrupt are coming
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- * by setting status register
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- */
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- s->regs[status_addr] = select;
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- trace_aspeed_intc_trigger_irq(irq, s->regs[status_addr]);
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- aspeed_intc_update(s, irq, 1);
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+ s->mask[inpin_idx] |= change;
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+ trace_aspeed_intc_mask(name, change, s->mask[inpin_idx]);
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+ }
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+
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+ s->regs[reg] = data;
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+}
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+
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+static void aspeed_intc_status_handler(AspeedINTCState *s, hwaddr offset,
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+ uint64_t data)
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+{
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+ AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
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+ const char *name = object_get_typename(OBJECT(s));
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+ const AspeedINTCIRQ *intc_irq;
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+ uint32_t reg = offset >> 2;
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+ int outpin_idx;
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+ int inpin_idx;
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+
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+ if (!data) {
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+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid data 0\n", __func__);
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+ return;
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+ }
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+
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+ intc_irq = aspeed_intc_get_irq(aic, reg);
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+ outpin_idx = intc_irq->outpin_idx;
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+ inpin_idx = intc_irq->inpin_idx;
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+
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+ assert(inpin_idx < aic->num_inpins);
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+
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+ /* clear status */
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+ s->regs[reg] &= ~data;
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+
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+ /*
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+ * These status registers are used for notify sources ISR are executed.
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+ * If one source ISR is executed, it will clear one bit.
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+ * If it clear all bits, it means to initialize this register status
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+ * rather than sources ISR are executed.
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+ */
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+ if (data == 0xffffffff) {
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+ return;
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+ }
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+
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+ /* All source ISR execution are done */
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+ if (!s->regs[reg]) {
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+ trace_aspeed_intc_all_isr_done(name, inpin_idx);
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+ if (s->pending[inpin_idx]) {
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+ /*
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+ * handle pending source interrupt
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+ * notify firmware which source interrupt are pending
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+ * by setting status register
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+ */
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+ s->regs[reg] = s->pending[inpin_idx];
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+ s->pending[inpin_idx] = 0;
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+ trace_aspeed_intc_trigger_irq(name, inpin_idx, outpin_idx,
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+ s->regs[reg]);
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+ aspeed_intc_update(s, inpin_idx, outpin_idx, 1);
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+ } else {
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+ /* clear irq */
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+ trace_aspeed_intc_clear_irq(name, inpin_idx, outpin_idx, 0);
|
|
|
+ aspeed_intc_update(s, inpin_idx, outpin_idx, 0);
|
|
|
+ }
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static void aspeed_intc_status_handler_multi_outpins(AspeedINTCState *s,
|
|
|
+ hwaddr offset, uint64_t data)
|
|
|
+{
|
|
|
+ const char *name = object_get_typename(OBJECT(s));
|
|
|
+ AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
|
|
|
+ const AspeedINTCIRQ *intc_irq;
|
|
|
+ uint32_t reg = offset >> 2;
|
|
|
+ int num_outpins;
|
|
|
+ int outpin_idx;
|
|
|
+ int inpin_idx;
|
|
|
+ int i;
|
|
|
+
|
|
|
+ if (!data) {
|
|
|
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid data 0\n", __func__);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ intc_irq = aspeed_intc_get_irq(aic, reg);
|
|
|
+ num_outpins = intc_irq->num_outpins;
|
|
|
+ outpin_idx = intc_irq->outpin_idx;
|
|
|
+ inpin_idx = intc_irq->inpin_idx;
|
|
|
+ assert(inpin_idx < aic->num_inpins);
|
|
|
+
|
|
|
+ /* clear status */
|
|
|
+ s->regs[reg] &= ~data;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * The status registers are used for notify sources ISR are executed.
|
|
|
+ * If one source ISR is executed, it will clear one bit.
|
|
|
+ * If it clear all bits, it means to initialize this register status
|
|
|
+ * rather than sources ISR are executed.
|
|
|
+ */
|
|
|
+ if (data == 0xffffffff) {
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ for (i = 0; i < num_outpins; i++) {
|
|
|
+ /* All source ISR executions are done from a specific bit */
|
|
|
+ if (data & BIT(i)) {
|
|
|
+ trace_aspeed_intc_all_isr_done_bit(name, inpin_idx, i);
|
|
|
+ if (s->pending[inpin_idx] & BIT(i)) {
|
|
|
+ /*
|
|
|
+ * Handle pending source interrupt.
|
|
|
+ * Notify firmware which source interrupt is pending
|
|
|
+ * by setting the status bit.
|
|
|
+ */
|
|
|
+ s->regs[reg] |= BIT(i);
|
|
|
+ s->pending[inpin_idx] &= ~BIT(i);
|
|
|
+ trace_aspeed_intc_trigger_irq(name, inpin_idx, outpin_idx + i,
|
|
|
+ s->regs[reg]);
|
|
|
+ aspeed_intc_update(s, inpin_idx, outpin_idx + i, 1);
|
|
|
+ } else {
|
|
|
+ /* clear irq for the specific bit */
|
|
|
+ trace_aspeed_intc_clear_irq(name, inpin_idx, outpin_idx + i, 0);
|
|
|
+ aspeed_intc_update(s, inpin_idx, outpin_idx + i, 0);
|
|
|
+ }
|
|
|
+ }
|
|
|
}
|
|
|
}
|
|
|
|
|
|
static uint64_t aspeed_intc_read(void *opaque, hwaddr offset, unsigned int size)
|
|
|
{
|
|
|
AspeedINTCState *s = ASPEED_INTC(opaque);
|
|
|
- uint32_t addr = offset >> 2;
|
|
|
+ const char *name = object_get_typename(OBJECT(s));
|
|
|
+ uint32_t reg = offset >> 2;
|
|
|
uint32_t value = 0;
|
|
|
|
|
|
- if (addr >= ASPEED_INTC_NR_REGS) {
|
|
|
- qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
- "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
|
|
|
- __func__, offset);
|
|
|
- return 0;
|
|
|
- }
|
|
|
-
|
|
|
- value = s->regs[addr];
|
|
|
- trace_aspeed_intc_read(offset, size, value);
|
|
|
+ value = s->regs[reg];
|
|
|
+ trace_aspeed_intc_read(name, offset, size, value);
|
|
|
|
|
|
return value;
|
|
|
}
|
|
|
@@ -137,22 +412,12 @@ static void aspeed_intc_write(void *opaque, hwaddr offset, uint64_t data,
|
|
|
unsigned size)
|
|
|
{
|
|
|
AspeedINTCState *s = ASPEED_INTC(opaque);
|
|
|
- AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
|
|
|
- uint32_t addr = offset >> 2;
|
|
|
- uint32_t old_enable;
|
|
|
- uint32_t change;
|
|
|
- uint32_t irq;
|
|
|
-
|
|
|
- if (addr >= ASPEED_INTC_NR_REGS) {
|
|
|
- qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
- "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
|
|
|
- __func__, offset);
|
|
|
- return;
|
|
|
- }
|
|
|
+ const char *name = object_get_typename(OBJECT(s));
|
|
|
+ uint32_t reg = offset >> 2;
|
|
|
|
|
|
- trace_aspeed_intc_write(offset, size, data);
|
|
|
+ trace_aspeed_intc_write(name, offset, size, data);
|
|
|
|
|
|
- switch (addr) {
|
|
|
+ switch (reg) {
|
|
|
case R_GICINT128_EN:
|
|
|
case R_GICINT129_EN:
|
|
|
case R_GICINT130_EN:
|
|
|
@@ -162,45 +427,8 @@ static void aspeed_intc_write(void *opaque, hwaddr offset, uint64_t data,
|
|
|
case R_GICINT134_EN:
|
|
|
case R_GICINT135_EN:
|
|
|
case R_GICINT136_EN:
|
|
|
- irq = (offset & 0x0f00) >> 8;
|
|
|
-
|
|
|
- if (irq >= aic->num_ints) {
|
|
|
- qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n",
|
|
|
- __func__, irq);
|
|
|
- return;
|
|
|
- }
|
|
|
-
|
|
|
- /*
|
|
|
- * These registers are used for enable sources interrupt and
|
|
|
- * mask and unmask source interrupt while executing source ISR.
|
|
|
- */
|
|
|
-
|
|
|
- /* disable all source interrupt */
|
|
|
- if (!data && !s->enable[irq]) {
|
|
|
- s->regs[addr] = data;
|
|
|
- return;
|
|
|
- }
|
|
|
-
|
|
|
- old_enable = s->enable[irq];
|
|
|
- s->enable[irq] |= data;
|
|
|
-
|
|
|
- /* enable new source interrupt */
|
|
|
- if (old_enable != s->enable[irq]) {
|
|
|
- trace_aspeed_intc_enable(s->enable[irq]);
|
|
|
- s->regs[addr] = data;
|
|
|
- return;
|
|
|
- }
|
|
|
-
|
|
|
- /* mask and unmask source interrupt */
|
|
|
- change = s->regs[addr] ^ data;
|
|
|
- if (change & data) {
|
|
|
- s->mask[irq] &= ~change;
|
|
|
- trace_aspeed_intc_unmask(change, s->mask[irq]);
|
|
|
- } else {
|
|
|
- s->mask[irq] |= change;
|
|
|
- trace_aspeed_intc_mask(change, s->mask[irq]);
|
|
|
- }
|
|
|
- s->regs[addr] = data;
|
|
|
+ case R_GICINT192_201_EN:
|
|
|
+ aspeed_intc_enable_handler(s, offset, data);
|
|
|
break;
|
|
|
case R_GICINT128_STATUS:
|
|
|
case R_GICINT129_STATUS:
|
|
|
@@ -211,55 +439,68 @@ static void aspeed_intc_write(void *opaque, hwaddr offset, uint64_t data,
|
|
|
case R_GICINT134_STATUS:
|
|
|
case R_GICINT135_STATUS:
|
|
|
case R_GICINT136_STATUS:
|
|
|
- irq = (offset & 0x0f00) >> 8;
|
|
|
+ aspeed_intc_status_handler(s, offset, data);
|
|
|
+ break;
|
|
|
+ case R_GICINT192_201_STATUS:
|
|
|
+ aspeed_intc_status_handler_multi_outpins(s, offset, data);
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ s->regs[reg] = data;
|
|
|
+ break;
|
|
|
+ }
|
|
|
|
|
|
- if (irq >= aic->num_ints) {
|
|
|
- qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n",
|
|
|
- __func__, irq);
|
|
|
- return;
|
|
|
- }
|
|
|
+ return;
|
|
|
+}
|
|
|
+
|
|
|
+static uint64_t aspeed_intcio_read(void *opaque, hwaddr offset,
|
|
|
+ unsigned int size)
|
|
|
+{
|
|
|
+ AspeedINTCState *s = ASPEED_INTC(opaque);
|
|
|
+ const char *name = object_get_typename(OBJECT(s));
|
|
|
+ uint32_t reg = offset >> 2;
|
|
|
+ uint32_t value = 0;
|
|
|
|
|
|
- /* clear status */
|
|
|
- s->regs[addr] &= ~data;
|
|
|
+ value = s->regs[reg];
|
|
|
+ trace_aspeed_intc_read(name, offset, size, value);
|
|
|
|
|
|
- /*
|
|
|
- * These status registers are used for notify sources ISR are executed.
|
|
|
- * If one source ISR is executed, it will clear one bit.
|
|
|
- * If it clear all bits, it means to initialize this register status
|
|
|
- * rather than sources ISR are executed.
|
|
|
- */
|
|
|
- if (data == 0xffffffff) {
|
|
|
- return;
|
|
|
- }
|
|
|
+ return value;
|
|
|
+}
|
|
|
|
|
|
- /* All source ISR execution are done */
|
|
|
- if (!s->regs[addr]) {
|
|
|
- trace_aspeed_intc_all_isr_done(irq);
|
|
|
- if (s->pending[irq]) {
|
|
|
- /*
|
|
|
- * handle pending source interrupt
|
|
|
- * notify firmware which source interrupt are pending
|
|
|
- * by setting status register
|
|
|
- */
|
|
|
- s->regs[addr] = s->pending[irq];
|
|
|
- s->pending[irq] = 0;
|
|
|
- trace_aspeed_intc_trigger_irq(irq, s->regs[addr]);
|
|
|
- aspeed_intc_update(s, irq, 1);
|
|
|
- } else {
|
|
|
- /* clear irq */
|
|
|
- trace_aspeed_intc_clear_irq(irq, 0);
|
|
|
- aspeed_intc_update(s, irq, 0);
|
|
|
- }
|
|
|
- }
|
|
|
+static void aspeed_intcio_write(void *opaque, hwaddr offset, uint64_t data,
|
|
|
+ unsigned size)
|
|
|
+{
|
|
|
+ AspeedINTCState *s = ASPEED_INTC(opaque);
|
|
|
+ const char *name = object_get_typename(OBJECT(s));
|
|
|
+ uint32_t reg = offset >> 2;
|
|
|
+
|
|
|
+ trace_aspeed_intc_write(name, offset, size, data);
|
|
|
+
|
|
|
+ switch (reg) {
|
|
|
+ case R_GICINT192_EN:
|
|
|
+ case R_GICINT193_EN:
|
|
|
+ case R_GICINT194_EN:
|
|
|
+ case R_GICINT195_EN:
|
|
|
+ case R_GICINT196_EN:
|
|
|
+ case R_GICINT197_EN:
|
|
|
+ aspeed_intc_enable_handler(s, offset, data);
|
|
|
+ break;
|
|
|
+ case R_GICINT192_STATUS:
|
|
|
+ case R_GICINT193_STATUS:
|
|
|
+ case R_GICINT194_STATUS:
|
|
|
+ case R_GICINT195_STATUS:
|
|
|
+ case R_GICINT196_STATUS:
|
|
|
+ case R_GICINT197_STATUS:
|
|
|
+ aspeed_intc_status_handler(s, offset, data);
|
|
|
break;
|
|
|
default:
|
|
|
- s->regs[addr] = data;
|
|
|
+ s->regs[reg] = data;
|
|
|
break;
|
|
|
}
|
|
|
|
|
|
return;
|
|
|
}
|
|
|
|
|
|
+
|
|
|
static const MemoryRegionOps aspeed_intc_ops = {
|
|
|
.read = aspeed_intc_read,
|
|
|
.write = aspeed_intc_write,
|
|
|
@@ -270,14 +511,24 @@ static const MemoryRegionOps aspeed_intc_ops = {
|
|
|
}
|
|
|
};
|
|
|
|
|
|
+static const MemoryRegionOps aspeed_intcio_ops = {
|
|
|
+ .read = aspeed_intcio_read,
|
|
|
+ .write = aspeed_intcio_write,
|
|
|
+ .endianness = DEVICE_LITTLE_ENDIAN,
|
|
|
+ .valid = {
|
|
|
+ .min_access_size = 4,
|
|
|
+ .max_access_size = 4,
|
|
|
+ }
|
|
|
+};
|
|
|
+
|
|
|
static void aspeed_intc_instance_init(Object *obj)
|
|
|
{
|
|
|
AspeedINTCState *s = ASPEED_INTC(obj);
|
|
|
AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
|
|
|
int i;
|
|
|
|
|
|
- assert(aic->num_ints <= ASPEED_INTC_NR_INTS);
|
|
|
- for (i = 0; i < aic->num_ints; i++) {
|
|
|
+ assert(aic->num_inpins <= ASPEED_INTC_MAX_INPINS);
|
|
|
+ for (i = 0; i < aic->num_inpins; i++) {
|
|
|
object_initialize_child(obj, "intc-orgates[*]", &s->orgates[i],
|
|
|
TYPE_OR_IRQ);
|
|
|
object_property_set_int(OBJECT(&s->orgates[i]), "num-lines",
|
|
|
@@ -288,8 +539,9 @@ static void aspeed_intc_instance_init(Object *obj)
|
|
|
static void aspeed_intc_reset(DeviceState *dev)
|
|
|
{
|
|
|
AspeedINTCState *s = ASPEED_INTC(dev);
|
|
|
+ AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
|
|
|
|
|
|
- memset(s->regs, 0, sizeof(s->regs));
|
|
|
+ memset(s->regs, 0, aic->nr_regs << 2);
|
|
|
memset(s->enable, 0, sizeof(s->enable));
|
|
|
memset(s->mask, 0, sizeof(s->mask));
|
|
|
memset(s->pending, 0, sizeof(s->pending));
|
|
|
@@ -302,28 +554,51 @@ static void aspeed_intc_realize(DeviceState *dev, Error **errp)
|
|
|
AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
|
|
|
int i;
|
|
|
|
|
|
- memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_intc_ops, s,
|
|
|
- TYPE_ASPEED_INTC ".regs", ASPEED_INTC_NR_REGS << 2);
|
|
|
+ memory_region_init(&s->iomem_container, OBJECT(s),
|
|
|
+ TYPE_ASPEED_INTC ".container", aic->mem_size);
|
|
|
+
|
|
|
+ sysbus_init_mmio(sbd, &s->iomem_container);
|
|
|
|
|
|
- sysbus_init_mmio(sbd, &s->iomem);
|
|
|
- qdev_init_gpio_in(dev, aspeed_intc_set_irq, aic->num_ints);
|
|
|
+ s->regs = g_new(uint32_t, aic->nr_regs);
|
|
|
+ memory_region_init_io(&s->iomem, OBJECT(s), aic->reg_ops, s,
|
|
|
+ TYPE_ASPEED_INTC ".regs", aic->nr_regs << 2);
|
|
|
|
|
|
- for (i = 0; i < aic->num_ints; i++) {
|
|
|
+ memory_region_add_subregion(&s->iomem_container, aic->reg_offset,
|
|
|
+ &s->iomem);
|
|
|
+
|
|
|
+ qdev_init_gpio_in(dev, aspeed_intc_set_irq, aic->num_inpins);
|
|
|
+
|
|
|
+ for (i = 0; i < aic->num_inpins; i++) {
|
|
|
if (!qdev_realize(DEVICE(&s->orgates[i]), NULL, errp)) {
|
|
|
return;
|
|
|
}
|
|
|
+ }
|
|
|
+
|
|
|
+ for (i = 0; i < aic->num_outpins; i++) {
|
|
|
sysbus_init_irq(sbd, &s->output_pins[i]);
|
|
|
}
|
|
|
}
|
|
|
|
|
|
+static void aspeed_intc_unrealize(DeviceState *dev)
|
|
|
+{
|
|
|
+ AspeedINTCState *s = ASPEED_INTC(dev);
|
|
|
+
|
|
|
+ g_free(s->regs);
|
|
|
+ s->regs = NULL;
|
|
|
+}
|
|
|
+
|
|
|
static void aspeed_intc_class_init(ObjectClass *klass, void *data)
|
|
|
{
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
+ AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
|
|
|
|
|
|
dc->desc = "ASPEED INTC Controller";
|
|
|
dc->realize = aspeed_intc_realize;
|
|
|
+ dc->unrealize = aspeed_intc_unrealize;
|
|
|
device_class_set_legacy_reset(dc, aspeed_intc_reset);
|
|
|
dc->vmsd = NULL;
|
|
|
+
|
|
|
+ aic->reg_ops = &aspeed_intc_ops;
|
|
|
}
|
|
|
|
|
|
static const TypeInfo aspeed_intc_info = {
|
|
|
@@ -336,6 +611,19 @@ static const TypeInfo aspeed_intc_info = {
|
|
|
.abstract = true,
|
|
|
};
|
|
|
|
|
|
+static AspeedINTCIRQ aspeed_2700_intc_irqs[ASPEED_INTC_MAX_INPINS] = {
|
|
|
+ {0, 0, 10, R_GICINT192_201_EN, R_GICINT192_201_STATUS},
|
|
|
+ {1, 10, 1, R_GICINT128_EN, R_GICINT128_STATUS},
|
|
|
+ {2, 11, 1, R_GICINT129_EN, R_GICINT129_STATUS},
|
|
|
+ {3, 12, 1, R_GICINT130_EN, R_GICINT130_STATUS},
|
|
|
+ {4, 13, 1, R_GICINT131_EN, R_GICINT131_STATUS},
|
|
|
+ {5, 14, 1, R_GICINT132_EN, R_GICINT132_STATUS},
|
|
|
+ {6, 15, 1, R_GICINT133_EN, R_GICINT133_STATUS},
|
|
|
+ {7, 16, 1, R_GICINT134_EN, R_GICINT134_STATUS},
|
|
|
+ {8, 17, 1, R_GICINT135_EN, R_GICINT135_STATUS},
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+ {9, 18, 1, R_GICINT136_EN, R_GICINT136_STATUS},
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+};
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+
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static void aspeed_2700_intc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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@@ -343,7 +631,13 @@ static void aspeed_2700_intc_class_init(ObjectClass *klass, void *data)
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dc->desc = "ASPEED 2700 INTC Controller";
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aic->num_lines = 32;
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- aic->num_ints = 9;
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+ aic->num_inpins = 10;
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+ aic->num_outpins = 19;
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+ aic->mem_size = 0x4000;
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+ aic->nr_regs = 0xB08 >> 2;
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+ aic->reg_offset = 0x1000;
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+ aic->irq_table = aspeed_2700_intc_irqs;
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+ aic->irq_table_count = ARRAY_SIZE(aspeed_2700_intc_irqs);
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}
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static const TypeInfo aspeed_2700_intc_info = {
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@@ -352,10 +646,43 @@ static const TypeInfo aspeed_2700_intc_info = {
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.class_init = aspeed_2700_intc_class_init,
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};
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+static AspeedINTCIRQ aspeed_2700_intcio_irqs[ASPEED_INTC_MAX_INPINS] = {
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+ {0, 0, 1, R_GICINT192_EN, R_GICINT192_STATUS},
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+ {1, 1, 1, R_GICINT193_EN, R_GICINT193_STATUS},
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+ {2, 2, 1, R_GICINT194_EN, R_GICINT194_STATUS},
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+ {3, 3, 1, R_GICINT195_EN, R_GICINT195_STATUS},
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+ {4, 4, 1, R_GICINT196_EN, R_GICINT196_STATUS},
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+ {5, 5, 1, R_GICINT197_EN, R_GICINT197_STATUS},
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+};
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+
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+static void aspeed_2700_intcio_class_init(ObjectClass *klass, void *data)
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+{
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+ DeviceClass *dc = DEVICE_CLASS(klass);
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+ AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
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+
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+ dc->desc = "ASPEED 2700 INTC IO Controller";
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+ aic->num_lines = 32;
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+ aic->num_inpins = 6;
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+ aic->num_outpins = 6;
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+ aic->mem_size = 0x400;
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+ aic->nr_regs = 0x58 >> 2;
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+ aic->reg_offset = 0x100;
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+ aic->reg_ops = &aspeed_intcio_ops;
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+ aic->irq_table = aspeed_2700_intcio_irqs;
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+ aic->irq_table_count = ARRAY_SIZE(aspeed_2700_intcio_irqs);
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+}
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+
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+static const TypeInfo aspeed_2700_intcio_info = {
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+ .name = TYPE_ASPEED_2700_INTCIO,
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+ .parent = TYPE_ASPEED_INTC,
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+ .class_init = aspeed_2700_intcio_class_init,
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+};
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+
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static void aspeed_intc_register_types(void)
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{
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type_register_static(&aspeed_intc_info);
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type_register_static(&aspeed_2700_intc_info);
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+ type_register_static(&aspeed_2700_intcio_info);
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}
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type_init(aspeed_intc_register_types);
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Stefan Hajnoczi