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@@ -40,7 +40,7 @@
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#define AHCI_PORT_PRIV_DMA_SZ (AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + \
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#define AHCI_PORT_PRIV_DMA_SZ (AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + \
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AHCI_RX_FIS_SZ)
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AHCI_RX_FIS_SZ)
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-#define AHCI_IRQ_ON_SG (1 << 31)
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+#define AHCI_IRQ_ON_SG (1U << 31)
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#define AHCI_CMD_ATAPI (1 << 5)
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#define AHCI_CMD_ATAPI (1 << 5)
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#define AHCI_CMD_WRITE (1 << 6)
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#define AHCI_CMD_WRITE (1 << 6)
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#define AHCI_CMD_PREFETCH (1 << 7)
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#define AHCI_CMD_PREFETCH (1 << 7)
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@@ -61,7 +61,7 @@
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/* HOST_CTL bits */
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/* HOST_CTL bits */
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#define HOST_CTL_RESET (1 << 0) /* reset controller; self-clear */
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#define HOST_CTL_RESET (1 << 0) /* reset controller; self-clear */
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#define HOST_CTL_IRQ_EN (1 << 1) /* global IRQ enable */
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#define HOST_CTL_IRQ_EN (1 << 1) /* global IRQ enable */
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-#define HOST_CTL_AHCI_EN (1 << 31) /* AHCI enabled */
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+#define HOST_CTL_AHCI_EN (1U << 31) /* AHCI enabled */
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/* HOST_CAP bits */
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/* HOST_CAP bits */
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#define HOST_CAP_SSC (1 << 14) /* Slumber capable */
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#define HOST_CAP_SSC (1 << 14) /* Slumber capable */
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@@ -69,7 +69,7 @@
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#define HOST_CAP_CLO (1 << 24) /* Command List Override support */
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#define HOST_CAP_CLO (1 << 24) /* Command List Override support */
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#define HOST_CAP_SSS (1 << 27) /* Staggered Spin-up */
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#define HOST_CAP_SSS (1 << 27) /* Staggered Spin-up */
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#define HOST_CAP_NCQ (1 << 30) /* Native Command Queueing */
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#define HOST_CAP_NCQ (1 << 30) /* Native Command Queueing */
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-#define HOST_CAP_64 (1 << 31) /* PCI DAC (64-bit DMA) support */
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+#define HOST_CAP_64 (1U << 31) /* PCI DAC (64-bit DMA) support */
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/* registers for each SATA port */
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/* registers for each SATA port */
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#define PORT_LST_ADDR 0x00 /* command list DMA addr */
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#define PORT_LST_ADDR 0x00 /* command list DMA addr */
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@@ -89,7 +89,7 @@
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#define PORT_RESERVED 0x3c /* reserved */
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#define PORT_RESERVED 0x3c /* reserved */
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/* PORT_IRQ_{STAT,MASK} bits */
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/* PORT_IRQ_{STAT,MASK} bits */
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-#define PORT_IRQ_COLD_PRES (1 << 31) /* cold presence detect */
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+#define PORT_IRQ_COLD_PRES (1U << 31) /* cold presence detect */
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#define PORT_IRQ_TF_ERR (1 << 30) /* task file error */
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#define PORT_IRQ_TF_ERR (1 << 30) /* task file error */
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#define PORT_IRQ_HBUS_ERR (1 << 29) /* host bus fatal error */
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#define PORT_IRQ_HBUS_ERR (1 << 29) /* host bus fatal error */
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#define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */
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#define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */
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@@ -151,7 +151,7 @@
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#define PORT_IRQ_STAT_HBDS (1 << 28) /* Host Bus Data Error Status */
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#define PORT_IRQ_STAT_HBDS (1 << 28) /* Host Bus Data Error Status */
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#define PORT_IRQ_STAT_HBFS (1 << 29) /* Host Bus Fatal Error Status */
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#define PORT_IRQ_STAT_HBFS (1 << 29) /* Host Bus Fatal Error Status */
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#define PORT_IRQ_STAT_TFES (1 << 30) /* Task File Error Status */
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#define PORT_IRQ_STAT_TFES (1 << 30) /* Task File Error Status */
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-#define PORT_IRQ_STAT_CPDS (1 << 31) /* Code Port Detect Status */
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+#define PORT_IRQ_STAT_CPDS (1U << 31) /* Code Port Detect Status */
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/* ap->flags bits */
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/* ap->flags bits */
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#define AHCI_FLAG_NO_NCQ (1 << 24)
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#define AHCI_FLAG_NO_NCQ (1 << 24)
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