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@@ -27,6 +27,7 @@
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#include "hw/sysbus.h"
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#include "hw/char/serial.h"
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+#include "hw/intc/nios2_vic.h"
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#include "hw/qdev-properties.h"
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#include "sysemu/sysemu.h"
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#include "hw/boards.h"
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@@ -43,6 +44,8 @@ struct Nios2MachineState {
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MemoryRegion phys_tcm_alias;
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MemoryRegion phys_ram;
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MemoryRegion phys_ram_alias;
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+
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+ bool vic;
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};
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#define TYPE_NIOS2_MACHINE MACHINE_TYPE_NAME("10m50-ghrd")
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@@ -81,10 +84,39 @@ static void nios2_10m50_ghrd_init(MachineState *machine)
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memory_region_add_subregion(address_space_mem, 0xc0000000 + ram_base,
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&nms->phys_ram_alias);
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- /* Create CPU -- FIXME */
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- cpu = NIOS2_CPU(cpu_create(TYPE_NIOS2_CPU));
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- for (i = 0; i < 32; i++) {
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- irq[i] = qdev_get_gpio_in_named(DEVICE(cpu), "IRQ", i);
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+ /* Create CPU. We need to set eic_present between init and realize. */
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+ cpu = NIOS2_CPU(object_new(TYPE_NIOS2_CPU));
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+
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+ /* Enable the External Interrupt Controller within the CPU. */
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+ cpu->eic_present = nms->vic;
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+
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+ /* Configure new exception vectors. */
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+ cpu->reset_addr = 0xd4000000;
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+ cpu->exception_addr = 0xc8000120;
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+ cpu->fast_tlb_miss_addr = 0xc0000100;
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+
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+ qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal);
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+
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+ if (nms->vic) {
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+ DeviceState *dev = qdev_new(TYPE_NIOS2_VIC);
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+ MemoryRegion *dev_mr;
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+ qemu_irq cpu_irq;
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+
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+ object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_fatal);
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+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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+
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+ cpu_irq = qdev_get_gpio_in_named(DEVICE(cpu), "EIC", 0);
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+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq);
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+ for (int i = 0; i < 32; i++) {
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+ irq[i] = qdev_get_gpio_in(dev, i);
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+ }
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+
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+ dev_mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
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+ memory_region_add_subregion(address_space_mem, 0x18002000, dev_mr);
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+ } else {
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+ for (i = 0; i < 32; i++) {
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+ irq[i] = qdev_get_gpio_in_named(DEVICE(cpu), "IRQ", i);
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+ }
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}
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/* Register: Altera 16550 UART */
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@@ -105,15 +137,22 @@ static void nios2_10m50_ghrd_init(MachineState *machine)
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xe0000880);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[5]);
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- /* Configure new exception vectors and reset CPU for it to take effect. */
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- cpu->reset_addr = 0xd4000000;
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- cpu->exception_addr = 0xc8000120;
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- cpu->fast_tlb_miss_addr = 0xc0000100;
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-
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nios2_load_kernel(cpu, ram_base, ram_size, machine->initrd_filename,
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BINARY_DEVICE_TREE_FILE, NULL);
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}
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+static bool get_vic(Object *obj, Error **errp)
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+{
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+ Nios2MachineState *nms = NIOS2_MACHINE(obj);
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+ return nms->vic;
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+}
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+
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+static void set_vic(Object *obj, bool value, Error **errp)
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+{
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+ Nios2MachineState *nms = NIOS2_MACHINE(obj);
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+ nms->vic = value;
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+}
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+
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static void nios2_10m50_ghrd_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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@@ -121,6 +160,10 @@ static void nios2_10m50_ghrd_class_init(ObjectClass *oc, void *data)
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mc->desc = "Altera 10M50 GHRD Nios II design";
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mc->init = nios2_10m50_ghrd_init;
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mc->is_default = true;
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+
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+ object_class_property_add_bool(oc, "vic", get_vic, set_vic);
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+ object_class_property_set_description(oc, "vic",
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+ "Set on/off to enable/disable the Vectored Interrupt Controller");
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}
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static const TypeInfo nios2_10m50_ghrd_type_info = {
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