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@@ -0,0 +1,225 @@
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+/*
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+ * QEMU RX CPU
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+ *
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+ * Copyright (c) 2019 Yoshinori Sato
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms and conditions of the GNU General Public License,
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+ * version 2 or later, as published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope it will be useful, but WITHOUT
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+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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+ * more details.
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+ *
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+ * You should have received a copy of the GNU General Public License along with
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+ * this program. If not, see <http://www.gnu.org/licenses/>.
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+ */
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+
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+#include "qemu/osdep.h"
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+#include "qemu/qemu-print.h"
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+#include "qapi/error.h"
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+#include "cpu.h"
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+#include "qemu-common.h"
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+#include "migration/vmstate.h"
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+#include "exec/exec-all.h"
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+#include "hw/loader.h"
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+#include "fpu/softfloat.h"
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+
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+static void rx_cpu_set_pc(CPUState *cs, vaddr value)
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+{
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+ RXCPU *cpu = RXCPU(cs);
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+
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+ cpu->env.pc = value;
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+}
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+
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+static void rx_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
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+{
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+ RXCPU *cpu = RXCPU(cs);
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+
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+ cpu->env.pc = tb->pc;
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+}
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+
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+static bool rx_cpu_has_work(CPUState *cs)
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+{
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+ return cs->interrupt_request &
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+ (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR);
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+}
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+
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+static void rx_cpu_reset(DeviceState *dev)
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+{
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+ RXCPU *cpu = RXCPU(dev);
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+ RXCPUClass *rcc = RXCPU_GET_CLASS(cpu);
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+ CPURXState *env = &cpu->env;
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+ uint32_t *resetvec;
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+
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+ rcc->parent_reset(dev);
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+
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+ memset(env, 0, offsetof(CPURXState, end_reset_fields));
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+
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+ resetvec = rom_ptr(0xfffffffc, 4);
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+ if (resetvec) {
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+ /* In the case of kernel, it is ignored because it is not set. */
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+ env->pc = ldl_p(resetvec);
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+ }
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+ rx_cpu_unpack_psw(env, 0, 1);
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+ env->regs[0] = env->isp = env->usp = 0;
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+ env->fpsw = 0;
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+ set_flush_to_zero(1, &env->fp_status);
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+ set_flush_inputs_to_zero(1, &env->fp_status);
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+}
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+
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+static void rx_cpu_list_entry(gpointer data, gpointer user_data)
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+{
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+ ObjectClass *oc = data;
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+
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+ qemu_printf(" %s\n", object_class_get_name(oc));
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+}
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+
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+void rx_cpu_list(void)
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+{
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+ GSList *list;
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+ list = object_class_get_list_sorted(TYPE_RX_CPU, false);
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+ qemu_printf("Available CPUs:\n");
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+ g_slist_foreach(list, rx_cpu_list_entry, NULL);
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+ g_slist_free(list);
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+}
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+
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+static ObjectClass *rx_cpu_class_by_name(const char *cpu_model)
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+{
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+ ObjectClass *oc;
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+ char *typename;
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+
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+ oc = object_class_by_name(cpu_model);
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+ if (oc != NULL && object_class_dynamic_cast(oc, TYPE_RX_CPU) != NULL &&
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+ !object_class_is_abstract(oc)) {
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+ return oc;
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+ }
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+ typename = g_strdup_printf(RX_CPU_TYPE_NAME("%s"), cpu_model);
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+ oc = object_class_by_name(typename);
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+ g_free(typename);
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+ if (oc != NULL && object_class_is_abstract(oc)) {
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+ oc = NULL;
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+ }
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+
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+ return oc;
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+}
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+
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+static void rx_cpu_realize(DeviceState *dev, Error **errp)
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+{
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+ CPUState *cs = CPU(dev);
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+ RXCPUClass *rcc = RXCPU_GET_CLASS(dev);
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+ Error *local_err = NULL;
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+
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+ cpu_exec_realizefn(cs, &local_err);
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+ if (local_err != NULL) {
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+ error_propagate(errp, local_err);
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+ return;
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+ }
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+
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+ qemu_init_vcpu(cs);
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+ cpu_reset(cs);
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+
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+ rcc->parent_realize(dev, errp);
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+}
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+
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+static void rx_cpu_set_irq(void *opaque, int no, int request)
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+{
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+ RXCPU *cpu = opaque;
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+ CPUState *cs = CPU(cpu);
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+ int irq = request & 0xff;
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+
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+ static const int mask[] = {
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+ [RX_CPU_IRQ] = CPU_INTERRUPT_HARD,
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+ [RX_CPU_FIR] = CPU_INTERRUPT_FIR,
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+ };
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+ if (irq) {
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+ cpu->env.req_irq = irq;
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+ cpu->env.req_ipl = (request >> 8) & 0x0f;
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+ cpu_interrupt(cs, mask[no]);
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+ } else {
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+ cpu_reset_interrupt(cs, mask[no]);
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+ }
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+}
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+
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+static void rx_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
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+{
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+ info->mach = bfd_mach_rx;
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+ info->print_insn = print_insn_rx;
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+}
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+
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+static bool rx_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
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+ MMUAccessType access_type, int mmu_idx,
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+ bool probe, uintptr_t retaddr)
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+{
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+ uint32_t address, physical, prot;
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+
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+ /* Linear mapping */
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+ address = physical = addr & TARGET_PAGE_MASK;
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+ prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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+ tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
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+ return true;
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+}
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+
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+static void rx_cpu_init(Object *obj)
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+{
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+ CPUState *cs = CPU(obj);
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+ RXCPU *cpu = RXCPU(obj);
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+ CPURXState *env = &cpu->env;
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+
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+ cpu_set_cpustate_pointers(cpu);
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+ cs->env_ptr = env;
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+ qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2);
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+}
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+
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+static void rx_cpu_class_init(ObjectClass *klass, void *data)
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+{
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+ DeviceClass *dc = DEVICE_CLASS(klass);
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+ CPUClass *cc = CPU_CLASS(klass);
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+ RXCPUClass *rcc = RXCPU_CLASS(klass);
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+
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+ device_class_set_parent_realize(dc, rx_cpu_realize,
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+ &rcc->parent_realize);
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+ device_class_set_parent_reset(dc, rx_cpu_reset,
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+ &rcc->parent_reset);
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+
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+ cc->class_by_name = rx_cpu_class_by_name;
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+ cc->has_work = rx_cpu_has_work;
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+ cc->do_interrupt = rx_cpu_do_interrupt;
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+ cc->cpu_exec_interrupt = rx_cpu_exec_interrupt;
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+ cc->dump_state = rx_cpu_dump_state;
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+ cc->set_pc = rx_cpu_set_pc;
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+ cc->synchronize_from_tb = rx_cpu_synchronize_from_tb;
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+ cc->gdb_read_register = rx_cpu_gdb_read_register;
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+ cc->gdb_write_register = rx_cpu_gdb_write_register;
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+ cc->get_phys_page_debug = rx_cpu_get_phys_page_debug;
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+ cc->disas_set_info = rx_cpu_disas_set_info;
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+ cc->tcg_initialize = rx_translate_init;
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+ cc->tlb_fill = rx_cpu_tlb_fill;
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+
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+ cc->gdb_num_core_regs = 26;
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+ cc->gdb_core_xml_file = "rx-core.xml";
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+}
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+
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+static const TypeInfo rx_cpu_info = {
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+ .name = TYPE_RX_CPU,
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+ .parent = TYPE_CPU,
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+ .instance_size = sizeof(RXCPU),
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+ .instance_init = rx_cpu_init,
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+ .abstract = true,
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+ .class_size = sizeof(RXCPUClass),
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+ .class_init = rx_cpu_class_init,
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+};
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+
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+static const TypeInfo rx62n_rx_cpu_info = {
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+ .name = TYPE_RX62N_CPU,
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+ .parent = TYPE_RX_CPU,
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+};
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+
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+static void rx_cpu_register_types(void)
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+{
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+ type_register_static(&rx_cpu_info);
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+ type_register_static(&rx62n_rx_cpu_info);
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+}
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+
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+type_init(rx_cpu_register_types)
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Yoshinori Sato