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@@ -650,31 +650,17 @@ static void apic_timer(void *opaque)
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apic_timer_update(s, s->next_time);
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}
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-static uint32_t apic_mem_readb(void *opaque, hwaddr addr)
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-{
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- return 0;
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-}
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-
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-static uint32_t apic_mem_readw(void *opaque, hwaddr addr)
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-{
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- return 0;
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-}
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-
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-static void apic_mem_writeb(void *opaque, hwaddr addr, uint32_t val)
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-{
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-}
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-
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-static void apic_mem_writew(void *opaque, hwaddr addr, uint32_t val)
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-{
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-}
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-
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-static uint32_t apic_mem_readl(void *opaque, hwaddr addr)
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+static uint64_t apic_mem_read(void *opaque, hwaddr addr, unsigned size)
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{
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DeviceState *dev;
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APICCommonState *s;
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uint32_t val;
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int index;
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+ if (size < 4) {
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+ return 0;
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+ }
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+
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dev = cpu_get_current_apic();
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if (!dev) {
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return 0;
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@@ -765,11 +751,17 @@ static void apic_send_msi(MSIMessage *msi)
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apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode);
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}
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-static void apic_mem_writel(void *opaque, hwaddr addr, uint32_t val)
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+static void apic_mem_write(void *opaque, hwaddr addr, uint64_t val,
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+ unsigned size)
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{
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DeviceState *dev;
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APICCommonState *s;
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int index = (addr >> 4) & 0xff;
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+
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+ if (size < 4) {
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+ return;
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+ }
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+
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if (addr > 0xfff || !index) {
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/* MSI and MMIO APIC are at the same memory location,
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* but actually not on the global bus: MSI is on PCI bus
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@@ -880,10 +872,12 @@ static void apic_post_load(APICCommonState *s)
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}
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static const MemoryRegionOps apic_io_ops = {
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- .old_mmio = {
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- .read = { apic_mem_readb, apic_mem_readw, apic_mem_readl, },
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- .write = { apic_mem_writeb, apic_mem_writew, apic_mem_writel, },
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- },
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+ .read = apic_mem_read,
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+ .write = apic_mem_write,
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+ .impl.min_access_size = 1,
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+ .impl.max_access_size = 4,
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+ .valid.min_access_size = 1,
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+ .valid.max_access_size = 4,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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