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@@ -543,19 +543,31 @@ static void rcc_update_cfgr_register(Stm32l4x5RccState *s)
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uint32_t val;
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/* MCOPRE */
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val = FIELD_EX32(s->cfgr, CFGR, MCOPRE);
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- assert(val <= 0b100);
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- clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_MCO],
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- 1, 1 << val);
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+ if (val > 0b100) {
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+ qemu_log_mask(LOG_GUEST_ERROR,
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+ "%s: Invalid MCOPRE value: 0x%"PRIx32"\n",
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+ __func__, val);
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+ clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_MCO], false);
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+ } else {
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+ clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_MCO],
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+ 1, 1 << val);
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+ }
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/* MCOSEL */
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val = FIELD_EX32(s->cfgr, CFGR, MCOSEL);
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- assert(val <= 0b111);
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- if (val == 0) {
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+ if (val > 0b111) {
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+ qemu_log_mask(LOG_GUEST_ERROR,
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+ "%s: Invalid MCOSEL value: 0x%"PRIx32"\n",
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+ __func__, val);
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clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_MCO], false);
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} else {
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- clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_MCO], true);
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- clock_mux_set_source(&s->clock_muxes[RCC_CLOCK_MUX_MCO],
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- val - 1);
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+ if (val == 0) {
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+ clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_MCO], false);
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+ } else {
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+ clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_MCO], true);
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+ clock_mux_set_source(&s->clock_muxes[RCC_CLOCK_MUX_MCO],
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+ val - 1);
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+ }
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}
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/* STOPWUCK */
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