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@@ -317,20 +317,24 @@ CPUArchState *cpu_copy(CPUArchState *env);
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#if !defined(CONFIG_USER_ONLY)
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-/* Flags stored in the low bits of the TLB virtual address. These are
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- * defined so that fast path ram access is all zeros.
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+/*
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+ * Flags stored in the low bits of the TLB virtual address.
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+ * These are defined so that fast path ram access is all zeros.
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* The flags all must be between TARGET_PAGE_BITS and
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* maximum address alignment bit.
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+ *
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+ * Use TARGET_PAGE_BITS_MIN so that these bits are constant
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+ * when TARGET_PAGE_BITS_VARY is in effect.
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*/
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/* Zero if TLB entry is valid. */
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-#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS - 1))
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+#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1))
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/* Set if TLB entry references a clean RAM page. The iotlb entry will
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contain the page physical address. */
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-#define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS - 2))
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+#define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2))
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/* Set if TLB entry is an IO callback. */
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-#define TLB_MMIO (1 << (TARGET_PAGE_BITS - 3))
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+#define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3))
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/* Set if TLB entry contains a watchpoint. */
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-#define TLB_WATCHPOINT (1 << (TARGET_PAGE_BITS - 4))
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+#define TLB_WATCHPOINT (1 << (TARGET_PAGE_BITS_MIN - 4))
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/* Use this mask to check interception with an alignment mask
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* in a TCG backend.
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