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@@ -25,6 +25,8 @@
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#include "sysemu/kvm.h"
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#include "util/event_notifier-posix.c"
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+static void probe_pci_info(PCIDevice *dev, Error **errp);
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+
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static void proxy_intx_update(PCIDevice *pci_dev)
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{
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PCIProxyDev *dev = PCI_PROXY_DEV(pci_dev);
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@@ -77,6 +79,7 @@ static void pci_proxy_dev_realize(PCIDevice *device, Error **errp)
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{
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ERRP_GUARD();
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PCIProxyDev *dev = PCI_PROXY_DEV(device);
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+ uint8_t *pci_conf = device->config;
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int fd;
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if (!dev->fd) {
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@@ -106,9 +109,14 @@ static void pci_proxy_dev_realize(PCIDevice *device, Error **errp)
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qemu_mutex_init(&dev->io_mutex);
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qio_channel_set_blocking(dev->ioc, true, NULL);
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+ pci_conf[PCI_LATENCY_TIMER] = 0xff;
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+ pci_conf[PCI_INTERRUPT_PIN] = 0x01;
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+
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proxy_memory_listener_configure(&dev->proxy_listener, dev->ioc);
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setup_irqfd(dev);
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+
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+ probe_pci_info(PCI_DEVICE(dev), errp);
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}
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static void pci_proxy_dev_exit(PCIDevice *pdev)
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@@ -274,3 +282,79 @@ const MemoryRegionOps proxy_mr_ops = {
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.max_access_size = 8,
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},
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};
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+
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+static void probe_pci_info(PCIDevice *dev, Error **errp)
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+{
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+ PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
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+ uint32_t orig_val, new_val, base_class, val;
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+ PCIProxyDev *pdev = PCI_PROXY_DEV(dev);
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+ DeviceClass *dc = DEVICE_CLASS(pc);
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+ uint8_t type;
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+ int i, size;
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+
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+ config_op_send(pdev, PCI_VENDOR_ID, &val, 2, MPQEMU_CMD_PCI_CFGREAD);
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+ pc->vendor_id = (uint16_t)val;
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+
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+ config_op_send(pdev, PCI_DEVICE_ID, &val, 2, MPQEMU_CMD_PCI_CFGREAD);
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+ pc->device_id = (uint16_t)val;
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+
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+ config_op_send(pdev, PCI_CLASS_DEVICE, &val, 2, MPQEMU_CMD_PCI_CFGREAD);
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+ pc->class_id = (uint16_t)val;
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+
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+ config_op_send(pdev, PCI_SUBSYSTEM_ID, &val, 2, MPQEMU_CMD_PCI_CFGREAD);
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+ pc->subsystem_id = (uint16_t)val;
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+
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+ base_class = pc->class_id >> 4;
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+ switch (base_class) {
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+ case PCI_BASE_CLASS_BRIDGE:
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+ set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
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+ break;
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+ case PCI_BASE_CLASS_STORAGE:
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+ set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
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+ break;
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+ case PCI_BASE_CLASS_NETWORK:
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+ set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
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+ break;
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+ case PCI_BASE_CLASS_INPUT:
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+ set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
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+ break;
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+ case PCI_BASE_CLASS_DISPLAY:
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+ set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
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+ break;
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+ case PCI_BASE_CLASS_PROCESSOR:
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+ set_bit(DEVICE_CATEGORY_CPU, dc->categories);
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+ break;
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+ default:
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+ set_bit(DEVICE_CATEGORY_MISC, dc->categories);
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+ break;
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+ }
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+
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+ for (i = 0; i < PCI_NUM_REGIONS; i++) {
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+ config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &orig_val, 4,
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+ MPQEMU_CMD_PCI_CFGREAD);
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+ new_val = 0xffffffff;
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+ config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &new_val, 4,
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+ MPQEMU_CMD_PCI_CFGWRITE);
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+ config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &new_val, 4,
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+ MPQEMU_CMD_PCI_CFGREAD);
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+ size = (~(new_val & 0xFFFFFFF0)) + 1;
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+ config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &orig_val, 4,
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+ MPQEMU_CMD_PCI_CFGWRITE);
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+ type = (new_val & 0x1) ?
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+ PCI_BASE_ADDRESS_SPACE_IO : PCI_BASE_ADDRESS_SPACE_MEMORY;
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+
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+ if (size) {
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+ g_autofree char *name;
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+ pdev->region[i].dev = pdev;
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+ pdev->region[i].present = true;
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+ if (type == PCI_BASE_ADDRESS_SPACE_MEMORY) {
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+ pdev->region[i].memory = true;
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+ }
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+ name = g_strdup_printf("bar-region-%d", i);
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+ memory_region_init_io(&pdev->region[i].mr, OBJECT(pdev),
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+ &proxy_mr_ops, &pdev->region[i],
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+ name, size);
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+ pci_register_bar(dev, i, type, &pdev->region[i].mr);
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+ }
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+ }
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+}
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