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@@ -132,6 +132,11 @@ FIELD(CPUCFG1, HP, 24, 1)
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FIELD(CPUCFG1, IOCSR_BRD, 25, 1)
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FIELD(CPUCFG1, IOCSR_BRD, 25, 1)
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FIELD(CPUCFG1, MSG_INT, 26, 1)
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FIELD(CPUCFG1, MSG_INT, 26, 1)
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+/* cpucfg[1].arch */
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+#define CPUCFG1_ARCH_LA32R 0
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+#define CPUCFG1_ARCH_LA32 1
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+#define CPUCFG1_ARCH_LA64 2
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+
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/* cpucfg[2] bits */
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/* cpucfg[2] bits */
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FIELD(CPUCFG2, FP, 0, 1)
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FIELD(CPUCFG2, FP, 0, 1)
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FIELD(CPUCFG2, FP_SP, 1, 1)
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FIELD(CPUCFG2, FP_SP, 1, 1)
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@@ -421,6 +426,11 @@ static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch)
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#endif
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#endif
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}
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}
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+static inline bool is_la64(CPULoongArchState *env)
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+{
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+ return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) == CPUCFG1_ARCH_LA64;
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+}
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+
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/*
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/*
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* LoongArch CPUs hardware flags.
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* LoongArch CPUs hardware flags.
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*/
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*/
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