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@@ -515,12 +515,12 @@ out:
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return frame_size;
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}
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-static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t tx_ring,
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- uint32_t tx_descriptor)
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+static void ftgmac100_do_tx(FTGMAC100State *s, uint64_t tx_ring,
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+ uint64_t tx_descriptor)
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{
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int frame_size = 0;
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uint8_t *ptr = s->frame;
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- uint32_t addr = tx_descriptor;
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+ uint64_t addr = tx_descriptor;
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uint32_t flags = 0;
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while (1) {
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@@ -726,9 +726,9 @@ static uint64_t ftgmac100_read(void *opaque, hwaddr addr, unsigned size)
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case FTGMAC100_MATH1:
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return s->math[1];
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case FTGMAC100_RXR_BADR:
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- return s->rx_ring;
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+ return extract64(s->rx_ring, 0, 32);
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case FTGMAC100_NPTXR_BADR:
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- return s->tx_ring;
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+ return extract64(s->tx_ring, 0, 32);
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case FTGMAC100_ITC:
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return s->itc;
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case FTGMAC100_DBLAC:
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@@ -799,9 +799,8 @@ static void ftgmac100_write(void *opaque, hwaddr addr,
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HWADDR_PRIx "\n", __func__, value);
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return;
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}
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-
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- s->rx_ring = value;
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- s->rx_descriptor = s->rx_ring;
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+ s->rx_ring = deposit64(s->rx_ring, 0, 32, value);
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+ s->rx_descriptor = deposit64(s->rx_descriptor, 0, 32, value);
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break;
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case FTGMAC100_RBSR: /* DMA buffer size */
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@@ -814,8 +813,8 @@ static void ftgmac100_write(void *opaque, hwaddr addr,
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HWADDR_PRIx "\n", __func__, value);
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return;
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}
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- s->tx_ring = value;
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- s->tx_descriptor = s->tx_ring;
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+ s->tx_ring = deposit64(s->tx_ring, 0, 32, value);
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+ s->tx_descriptor = deposit64(s->tx_descriptor, 0, 32, value);
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break;
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case FTGMAC100_NPTXPD: /* Trigger transmit */
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@@ -957,7 +956,7 @@ static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf,
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FTGMAC100State *s = FTGMAC100(qemu_get_nic_opaque(nc));
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FTGMAC100Desc bd;
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uint32_t flags = 0;
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- uint32_t addr;
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+ uint64_t addr;
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uint32_t crc;
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uint32_t buf_addr;
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uint8_t *crc_ptr;
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@@ -1126,18 +1125,14 @@ static void ftgmac100_realize(DeviceState *dev, Error **errp)
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static const VMStateDescription vmstate_ftgmac100 = {
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.name = TYPE_FTGMAC100,
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- .version_id = 1,
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- .minimum_version_id = 1,
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+ .version_id = 2,
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+ .minimum_version_id = 2,
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.fields = (const VMStateField[]) {
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VMSTATE_UINT32(irq_state, FTGMAC100State),
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VMSTATE_UINT32(isr, FTGMAC100State),
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VMSTATE_UINT32(ier, FTGMAC100State),
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VMSTATE_UINT32(rx_enabled, FTGMAC100State),
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- VMSTATE_UINT32(rx_ring, FTGMAC100State),
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VMSTATE_UINT32(rbsr, FTGMAC100State),
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- VMSTATE_UINT32(tx_ring, FTGMAC100State),
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- VMSTATE_UINT32(rx_descriptor, FTGMAC100State),
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- VMSTATE_UINT32(tx_descriptor, FTGMAC100State),
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VMSTATE_UINT32_ARRAY(math, FTGMAC100State, 2),
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VMSTATE_UINT32(itc, FTGMAC100State),
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VMSTATE_UINT32(aptcr, FTGMAC100State),
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@@ -1156,6 +1151,10 @@ static const VMStateDescription vmstate_ftgmac100 = {
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VMSTATE_UINT32(phy_int_mask, FTGMAC100State),
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VMSTATE_UINT32(txdes0_edotr, FTGMAC100State),
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VMSTATE_UINT32(rxdes0_edorr, FTGMAC100State),
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+ VMSTATE_UINT64(rx_ring, FTGMAC100State),
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+ VMSTATE_UINT64(tx_ring, FTGMAC100State),
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+ VMSTATE_UINT64(rx_descriptor, FTGMAC100State),
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+ VMSTATE_UINT64(tx_descriptor, FTGMAC100State),
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VMSTATE_END_OF_LIST()
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}
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};
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