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+@c man begin SYNOPSIS
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+QEMU / KVM CPU model configuration
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+@c man end
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+
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+@c man begin DESCRIPTION
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+
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+@menu
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+* recommendations_cpu_models_x86:: Recommendations for KVM CPU model configuration on x86 hosts
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+* cpu_model_syntax_apps:: Syntax for configuring CPU models
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+@end menu
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+
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+QEMU / KVM virtualization supports two ways to configure CPU models
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+
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+@table @option
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+
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+@item Host passthrough
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+
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+This passes the host CPU model features, model, stepping, exactly to the
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+guest. Note that KVM may filter out some host CPU model features if they
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+cannot be supported with virtualization. Live migration is unsafe when
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+this mode is used as libvirt / QEMU cannot guarantee a stable CPU is
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+exposed to the guest across hosts. This is the recommended CPU to use,
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+provided live migration is not required.
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+
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+@item Named model
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+
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+QEMU comes with a number of predefined named CPU models, that typically
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+refer to specific generations of hardware released by Intel and AMD.
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+These allow the guest VMs to have a degree of isolation from the host CPU,
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+allowing greater flexibility in live migrating between hosts with differing
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+hardware.
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+@end table
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+
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+In both cases, it is possible to optionally add or remove individual CPU
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+features, to alter what is presented to the guest by default.
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+
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+Libvirt supports a third way to configure CPU models known as "Host model".
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+This uses the QEMU "Named model" feature, automatically picking a CPU model
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+that is similar the host CPU, and then adding extra features to approximate
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+the host model as closely as possible. This does not guarantee the CPU family,
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+stepping, etc will precisely match the host CPU, as they would with "Host
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+passthrough", but gives much of the benefit of passthrough, while making
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+live migration safe.
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+
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+@node recommendations_cpu_models_x86
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+@subsection Recommendations for KVM CPU model configuration on x86 hosts
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+
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+The information that follows provides recommendations for configuring
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+CPU models on x86 hosts. The goals are to maximise performance, while
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+protecting guest OS against various CPU hardware flaws, and optionally
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+enabling live migration between hosts with hetergeneous CPU models.
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+
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+@menu
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+* preferred_cpu_models_intel_x86:: Preferred CPU models for Intel x86 hosts
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+* important_cpu_features_intel_x86:: Important CPU features for Intel x86 hosts
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+* preferred_cpu_models_amd_x86:: Preferred CPU models for AMD x86 hosts
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+* important_cpu_features_amd_x86:: Important CPU features for AMD x86 hosts
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+* default_cpu_models_x86:: Default x86 CPU models
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+* other_non_recommended_cpu_models_x86:: Other non-recommended x86 CPUs
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+@end menu
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+
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+@node preferred_cpu_models_intel_x86
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+@subsubsection Preferred CPU models for Intel x86 hosts
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+
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+The following CPU models are preferred for use on Intel hosts. Administrators /
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+applications are recommended to use the CPU model that matches the generation
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+of the host CPUs in use. In a deployment with a mixture of host CPU models
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+between machines, if live migration compatibility is required, use the newest
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+CPU model that is compatible across all desired hosts.
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+
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+@table @option
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+@item @code{Skylake-Server}
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+@item @code{Skylake-Server-IBRS}
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+
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+Intel Xeon Processor (Skylake, 2016)
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+
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+
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+@item @code{Skylake-Client}
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+@item @code{Skylake-Client-IBRS}
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+
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+Intel Core Processor (Skylake, 2015)
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+
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+
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+@item @code{Broadwell}
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+@item @code{Broadwell-IBRS}
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+@item @code{Broadwell-noTSX}
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+@item @code{Broadwell-noTSX-IBRS}
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+
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+Intel Core Processor (Broadwell, 2014)
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+
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+
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+@item @code{Haswell}
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+@item @code{Haswell-IBRS}
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+@item @code{Haswell-noTSX}
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+@item @code{Haswell-noTSX-IBRS}
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+
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+Intel Core Processor (Haswell, 2013)
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+
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+
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+@item @code{IvyBridge}
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+@item @code{IvyBridge-IBRS}
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+
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+Intel Xeon E3-12xx v2 (Ivy Bridge, 2012)
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+
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+
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+@item @code{SandyBridge}
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+@item @code{SandyBridge-IBRS}
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+
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+Intel Xeon E312xx (Sandy Bridge, 2011)
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+
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+
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+@item @code{Westmere}
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+@item @code{Westmere-IBRS}
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+
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+Westmere E56xx/L56xx/X56xx (Nehalem-C, 2010)
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+
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+
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+@item @code{Nehalem}
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+@item @code{Nehalem-IBRS}
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+
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+Intel Core i7 9xx (Nehalem Class Core i7, 2008)
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+
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+
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+@item @code{Penryn}
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+
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+Intel Core 2 Duo P9xxx (Penryn Class Core 2, 2007)
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+
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+
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+@item @code{Conroe}
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+
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+Intel Celeron_4x0 (Conroe/Merom Class Core 2, 2006)
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+
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+@end table
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+
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+@node important_cpu_features_intel_x86
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+@subsubsection Important CPU features for Intel x86 hosts
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+
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+The following are important CPU features that should be used on Intel x86
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+hosts, when available in the host CPU. Some of them require explicit
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+configuration to enable, as they are not included by default in some, or all,
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+of the named CPU models listed above. In general all of these features are
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+included if using "Host passthrough" or "Host model".
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+
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+
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+@table @option
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+
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+@item @code{pcid}
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+
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+Recommended to mitigate the cost of the Meltdown (CVE-2017-5754) fix
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+
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+Included by default in Haswell, Broadwell & Skylake Intel CPU models.
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+
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+Should be explicitly turned on for Westmere, SandyBridge, and IvyBridge
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+Intel CPU models. Note that some desktop/mobile Westmere CPUs cannot
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+support this feature.
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+
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+
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+@item @code{spec-ctrl}
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+
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+Required to enable the Spectre (CVE-2017-5753 and CVE-2017-5715) fix,
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+in cases where retpolines are not sufficient.
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+
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+Included by default in Intel CPU models with -IBRS suffix.
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+
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+Must be explicitly turned on for Intel CPU models without -IBRS suffix.
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+
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+Requires the host CPU microcode to support this feature before it
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+can be used for guest CPUs.
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+
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+
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+@item @code{ssbd}
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+
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+Required to enable the CVE-2018-3639 fix
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+
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+Not included by default in any Intel CPU model.
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+
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+Must be explicitly turned on for all Intel CPU models.
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+
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+Requires the host CPU microcode to support this feature before it
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+can be used for guest CPUs.
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+
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+
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+@item @code{pdpe1gb}
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+
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+Recommended to allow guest OS to use 1GB size pages
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+
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+Not included by default in any Intel CPU model.
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+
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+Should be explicitly turned on for all Intel CPU models.
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+
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+Note that not all CPU hardware will support this feature.
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+@end table
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+
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+
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+@node preferred_cpu_models_amd_x86
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+@subsubsection Preferred CPU models for AMD x86 hosts
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+
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+The following CPU models are preferred for use on Intel hosts. Administrators /
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+applications are recommended to use the CPU model that matches the generation
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+of the host CPUs in use. In a deployment with a mixture of host CPU models
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+between machines, if live migration compatibility is required, use the newest
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+CPU model that is compatible across all desired hosts.
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+
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+@table @option
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+
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+@item @code{EPYC}
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+@item @code{EPYC-IBPB}
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+
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+AMD EPYC Processor (2017)
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+
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+
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+@item @code{Opteron_G5}
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+
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+AMD Opteron 63xx class CPU (2012)
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+
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+
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+@item @code{Opteron_G4}
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+
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+AMD Opteron 62xx class CPU (2011)
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+
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+
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+@item @code{Opteron_G3}
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+
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+AMD Opteron 23xx (Gen 3 Class Opteron, 2009)
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+
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+
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+@item @code{Opteron_G2}
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+
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+AMD Opteron 22xx (Gen 2 Class Opteron, 2006)
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+
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+
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+@item @code{Opteron_G1}
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+
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+AMD Opteron 240 (Gen 1 Class Opteron, 2004)
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+@end table
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+
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+@node important_cpu_features_amd_x86
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+@subsubsection Important CPU features for AMD x86 hosts
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+
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+The following are important CPU features that should be used on AMD x86
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+hosts, when available in the host CPU. Some of them require explicit
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+configuration to enable, as they are not included by default in some, or all,
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+of the named CPU models listed above. In general all of these features are
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+included if using "Host passthrough" or "Host model".
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+
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+
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+@table @option
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+
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+@item @code{ibpb}
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+
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+Required to enable the Spectre (CVE-2017-5753 and CVE-2017-5715) fix,
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+in cases where retpolines are not sufficient.
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+
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+Included by default in AMD CPU models with -IBPB suffix.
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+
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+Must be explicitly turned on for AMD CPU models without -IBPB suffix.
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+
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+Requires the host CPU microcode to support this feature before it
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+can be used for guest CPUs.
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+
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+
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+@item @code{virt-ssbd}
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+
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+Required to enable the CVE-2018-3639 fix
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+
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+Not included by default in any AMD CPU model.
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+
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+Must be explicitly turned on for all AMD CPU models.
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+
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+This should be provided to guests, even if amd-ssbd is also
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+provided, for maximum guest compatibility.
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+
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+Note for some QEMU / libvirt versions, this must be force enabled
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+when when using "Host model", because this is a virtual feature
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+that doesn't exist in the physical host CPUs.
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+
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+
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+@item @code{amd-ssbd}
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+
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+Required to enable the CVE-2018-3639 fix
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+
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+Not included by default in any AMD CPU model.
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+
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+Must be explicitly turned on for all AMD CPU models.
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+
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+This provides higher performance than virt-ssbd so should be
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+exposed to guests whenever available in the host. virt-ssbd
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+should none the less also be exposed for maximum guest
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+compatability as some kernels only know about virt-ssbd.
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+
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+
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+@item @code{amd-no-ssb}
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+
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+Recommended to indicate the host is not vulnerable CVE-2018-3639
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+
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+Not included by default in any AMD CPU model.
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+
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+Future hardware genarations of CPU will not be vulnerable to
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+CVE-2018-3639, and thus the guest should be told not to enable
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+its mitigations, by exposing amd-no-ssb. This is mutually
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+exclusive with virt-ssbd and amd-ssbd.
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+
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+
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+@item @code{pdpe1gb}
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+
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+Recommended to allow guest OS to use 1GB size pages
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+
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+Not included by default in any AMD CPU model.
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+
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+Should be explicitly turned on for all AMD CPU models.
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+
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+Note that not all CPU hardware will support this feature.
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+@end table
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+
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+
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+@node default_cpu_models_x86
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+@subsubsection Default x86 CPU models
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+
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+The default QEMU CPU models are designed such that they can run on all hosts.
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+If an application does not wish to do perform any host compatibility checks
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+before launching guests, the default is guaranteed to work.
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+
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+The default CPU models will, however, leave the guest OS vulnerable to various
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+CPU hardware flaws, so their use is strongly discouraged. Applications should
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+follow the earlier guidance to setup a better CPU configuration, with host
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+passthrough recommended if live migration is not needed.
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+
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+@table @option
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+@item @code{qemu32}
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+@item @code{qemu64}
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+
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+QEMU Virtual CPU version 2.5+ (32 & 64 bit variants)
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+
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+qemu64 is used for x86_64 guests and qemu32 is used for i686 guests, when no
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+-cpu argument is given to QEMU, or no <cpu> is provided in libvirt XML.
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+@end table
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+
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+
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+@node other_non_recommended_cpu_models_x86
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+@subsubsection Other non-recommended x86 CPUs
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+
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+The following CPUs models are compatible with most AMD and Intel x86 hosts, but
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+their usage is discouraged, as they expose a very limited featureset, which
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+prevents guests having optimal performance.
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+
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+@table @option
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+
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+@item @code{kvm32}
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+@item @code{kvm64}
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+
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+Common KVM processor (32 & 64 bit variants)
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+
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+Legacy models just for historical compatibility with ancient QEMU versions.
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+
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+
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+@item @code{486}
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+@item @code{athlon}
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+@item @code{phenom}
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+@item @code{coreduo}
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+@item @code{core2duo}
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+@item @code{n270}
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+@item @code{pentium}
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+@item @code{pentium2}
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+@item @code{pentium3}
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+
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+Various very old x86 CPU models, mostly predating the introduction of
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+hardware assisted virtualization, that should thus not be required for
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+running virtual machines.
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+@end table
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+
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+@node cpu_model_syntax_apps
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+@subsection Syntax for configuring CPU models
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+
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+The example below illustrate the approach to configuring the various
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+CPU models / features in QEMU and libvirt
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+
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+@menu
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+* cpu_model_syntax_qemu:: QEMU command line
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+* cpu_model_syntax_libvirt:: Libvirt guest XML
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+@end menu
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+
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+@node cpu_model_syntax_qemu
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+@subsubsection QEMU command line
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+
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+@table @option
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+
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+@item Host passthrough
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+
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+@example
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+ $ qemu-system-x86_64 -cpu host
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+@end example
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+
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+With feature customization:
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+
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+@example
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+ $ qemu-system-x86_64 -cpu host,-vmx,...
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+@end example
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+
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+@item Named CPU models
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+
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+@example
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+ $ qemu-system-x86_64 -cpu Westmere
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+@end example
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+
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+With feature customization:
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+
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+@example
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+ $ qemu-system-x86_64 -cpu Westmere,+pcid,...
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+@end example
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+
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+@end table
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+
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+@node cpu_model_syntax_libvirt
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+@subsubsection Libvirt guest XML
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+
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+@table @option
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+
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+@item Host passthrough
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+
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+@example
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+ <cpu mode='host-passthrough'/>
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+@end example
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+
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+With feature customization:
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+
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+@example
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+ <cpu mode='host-passthrough'>
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+ <feature name="vmx" policy="disable"/>
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+ ...
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+ </cpu>
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+@end example
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|
|
+
|
|
|
+@item Host model
|
|
|
+
|
|
|
+@example
|
|
|
+ <cpu mode='host-model'/>
|
|
|
+@end example
|
|
|
+
|
|
|
+With feature customization:
|
|
|
+
|
|
|
+@example
|
|
|
+ <cpu mode='host-model'>
|
|
|
+ <feature name="vmx" policy="disable"/>
|
|
|
+ ...
|
|
|
+ </cpu>
|
|
|
+@end example
|
|
|
+
|
|
|
+@item Named model
|
|
|
+
|
|
|
+@example
|
|
|
+ <cpu mode='custom'>
|
|
|
+ <model name="Westmere"/>
|
|
|
+ </cpu>
|
|
|
+@end example
|
|
|
+
|
|
|
+With feature customization:
|
|
|
+
|
|
|
+@example
|
|
|
+ <cpu mode='custom'>
|
|
|
+ <model name="Westmere"/>
|
|
|
+ <feature name="pcid" policy="require"/>
|
|
|
+ ...
|
|
|
+ </cpu>
|
|
|
+@end example
|
|
|
+
|
|
|
+@end table
|
|
|
+
|
|
|
+@c man end
|
|
|
+
|
|
|
+@ignore
|
|
|
+
|
|
|
+@setfilename qemu-cpu-models
|
|
|
+@settitle QEMU / KVM CPU model configuration
|
|
|
+
|
|
|
+@c man begin SEEALSO
|
|
|
+The HTML documentation of QEMU for more precise information and Linux
|
|
|
+user mode emulator invocation.
|
|
|
+@c man end
|
|
|
+
|
|
|
+@c man begin AUTHOR
|
|
|
+Daniel P. Berrange
|
|
|
+@c man end
|
|
|
+
|
|
|
+@end ignore
|
Peter Maydell