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@@ -25,6 +25,7 @@
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "hw/ppc/mac.h"
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+#include "hw/intc/heathrow_pic.h"
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/* debug PIC */
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//#define DEBUG_PIC
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@@ -36,39 +37,27 @@
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#define PIC_DPRINTF(fmt, ...)
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#endif
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-typedef struct HeathrowPIC {
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- uint32_t events;
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- uint32_t mask;
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- uint32_t levels;
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- uint32_t level_triggered;
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-} HeathrowPIC;
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-
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-typedef struct HeathrowPICS {
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- MemoryRegion mem;
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- HeathrowPIC pics[2];
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- qemu_irq *irqs;
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-} HeathrowPICS;
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-
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-static inline int check_irq(HeathrowPIC *pic)
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+static inline int heathrow_check_irq(HeathrowPICState *pic)
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{
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return (pic->events | (pic->levels & pic->level_triggered)) & pic->mask;
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}
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/* update the CPU irq state */
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-static void heathrow_pic_update(HeathrowPICS *s)
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+static void heathrow_update_irq(HeathrowState *s)
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{
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- if (check_irq(&s->pics[0]) || check_irq(&s->pics[1])) {
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+ if (heathrow_check_irq(&s->pics[0]) ||
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+ heathrow_check_irq(&s->pics[1])) {
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qemu_irq_raise(s->irqs[0]);
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} else {
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qemu_irq_lower(s->irqs[0]);
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}
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}
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-static void pic_write(void *opaque, hwaddr addr,
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- uint64_t value, unsigned size)
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+static void heathrow_write(void *opaque, hwaddr addr,
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+ uint64_t value, unsigned size)
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{
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- HeathrowPICS *s = opaque;
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- HeathrowPIC *pic;
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+ HeathrowState *s = opaque;
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+ HeathrowPICState *pic;
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unsigned int n;
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n = ((addr & 0xfff) - 0x10) >> 4;
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@@ -79,24 +68,24 @@ static void pic_write(void *opaque, hwaddr addr,
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switch(addr & 0xf) {
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case 0x04:
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pic->mask = value;
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- heathrow_pic_update(s);
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+ heathrow_update_irq(s);
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break;
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case 0x08:
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/* do not reset level triggered IRQs */
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value &= ~pic->level_triggered;
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pic->events &= ~value;
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- heathrow_pic_update(s);
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+ heathrow_update_irq(s);
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break;
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default:
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break;
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}
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}
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-static uint64_t pic_read(void *opaque, hwaddr addr,
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- unsigned size)
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+static uint64_t heathrow_read(void *opaque, hwaddr addr,
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+ unsigned size)
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{
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- HeathrowPICS *s = opaque;
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- HeathrowPIC *pic;
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+ HeathrowState *s = opaque;
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+ HeathrowPICState *pic;
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unsigned int n;
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uint32_t value;
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@@ -124,16 +113,16 @@ static uint64_t pic_read(void *opaque, hwaddr addr,
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return value;
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}
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-static const MemoryRegionOps heathrow_pic_ops = {
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- .read = pic_read,
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- .write = pic_write,
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+static const MemoryRegionOps heathrow_ops = {
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+ .read = heathrow_read,
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+ .write = heathrow_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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-static void heathrow_pic_set_irq(void *opaque, int num, int level)
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+static void heathrow_set_irq(void *opaque, int num, int level)
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{
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- HeathrowPICS *s = opaque;
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- HeathrowPIC *pic;
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+ HeathrowState *s = opaque;
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+ HeathrowPICState *pic;
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unsigned int irq_bit;
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#if defined(DEBUG)
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@@ -153,7 +142,7 @@ static void heathrow_pic_set_irq(void *opaque, int num, int level)
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} else {
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pic->levels &= ~irq_bit;
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}
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- heathrow_pic_update(s);
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+ heathrow_update_irq(s);
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}
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static const VMStateDescription vmstate_heathrow_pic_one = {
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@@ -161,54 +150,79 @@ static const VMStateDescription vmstate_heathrow_pic_one = {
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (VMStateField[]) {
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- VMSTATE_UINT32(events, HeathrowPIC),
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- VMSTATE_UINT32(mask, HeathrowPIC),
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- VMSTATE_UINT32(levels, HeathrowPIC),
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- VMSTATE_UINT32(level_triggered, HeathrowPIC),
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+ VMSTATE_UINT32(events, HeathrowPICState),
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+ VMSTATE_UINT32(mask, HeathrowPICState),
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+ VMSTATE_UINT32(levels, HeathrowPICState),
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+ VMSTATE_UINT32(level_triggered, HeathrowPICState),
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VMSTATE_END_OF_LIST()
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}
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};
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-static const VMStateDescription vmstate_heathrow_pic = {
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+static const VMStateDescription vmstate_heathrow = {
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.name = "heathrow_pic",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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- VMSTATE_STRUCT_ARRAY(pics, HeathrowPICS, 2, 1,
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- vmstate_heathrow_pic_one, HeathrowPIC),
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+ VMSTATE_STRUCT_ARRAY(pics, HeathrowState, 2, 1,
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+ vmstate_heathrow_pic_one, HeathrowPICState),
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VMSTATE_END_OF_LIST()
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}
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};
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-static void heathrow_pic_reset_one(HeathrowPIC *s)
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+static void heathrow_reset(DeviceState *d)
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{
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- memset(s, '\0', sizeof(HeathrowPIC));
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+ HeathrowState *s = HEATHROW(d);
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+
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+ s->pics[0].level_triggered = 0;
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+ s->pics[1].level_triggered = 0x1ff00000;
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}
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-static void heathrow_pic_reset(void *opaque)
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+static void heathrow_init(Object *obj)
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{
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- HeathrowPICS *s = opaque;
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-
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- heathrow_pic_reset_one(&s->pics[0]);
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- heathrow_pic_reset_one(&s->pics[1]);
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+ HeathrowState *s = HEATHROW(obj);
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- s->pics[0].level_triggered = 0;
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- s->pics[1].level_triggered = 0x1ff00000;
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+ memory_region_init_io(&s->mem, OBJECT(s), &heathrow_ops, s,
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+ "heathrow-pic", 0x1000);
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}
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qemu_irq *heathrow_pic_init(MemoryRegion **pmem,
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int nb_cpus, qemu_irq **irqs)
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{
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- HeathrowPICS *s;
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+ DeviceState *d;
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+ HeathrowState *s;
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- s = g_malloc0(sizeof(HeathrowPICS));
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+ d = qdev_create(NULL, TYPE_HEATHROW);
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+ qdev_init_nofail(d);
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+
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+ s = HEATHROW(d);
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/* only 1 CPU */
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s->irqs = irqs[0];
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- memory_region_init_io(&s->mem, NULL, &heathrow_pic_ops, s,
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- "heathrow-pic", 0x1000);
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+
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*pmem = &s->mem;
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- vmstate_register(NULL, -1, &vmstate_heathrow_pic, s);
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- qemu_register_reset(heathrow_pic_reset, s);
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- return qemu_allocate_irqs(heathrow_pic_set_irq, s, 64);
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+ return qemu_allocate_irqs(heathrow_set_irq, s, HEATHROW_NUM_IRQS);
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+}
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+
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+static void heathrow_class_init(ObjectClass *oc, void *data)
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+{
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+ DeviceClass *dc = DEVICE_CLASS(oc);
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+
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+ dc->reset = heathrow_reset;
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+ dc->vmsd = &vmstate_heathrow;
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+ set_bit(DEVICE_CATEGORY_MISC, dc->categories);
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}
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+
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+static const TypeInfo heathrow_type_info = {
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+ .name = TYPE_HEATHROW,
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+ .parent = TYPE_SYS_BUS_DEVICE,
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+ .instance_size = sizeof(HeathrowState),
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+ .instance_init = heathrow_init,
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+ .class_init = heathrow_class_init,
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+};
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+
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+static void heathrow_register_types(void)
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+{
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+ type_register_static(&heathrow_type_info);
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+}
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+
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+type_init(heathrow_register_types)
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