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@@ -7409,8 +7409,11 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
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gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
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gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
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} else {
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} else {
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modrm = ldub_code(s->pc++);
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modrm = ldub_code(s->pc++);
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- if ((modrm & 0xc0) != 0xc0)
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- goto illegal_op;
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+ /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
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+ * AMD documentation (24594.pdf) and testing of
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+ * intel 386 and 486 processors all show that the mod bits
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+ * are assumed to be 1's, regardless of actual values.
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+ */
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rm = (modrm & 7) | REX_B(s);
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rm = (modrm & 7) | REX_B(s);
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reg = ((modrm >> 3) & 7) | rex_r;
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reg = ((modrm >> 3) & 7) | rex_r;
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if (CODE64(s))
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if (CODE64(s))
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@@ -7451,8 +7454,11 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
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gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
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gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
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} else {
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} else {
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modrm = ldub_code(s->pc++);
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modrm = ldub_code(s->pc++);
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- if ((modrm & 0xc0) != 0xc0)
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- goto illegal_op;
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+ /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
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+ * AMD documentation (24594.pdf) and testing of
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+ * intel 386 and 486 processors all show that the mod bits
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+ * are assumed to be 1's, regardless of actual values.
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+ */
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rm = (modrm & 7) | REX_B(s);
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rm = (modrm & 7) | REX_B(s);
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reg = ((modrm >> 3) & 7) | rex_r;
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reg = ((modrm >> 3) & 7) | rex_r;
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if (CODE64(s))
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if (CODE64(s))
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