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@@ -50,7 +50,7 @@ typedef struct MiscState {
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uint8_t diag, mctrl;
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uint32_t sysctrl;
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uint16_t leds;
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- target_phys_addr_t power_base;
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+ CPUState *env;
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} MiscState;
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#define MISC_SIZE 1
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@@ -62,8 +62,6 @@ typedef struct MiscState {
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#define MISC_MASK 0x0fff0000
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#define MISC_LEDS 0x01600000
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#define MISC_CFG 0x01800000
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-#define MISC_AUX1 0x01900000
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-#define MISC_AUX2 0x01910000
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#define MISC_DIAG 0x01a00000
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#define MISC_MDM 0x01b00000
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#define MISC_SYS 0x01f00000
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@@ -122,21 +120,6 @@ static void slavio_misc_mem_writeb(void *opaque, target_phys_addr_t addr,
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s->config = val & 0xff;
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slavio_misc_update_irq(s);
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break;
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- case MISC_AUX1:
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- MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff);
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- s->aux1 = val & 0xff;
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- break;
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- case MISC_AUX2:
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- val &= AUX2_PWRINTCLR | AUX2_PWROFF;
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- MISC_DPRINTF("Write aux2 %2.2x\n", val);
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- val |= s->aux2 & AUX2_PWRFAIL;
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- if (val & AUX2_PWRINTCLR) // Clear Power Fail int
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- val &= AUX2_PWROFF;
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- s->aux2 = val;
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- if (val & AUX2_PWROFF)
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- qemu_system_shutdown_request();
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- slavio_misc_update_irq(s);
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- break;
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case MISC_DIAG:
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MISC_DPRINTF("Write diag %2.2x\n", val & 0xff);
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s->diag = val & 0xff;
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@@ -146,10 +129,6 @@ static void slavio_misc_mem_writeb(void *opaque, target_phys_addr_t addr,
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s->mctrl = val & 0xff;
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break;
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default:
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- if (addr == s->power_base) {
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- MISC_DPRINTF("Write power management %2.2x\n", val & 0xff);
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- cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
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- }
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break;
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}
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}
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@@ -164,14 +143,6 @@ static uint32_t slavio_misc_mem_readb(void *opaque, target_phys_addr_t addr)
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ret = s->config;
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MISC_DPRINTF("Read config %2.2x\n", ret);
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break;
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- case MISC_AUX1:
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- ret = s->aux1;
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- MISC_DPRINTF("Read aux1 %2.2x\n", ret);
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- break;
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- case MISC_AUX2:
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- ret = s->aux2;
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- MISC_DPRINTF("Read aux2 %2.2x\n", ret);
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- break;
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case MISC_DIAG:
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ret = s->diag;
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MISC_DPRINTF("Read diag %2.2x\n", ret);
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@@ -181,9 +152,6 @@ static uint32_t slavio_misc_mem_readb(void *opaque, target_phys_addr_t addr)
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MISC_DPRINTF("Read modem control %2.2x\n", ret);
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break;
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default:
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- if (addr == s->power_base) {
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- MISC_DPRINTF("Read power management %2.2x\n", ret);
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- }
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break;
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}
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return ret;
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@@ -201,6 +169,105 @@ static CPUWriteMemoryFunc *slavio_misc_mem_write[3] = {
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NULL,
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};
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+static void slavio_aux1_mem_writeb(void *opaque, target_phys_addr_t addr,
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+ uint32_t val)
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+{
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+ MiscState *s = opaque;
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+
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+ MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff);
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+ s->aux1 = val & 0xff;
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+}
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+
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+static uint32_t slavio_aux1_mem_readb(void *opaque, target_phys_addr_t addr)
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+{
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+ MiscState *s = opaque;
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+ uint32_t ret = 0;
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+
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+ ret = s->aux1;
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+ MISC_DPRINTF("Read aux1 %2.2x\n", ret);
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+
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+ return ret;
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+}
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+
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+static CPUReadMemoryFunc *slavio_aux1_mem_read[3] = {
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+ slavio_aux1_mem_readb,
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+ NULL,
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+ NULL,
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+};
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+
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+static CPUWriteMemoryFunc *slavio_aux1_mem_write[3] = {
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+ slavio_aux1_mem_writeb,
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+ NULL,
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+ NULL,
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+};
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+
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+static void slavio_aux2_mem_writeb(void *opaque, target_phys_addr_t addr,
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+ uint32_t val)
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+{
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+ MiscState *s = opaque;
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+
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+ val &= AUX2_PWRINTCLR | AUX2_PWROFF;
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+ MISC_DPRINTF("Write aux2 %2.2x\n", val);
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+ val |= s->aux2 & AUX2_PWRFAIL;
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+ if (val & AUX2_PWRINTCLR) // Clear Power Fail int
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+ val &= AUX2_PWROFF;
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+ s->aux2 = val;
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+ if (val & AUX2_PWROFF)
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+ qemu_system_shutdown_request();
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+ slavio_misc_update_irq(s);
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+}
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+
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+static uint32_t slavio_aux2_mem_readb(void *opaque, target_phys_addr_t addr)
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+{
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+ MiscState *s = opaque;
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+ uint32_t ret = 0;
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+
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+ ret = s->aux2;
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+ MISC_DPRINTF("Read aux2 %2.2x\n", ret);
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+
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+ return ret;
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+}
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+
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+static CPUReadMemoryFunc *slavio_aux2_mem_read[3] = {
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+ slavio_aux2_mem_readb,
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+ NULL,
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+ NULL,
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+};
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+
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+static CPUWriteMemoryFunc *slavio_aux2_mem_write[3] = {
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+ slavio_aux2_mem_writeb,
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+ NULL,
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+ NULL,
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+};
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+
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+static void apc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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+{
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+ MiscState *s = opaque;
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+
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+ MISC_DPRINTF("Write power management %2.2x\n", val & 0xff);
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+ cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
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+}
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+
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+static uint32_t apc_mem_readb(void *opaque, target_phys_addr_t addr)
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+{
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+ uint32_t ret = 0;
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+
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+ MISC_DPRINTF("Read power management %2.2x\n", ret);
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+ return ret;
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+}
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+
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+static CPUReadMemoryFunc *apc_mem_read[3] = {
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+ apc_mem_readb,
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+ NULL,
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+ NULL,
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+};
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+
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+static CPUWriteMemoryFunc *apc_mem_write[3] = {
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+ apc_mem_writeb,
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+ NULL,
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+ NULL,
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+};
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+
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static uint32_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr)
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{
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MiscState *s = opaque;
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@@ -338,57 +405,68 @@ static int slavio_misc_load(QEMUFile *f, void *opaque, int version_id)
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}
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void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
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- qemu_irq irq)
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+ target_phys_addr_t aux1_base,
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+ target_phys_addr_t aux2_base, qemu_irq irq,
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+ CPUState *env)
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{
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- int slavio_misc_io_memory;
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+ int io;
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MiscState *s;
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s = qemu_mallocz(sizeof(MiscState));
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if (!s)
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return NULL;
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- /* 8 bit registers */
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- slavio_misc_io_memory = cpu_register_io_memory(0, slavio_misc_mem_read,
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- slavio_misc_mem_write, s);
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- // Slavio control
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- cpu_register_physical_memory(base + MISC_CFG, MISC_SIZE,
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- slavio_misc_io_memory);
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- // AUX 1
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- cpu_register_physical_memory(base + MISC_AUX1, MISC_SIZE,
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- slavio_misc_io_memory);
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- // AUX 2
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- cpu_register_physical_memory(base + MISC_AUX2, MISC_SIZE,
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- slavio_misc_io_memory);
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- // Diagnostics
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- cpu_register_physical_memory(base + MISC_DIAG, MISC_SIZE,
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- slavio_misc_io_memory);
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- // Modem control
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- cpu_register_physical_memory(base + MISC_MDM, MISC_SIZE,
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- slavio_misc_io_memory);
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- // Power management
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- cpu_register_physical_memory(power_base, MISC_SIZE, slavio_misc_io_memory);
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- s->power_base = power_base;
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-
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- /* 16 bit registers */
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- slavio_misc_io_memory = cpu_register_io_memory(0, slavio_led_mem_read,
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- slavio_led_mem_write, s);
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- /* ss600mp diag LEDs */
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- cpu_register_physical_memory(base + MISC_LEDS, MISC_SIZE,
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- slavio_misc_io_memory);
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-
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- /* 32 bit registers */
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- slavio_misc_io_memory = cpu_register_io_memory(0, slavio_sysctrl_mem_read,
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- slavio_sysctrl_mem_write,
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- s);
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- // System control
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- cpu_register_physical_memory(base + MISC_SYS, SYSCTRL_SIZE,
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- slavio_misc_io_memory);
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+ if (base) {
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+ /* 8 bit registers */
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+ io = cpu_register_io_memory(0, slavio_misc_mem_read,
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+ slavio_misc_mem_write, s);
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+ // Slavio control
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+ cpu_register_physical_memory(base + MISC_CFG, MISC_SIZE, io);
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+ // Diagnostics
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+ cpu_register_physical_memory(base + MISC_DIAG, MISC_SIZE, io);
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+ // Modem control
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+ cpu_register_physical_memory(base + MISC_MDM, MISC_SIZE, io);
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+
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+ /* 16 bit registers */
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+ io = cpu_register_io_memory(0, slavio_led_mem_read,
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+ slavio_led_mem_write, s);
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+ /* ss600mp diag LEDs */
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+ cpu_register_physical_memory(base + MISC_LEDS, MISC_SIZE, io);
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+
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+ /* 32 bit registers */
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+ io = cpu_register_io_memory(0, slavio_sysctrl_mem_read,
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+ slavio_sysctrl_mem_write, s);
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+ // System control
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+ cpu_register_physical_memory(base + MISC_SYS, SYSCTRL_SIZE, io);
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+ }
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+
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+ // AUX 1 (Misc System Functions)
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+ if (aux1_base) {
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+ io = cpu_register_io_memory(0, slavio_aux1_mem_read,
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+ slavio_aux1_mem_write, s);
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+ cpu_register_physical_memory(aux1_base, MISC_SIZE, io);
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+ }
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+
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+ // AUX 2 (Software Powerdown Control)
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+ if (aux2_base) {
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+ io = cpu_register_io_memory(0, slavio_aux2_mem_read,
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+ slavio_aux2_mem_write, s);
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+ cpu_register_physical_memory(aux2_base, MISC_SIZE, io);
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+ }
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+
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+ // Power management (APC) XXX: not a Slavio device
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+ if (power_base) {
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+ io = cpu_register_io_memory(0, apc_mem_read, apc_mem_write, s);
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+ cpu_register_physical_memory(power_base, MISC_SIZE, io);
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+ }
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s->irq = irq;
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+ s->env = env;
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register_savevm("slavio_misc", base, 1, slavio_misc_save, slavio_misc_load,
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s);
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qemu_register_reset(slavio_misc_reset, s);
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slavio_misc_reset(s);
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+
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return s;
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}
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