FunctionLoweringInfo.cpp 21 KB

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  1. //===-- FunctionLoweringInfo.cpp ------------------------------------------===//
  2. //
  3. // The LLVM Compiler Infrastructure
  4. //
  5. // This file is distributed under the University of Illinois Open Source
  6. // License. See LICENSE.TXT for details.
  7. //
  8. //===----------------------------------------------------------------------===//
  9. //
  10. // This implements routines for translating functions from LLVM IR into
  11. // Machine IR.
  12. //
  13. //===----------------------------------------------------------------------===//
  14. #include "llvm/CodeGen/FunctionLoweringInfo.h"
  15. #include "llvm/CodeGen/Analysis.h"
  16. #include "llvm/CodeGen/MachineFrameInfo.h"
  17. #include "llvm/CodeGen/MachineFunction.h"
  18. #include "llvm/CodeGen/MachineInstrBuilder.h"
  19. #include "llvm/CodeGen/MachineRegisterInfo.h"
  20. #include "llvm/CodeGen/TargetFrameLowering.h"
  21. #include "llvm/CodeGen/TargetInstrInfo.h"
  22. #include "llvm/CodeGen/TargetLowering.h"
  23. #include "llvm/CodeGen/TargetRegisterInfo.h"
  24. #include "llvm/CodeGen/TargetSubtargetInfo.h"
  25. #include "llvm/CodeGen/WinEHFuncInfo.h"
  26. #include "llvm/IR/DataLayout.h"
  27. #include "llvm/IR/DerivedTypes.h"
  28. #include "llvm/IR/Function.h"
  29. #include "llvm/IR/Instructions.h"
  30. #include "llvm/IR/IntrinsicInst.h"
  31. #include "llvm/IR/LLVMContext.h"
  32. #include "llvm/IR/Module.h"
  33. #include "llvm/Support/Debug.h"
  34. #include "llvm/Support/ErrorHandling.h"
  35. #include "llvm/Support/MathExtras.h"
  36. #include "llvm/Support/raw_ostream.h"
  37. #include "llvm/Target/TargetOptions.h"
  38. #include <algorithm>
  39. using namespace llvm;
  40. #define DEBUG_TYPE "function-lowering-info"
  41. /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
  42. /// PHI nodes or outside of the basic block that defines it, or used by a
  43. /// switch or atomic instruction, which may expand to multiple basic blocks.
  44. static bool isUsedOutsideOfDefiningBlock(const Instruction *I) {
  45. if (I->use_empty()) return false;
  46. if (isa<PHINode>(I)) return true;
  47. const BasicBlock *BB = I->getParent();
  48. for (const User *U : I->users())
  49. if (cast<Instruction>(U)->getParent() != BB || isa<PHINode>(U))
  50. return true;
  51. return false;
  52. }
  53. static ISD::NodeType getPreferredExtendForValue(const Value *V) {
  54. // For the users of the source value being used for compare instruction, if
  55. // the number of signed predicate is greater than unsigned predicate, we
  56. // prefer to use SIGN_EXTEND.
  57. //
  58. // With this optimization, we would be able to reduce some redundant sign or
  59. // zero extension instruction, and eventually more machine CSE opportunities
  60. // can be exposed.
  61. ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
  62. unsigned NumOfSigned = 0, NumOfUnsigned = 0;
  63. for (const User *U : V->users()) {
  64. if (const auto *CI = dyn_cast<CmpInst>(U)) {
  65. NumOfSigned += CI->isSigned();
  66. NumOfUnsigned += CI->isUnsigned();
  67. }
  68. }
  69. if (NumOfSigned > NumOfUnsigned)
  70. ExtendKind = ISD::SIGN_EXTEND;
  71. return ExtendKind;
  72. }
  73. void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
  74. SelectionDAG *DAG) {
  75. Fn = &fn;
  76. MF = &mf;
  77. TLI = MF->getSubtarget().getTargetLowering();
  78. RegInfo = &MF->getRegInfo();
  79. const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
  80. unsigned StackAlign = TFI->getStackAlignment();
  81. // Check whether the function can return without sret-demotion.
  82. SmallVector<ISD::OutputArg, 4> Outs;
  83. GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI,
  84. mf.getDataLayout());
  85. CanLowerReturn = TLI->CanLowerReturn(Fn->getCallingConv(), *MF,
  86. Fn->isVarArg(), Outs, Fn->getContext());
  87. // If this personality uses funclets, we need to do a bit more work.
  88. DenseMap<const AllocaInst *, TinyPtrVector<int *>> CatchObjects;
  89. EHPersonality Personality = classifyEHPersonality(
  90. Fn->hasPersonalityFn() ? Fn->getPersonalityFn() : nullptr);
  91. if (isFuncletEHPersonality(Personality)) {
  92. // Calculate state numbers if we haven't already.
  93. WinEHFuncInfo &EHInfo = *MF->getWinEHFuncInfo();
  94. if (Personality == EHPersonality::MSVC_CXX)
  95. calculateWinCXXEHStateNumbers(&fn, EHInfo);
  96. else if (isAsynchronousEHPersonality(Personality))
  97. calculateSEHStateNumbers(&fn, EHInfo);
  98. else if (Personality == EHPersonality::CoreCLR)
  99. calculateClrEHStateNumbers(&fn, EHInfo);
  100. // Map all BB references in the WinEH data to MBBs.
  101. for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) {
  102. for (WinEHHandlerType &H : TBME.HandlerArray) {
  103. if (const AllocaInst *AI = H.CatchObj.Alloca)
  104. CatchObjects.insert({AI, {}}).first->second.push_back(
  105. &H.CatchObj.FrameIndex);
  106. else
  107. H.CatchObj.FrameIndex = INT_MAX;
  108. }
  109. }
  110. }
  111. // Initialize the mapping of values to registers. This is only set up for
  112. // instruction values that are used outside of the block that defines
  113. // them.
  114. for (const BasicBlock &BB : *Fn) {
  115. for (const Instruction &I : BB) {
  116. if (const AllocaInst *AI = dyn_cast<AllocaInst>(&I)) {
  117. Type *Ty = AI->getAllocatedType();
  118. unsigned Align =
  119. std::max((unsigned)MF->getDataLayout().getPrefTypeAlignment(Ty),
  120. AI->getAlignment());
  121. // Static allocas can be folded into the initial stack frame
  122. // adjustment. For targets that don't realign the stack, don't
  123. // do this if there is an extra alignment requirement.
  124. if (AI->isStaticAlloca() &&
  125. (TFI->isStackRealignable() || (Align <= StackAlign))) {
  126. const ConstantInt *CUI = cast<ConstantInt>(AI->getArraySize());
  127. uint64_t TySize = MF->getDataLayout().getTypeAllocSize(Ty);
  128. TySize *= CUI->getZExtValue(); // Get total allocated size.
  129. if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
  130. int FrameIndex = INT_MAX;
  131. auto Iter = CatchObjects.find(AI);
  132. if (Iter != CatchObjects.end() && TLI->needsFixedCatchObjects()) {
  133. FrameIndex = MF->getFrameInfo().CreateFixedObject(
  134. TySize, 0, /*Immutable=*/false, /*isAliased=*/true);
  135. MF->getFrameInfo().setObjectAlignment(FrameIndex, Align);
  136. } else {
  137. FrameIndex =
  138. MF->getFrameInfo().CreateStackObject(TySize, Align, false, AI);
  139. }
  140. StaticAllocaMap[AI] = FrameIndex;
  141. // Update the catch handler information.
  142. if (Iter != CatchObjects.end()) {
  143. for (int *CatchObjPtr : Iter->second)
  144. *CatchObjPtr = FrameIndex;
  145. }
  146. } else {
  147. // FIXME: Overaligned static allocas should be grouped into
  148. // a single dynamic allocation instead of using a separate
  149. // stack allocation for each one.
  150. if (Align <= StackAlign)
  151. Align = 0;
  152. // Inform the Frame Information that we have variable-sized objects.
  153. MF->getFrameInfo().CreateVariableSizedObject(Align ? Align : 1, AI);
  154. }
  155. }
  156. // Look for inline asm that clobbers the SP register.
  157. if (isa<CallInst>(I) || isa<InvokeInst>(I)) {
  158. ImmutableCallSite CS(&I);
  159. if (isa<InlineAsm>(CS.getCalledValue())) {
  160. unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
  161. const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
  162. std::vector<TargetLowering::AsmOperandInfo> Ops =
  163. TLI->ParseConstraints(Fn->getParent()->getDataLayout(), TRI, CS);
  164. for (TargetLowering::AsmOperandInfo &Op : Ops) {
  165. if (Op.Type == InlineAsm::isClobber) {
  166. // Clobbers don't have SDValue operands, hence SDValue().
  167. TLI->ComputeConstraintToUse(Op, SDValue(), DAG);
  168. std::pair<unsigned, const TargetRegisterClass *> PhysReg =
  169. TLI->getRegForInlineAsmConstraint(TRI, Op.ConstraintCode,
  170. Op.ConstraintVT);
  171. if (PhysReg.first == SP)
  172. MF->getFrameInfo().setHasOpaqueSPAdjustment(true);
  173. }
  174. }
  175. }
  176. }
  177. // Look for calls to the @llvm.va_start intrinsic. We can omit some
  178. // prologue boilerplate for variadic functions that don't examine their
  179. // arguments.
  180. if (const auto *II = dyn_cast<IntrinsicInst>(&I)) {
  181. if (II->getIntrinsicID() == Intrinsic::vastart)
  182. MF->getFrameInfo().setHasVAStart(true);
  183. }
  184. // If we have a musttail call in a variadic function, we need to ensure we
  185. // forward implicit register parameters.
  186. if (const auto *CI = dyn_cast<CallInst>(&I)) {
  187. if (CI->isMustTailCall() && Fn->isVarArg())
  188. MF->getFrameInfo().setHasMustTailInVarArgFunc(true);
  189. }
  190. // Mark values used outside their block as exported, by allocating
  191. // a virtual register for them.
  192. if (isUsedOutsideOfDefiningBlock(&I))
  193. if (!isa<AllocaInst>(I) || !StaticAllocaMap.count(cast<AllocaInst>(&I)))
  194. InitializeRegForValue(&I);
  195. // Decide the preferred extend type for a value.
  196. PreferredExtendType[&I] = getPreferredExtendForValue(&I);
  197. }
  198. }
  199. // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
  200. // also creates the initial PHI MachineInstrs, though none of the input
  201. // operands are populated.
  202. for (const BasicBlock &BB : *Fn) {
  203. // Don't create MachineBasicBlocks for imaginary EH pad blocks. These blocks
  204. // are really data, and no instructions can live here.
  205. if (BB.isEHPad()) {
  206. const Instruction *PadInst = BB.getFirstNonPHI();
  207. // If this is a non-landingpad EH pad, mark this function as using
  208. // funclets.
  209. // FIXME: SEH catchpads do not create funclets, so we could avoid setting
  210. // this in such cases in order to improve frame layout.
  211. if (!isa<LandingPadInst>(PadInst)) {
  212. MF->setHasEHFunclets(true);
  213. MF->getFrameInfo().setHasOpaqueSPAdjustment(true);
  214. }
  215. if (isa<CatchSwitchInst>(PadInst)) {
  216. assert(&*BB.begin() == PadInst &&
  217. "WinEHPrepare failed to remove PHIs from imaginary BBs");
  218. continue;
  219. }
  220. if (isa<FuncletPadInst>(PadInst))
  221. assert(&*BB.begin() == PadInst && "WinEHPrepare failed to demote PHIs");
  222. }
  223. MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(&BB);
  224. MBBMap[&BB] = MBB;
  225. MF->push_back(MBB);
  226. // Transfer the address-taken flag. This is necessary because there could
  227. // be multiple MachineBasicBlocks corresponding to one BasicBlock, and only
  228. // the first one should be marked.
  229. if (BB.hasAddressTaken())
  230. MBB->setHasAddressTaken();
  231. // Mark landing pad blocks.
  232. if (BB.isEHPad())
  233. MBB->setIsEHPad();
  234. // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
  235. // appropriate.
  236. for (const PHINode &PN : BB.phis()) {
  237. if (PN.use_empty())
  238. continue;
  239. // Skip empty types
  240. if (PN.getType()->isEmptyTy())
  241. continue;
  242. DebugLoc DL = PN.getDebugLoc();
  243. unsigned PHIReg = ValueMap[&PN];
  244. assert(PHIReg && "PHI node does not have an assigned virtual register!");
  245. SmallVector<EVT, 4> ValueVTs;
  246. ComputeValueVTs(*TLI, MF->getDataLayout(), PN.getType(), ValueVTs);
  247. for (EVT VT : ValueVTs) {
  248. unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);
  249. const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
  250. for (unsigned i = 0; i != NumRegisters; ++i)
  251. BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);
  252. PHIReg += NumRegisters;
  253. }
  254. }
  255. }
  256. if (!isFuncletEHPersonality(Personality))
  257. return;
  258. WinEHFuncInfo &EHInfo = *MF->getWinEHFuncInfo();
  259. // Map all BB references in the WinEH data to MBBs.
  260. for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) {
  261. for (WinEHHandlerType &H : TBME.HandlerArray) {
  262. if (H.Handler)
  263. H.Handler = MBBMap[H.Handler.get<const BasicBlock *>()];
  264. }
  265. }
  266. for (CxxUnwindMapEntry &UME : EHInfo.CxxUnwindMap)
  267. if (UME.Cleanup)
  268. UME.Cleanup = MBBMap[UME.Cleanup.get<const BasicBlock *>()];
  269. for (SEHUnwindMapEntry &UME : EHInfo.SEHUnwindMap) {
  270. const BasicBlock *BB = UME.Handler.get<const BasicBlock *>();
  271. UME.Handler = MBBMap[BB];
  272. }
  273. for (ClrEHUnwindMapEntry &CME : EHInfo.ClrEHUnwindMap) {
  274. const BasicBlock *BB = CME.Handler.get<const BasicBlock *>();
  275. CME.Handler = MBBMap[BB];
  276. }
  277. }
  278. /// clear - Clear out all the function-specific state. This returns this
  279. /// FunctionLoweringInfo to an empty state, ready to be used for a
  280. /// different function.
  281. void FunctionLoweringInfo::clear() {
  282. MBBMap.clear();
  283. ValueMap.clear();
  284. StaticAllocaMap.clear();
  285. LiveOutRegInfo.clear();
  286. VisitedBBs.clear();
  287. ArgDbgValues.clear();
  288. ByValArgFrameIndexMap.clear();
  289. RegFixups.clear();
  290. StatepointStackSlots.clear();
  291. StatepointSpillMaps.clear();
  292. PreferredExtendType.clear();
  293. }
  294. /// CreateReg - Allocate a single virtual register for the given type.
  295. unsigned FunctionLoweringInfo::CreateReg(MVT VT) {
  296. return RegInfo->createVirtualRegister(
  297. MF->getSubtarget().getTargetLowering()->getRegClassFor(VT));
  298. }
  299. /// CreateRegs - Allocate the appropriate number of virtual registers of
  300. /// the correctly promoted or expanded types. Assign these registers
  301. /// consecutive vreg numbers and return the first assigned number.
  302. ///
  303. /// In the case that the given value has struct or array type, this function
  304. /// will assign registers for each member or element.
  305. ///
  306. unsigned FunctionLoweringInfo::CreateRegs(Type *Ty) {
  307. const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
  308. SmallVector<EVT, 4> ValueVTs;
  309. ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs);
  310. unsigned FirstReg = 0;
  311. for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
  312. EVT ValueVT = ValueVTs[Value];
  313. MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT);
  314. unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT);
  315. for (unsigned i = 0; i != NumRegs; ++i) {
  316. unsigned R = CreateReg(RegisterVT);
  317. if (!FirstReg) FirstReg = R;
  318. }
  319. }
  320. return FirstReg;
  321. }
  322. /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
  323. /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
  324. /// the register's LiveOutInfo is for a smaller bit width, it is extended to
  325. /// the larger bit width by zero extension. The bit width must be no smaller
  326. /// than the LiveOutInfo's existing bit width.
  327. const FunctionLoweringInfo::LiveOutInfo *
  328. FunctionLoweringInfo::GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth) {
  329. if (!LiveOutRegInfo.inBounds(Reg))
  330. return nullptr;
  331. LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
  332. if (!LOI->IsValid)
  333. return nullptr;
  334. if (BitWidth > LOI->Known.getBitWidth()) {
  335. LOI->NumSignBits = 1;
  336. LOI->Known = LOI->Known.zextOrTrunc(BitWidth);
  337. }
  338. return LOI;
  339. }
  340. /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
  341. /// register based on the LiveOutInfo of its operands.
  342. void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
  343. Type *Ty = PN->getType();
  344. if (!Ty->isIntegerTy() || Ty->isVectorTy())
  345. return;
  346. SmallVector<EVT, 1> ValueVTs;
  347. ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs);
  348. assert(ValueVTs.size() == 1 &&
  349. "PHIs with non-vector integer types should have a single VT.");
  350. EVT IntVT = ValueVTs[0];
  351. if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1)
  352. return;
  353. IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT);
  354. unsigned BitWidth = IntVT.getSizeInBits();
  355. unsigned DestReg = ValueMap[PN];
  356. if (!TargetRegisterInfo::isVirtualRegister(DestReg))
  357. return;
  358. LiveOutRegInfo.grow(DestReg);
  359. LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];
  360. Value *V = PN->getIncomingValue(0);
  361. if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
  362. DestLOI.NumSignBits = 1;
  363. DestLOI.Known = KnownBits(BitWidth);
  364. return;
  365. }
  366. if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
  367. APInt Val = CI->getValue().zextOrTrunc(BitWidth);
  368. DestLOI.NumSignBits = Val.getNumSignBits();
  369. DestLOI.Known.Zero = ~Val;
  370. DestLOI.Known.One = Val;
  371. } else {
  372. assert(ValueMap.count(V) && "V should have been placed in ValueMap when its"
  373. "CopyToReg node was created.");
  374. unsigned SrcReg = ValueMap[V];
  375. if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
  376. DestLOI.IsValid = false;
  377. return;
  378. }
  379. const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
  380. if (!SrcLOI) {
  381. DestLOI.IsValid = false;
  382. return;
  383. }
  384. DestLOI = *SrcLOI;
  385. }
  386. assert(DestLOI.Known.Zero.getBitWidth() == BitWidth &&
  387. DestLOI.Known.One.getBitWidth() == BitWidth &&
  388. "Masks should have the same bit width as the type.");
  389. for (unsigned i = 1, e = PN->getNumIncomingValues(); i != e; ++i) {
  390. Value *V = PN->getIncomingValue(i);
  391. if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
  392. DestLOI.NumSignBits = 1;
  393. DestLOI.Known = KnownBits(BitWidth);
  394. return;
  395. }
  396. if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
  397. APInt Val = CI->getValue().zextOrTrunc(BitWidth);
  398. DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, Val.getNumSignBits());
  399. DestLOI.Known.Zero &= ~Val;
  400. DestLOI.Known.One &= Val;
  401. continue;
  402. }
  403. assert(ValueMap.count(V) && "V should have been placed in ValueMap when "
  404. "its CopyToReg node was created.");
  405. unsigned SrcReg = ValueMap[V];
  406. if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
  407. DestLOI.IsValid = false;
  408. return;
  409. }
  410. const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
  411. if (!SrcLOI) {
  412. DestLOI.IsValid = false;
  413. return;
  414. }
  415. DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, SrcLOI->NumSignBits);
  416. DestLOI.Known.Zero &= SrcLOI->Known.Zero;
  417. DestLOI.Known.One &= SrcLOI->Known.One;
  418. }
  419. }
  420. /// setArgumentFrameIndex - Record frame index for the byval
  421. /// argument. This overrides previous frame index entry for this argument,
  422. /// if any.
  423. void FunctionLoweringInfo::setArgumentFrameIndex(const Argument *A,
  424. int FI) {
  425. ByValArgFrameIndexMap[A] = FI;
  426. }
  427. /// getArgumentFrameIndex - Get frame index for the byval argument.
  428. /// If the argument does not have any assigned frame index then 0 is
  429. /// returned.
  430. int FunctionLoweringInfo::getArgumentFrameIndex(const Argument *A) {
  431. auto I = ByValArgFrameIndexMap.find(A);
  432. if (I != ByValArgFrameIndexMap.end())
  433. return I->second;
  434. DEBUG(dbgs() << "Argument does not have assigned frame index!\n");
  435. return INT_MAX;
  436. }
  437. unsigned FunctionLoweringInfo::getCatchPadExceptionPointerVReg(
  438. const Value *CPI, const TargetRegisterClass *RC) {
  439. MachineRegisterInfo &MRI = MF->getRegInfo();
  440. auto I = CatchPadExceptionPointers.insert({CPI, 0});
  441. unsigned &VReg = I.first->second;
  442. if (I.second)
  443. VReg = MRI.createVirtualRegister(RC);
  444. assert(VReg && "null vreg in exception pointer table!");
  445. return VReg;
  446. }
  447. unsigned
  448. FunctionLoweringInfo::getOrCreateSwiftErrorVReg(const MachineBasicBlock *MBB,
  449. const Value *Val) {
  450. auto Key = std::make_pair(MBB, Val);
  451. auto It = SwiftErrorVRegDefMap.find(Key);
  452. // If this is the first use of this swifterror value in this basic block,
  453. // create a new virtual register.
  454. // After we processed all basic blocks we will satisfy this "upwards exposed
  455. // use" by inserting a copy or phi at the beginning of this block.
  456. if (It == SwiftErrorVRegDefMap.end()) {
  457. auto &DL = MF->getDataLayout();
  458. const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL));
  459. auto VReg = MF->getRegInfo().createVirtualRegister(RC);
  460. SwiftErrorVRegDefMap[Key] = VReg;
  461. SwiftErrorVRegUpwardsUse[Key] = VReg;
  462. return VReg;
  463. } else return It->second;
  464. }
  465. void FunctionLoweringInfo::setCurrentSwiftErrorVReg(
  466. const MachineBasicBlock *MBB, const Value *Val, unsigned VReg) {
  467. SwiftErrorVRegDefMap[std::make_pair(MBB, Val)] = VReg;
  468. }
  469. std::pair<unsigned, bool>
  470. FunctionLoweringInfo::getOrCreateSwiftErrorVRegDefAt(const Instruction *I) {
  471. auto Key = PointerIntPair<const Instruction *, 1, bool>(I, true);
  472. auto It = SwiftErrorVRegDefUses.find(Key);
  473. if (It == SwiftErrorVRegDefUses.end()) {
  474. auto &DL = MF->getDataLayout();
  475. const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL));
  476. unsigned VReg = MF->getRegInfo().createVirtualRegister(RC);
  477. SwiftErrorVRegDefUses[Key] = VReg;
  478. return std::make_pair(VReg, true);
  479. }
  480. return std::make_pair(It->second, false);
  481. }
  482. std::pair<unsigned, bool>
  483. FunctionLoweringInfo::getOrCreateSwiftErrorVRegUseAt(const Instruction *I, const MachineBasicBlock *MBB, const Value *Val) {
  484. auto Key = PointerIntPair<const Instruction *, 1, bool>(I, false);
  485. auto It = SwiftErrorVRegDefUses.find(Key);
  486. if (It == SwiftErrorVRegDefUses.end()) {
  487. unsigned VReg = getOrCreateSwiftErrorVReg(MBB, Val);
  488. SwiftErrorVRegDefUses[Key] = VReg;
  489. return std::make_pair(VReg, true);
  490. }
  491. return std::make_pair(It->second, false);
  492. }