MachineVerifier.cpp 85 KB

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  1. //===- MachineVerifier.cpp - Machine Code Verifier ------------------------===//
  2. //
  3. // The LLVM Compiler Infrastructure
  4. //
  5. // This file is distributed under the University of Illinois Open Source
  6. // License. See LICENSE.TXT for details.
  7. //
  8. //===----------------------------------------------------------------------===//
  9. //
  10. // Pass to verify generated machine code. The following is checked:
  11. //
  12. // Operand counts: All explicit operands must be present.
  13. //
  14. // Register classes: All physical and virtual register operands must be
  15. // compatible with the register class required by the instruction descriptor.
  16. //
  17. // Register live intervals: Registers must be defined only once, and must be
  18. // defined before use.
  19. //
  20. // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
  21. // command-line option -verify-machineinstrs, or by defining the environment
  22. // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
  23. // the verifier errors.
  24. //===----------------------------------------------------------------------===//
  25. #include "llvm/ADT/BitVector.h"
  26. #include "llvm/ADT/DenseMap.h"
  27. #include "llvm/ADT/DenseSet.h"
  28. #include "llvm/ADT/DepthFirstIterator.h"
  29. #include "llvm/ADT/STLExtras.h"
  30. #include "llvm/ADT/SetOperations.h"
  31. #include "llvm/ADT/SmallPtrSet.h"
  32. #include "llvm/ADT/SmallVector.h"
  33. #include "llvm/ADT/StringRef.h"
  34. #include "llvm/ADT/Twine.h"
  35. #include "llvm/Analysis/EHPersonalities.h"
  36. #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
  37. #include "llvm/CodeGen/LiveInterval.h"
  38. #include "llvm/CodeGen/LiveIntervals.h"
  39. #include "llvm/CodeGen/LiveStacks.h"
  40. #include "llvm/CodeGen/LiveVariables.h"
  41. #include "llvm/CodeGen/MachineBasicBlock.h"
  42. #include "llvm/CodeGen/MachineFrameInfo.h"
  43. #include "llvm/CodeGen/MachineFunction.h"
  44. #include "llvm/CodeGen/MachineFunctionPass.h"
  45. #include "llvm/CodeGen/MachineInstr.h"
  46. #include "llvm/CodeGen/MachineInstrBundle.h"
  47. #include "llvm/CodeGen/MachineMemOperand.h"
  48. #include "llvm/CodeGen/MachineOperand.h"
  49. #include "llvm/CodeGen/MachineRegisterInfo.h"
  50. #include "llvm/CodeGen/PseudoSourceValue.h"
  51. #include "llvm/CodeGen/SlotIndexes.h"
  52. #include "llvm/CodeGen/StackMaps.h"
  53. #include "llvm/CodeGen/TargetInstrInfo.h"
  54. #include "llvm/CodeGen/TargetOpcodes.h"
  55. #include "llvm/CodeGen/TargetRegisterInfo.h"
  56. #include "llvm/CodeGen/TargetSubtargetInfo.h"
  57. #include "llvm/IR/BasicBlock.h"
  58. #include "llvm/IR/Function.h"
  59. #include "llvm/IR/InlineAsm.h"
  60. #include "llvm/IR/Instructions.h"
  61. #include "llvm/MC/LaneBitmask.h"
  62. #include "llvm/MC/MCAsmInfo.h"
  63. #include "llvm/MC/MCInstrDesc.h"
  64. #include "llvm/MC/MCRegisterInfo.h"
  65. #include "llvm/MC/MCTargetOptions.h"
  66. #include "llvm/Pass.h"
  67. #include "llvm/Support/Casting.h"
  68. #include "llvm/Support/ErrorHandling.h"
  69. #include "llvm/Support/LowLevelTypeImpl.h"
  70. #include "llvm/Support/MathExtras.h"
  71. #include "llvm/Support/raw_ostream.h"
  72. #include "llvm/Target/TargetMachine.h"
  73. #include <algorithm>
  74. #include <cassert>
  75. #include <cstddef>
  76. #include <cstdint>
  77. #include <iterator>
  78. #include <string>
  79. #include <utility>
  80. using namespace llvm;
  81. namespace {
  82. struct MachineVerifier {
  83. MachineVerifier(Pass *pass, const char *b) : PASS(pass), Banner(b) {}
  84. unsigned verify(MachineFunction &MF);
  85. Pass *const PASS;
  86. const char *Banner;
  87. const MachineFunction *MF;
  88. const TargetMachine *TM;
  89. const TargetInstrInfo *TII;
  90. const TargetRegisterInfo *TRI;
  91. const MachineRegisterInfo *MRI;
  92. unsigned foundErrors;
  93. // Avoid querying the MachineFunctionProperties for each operand.
  94. bool isFunctionRegBankSelected;
  95. bool isFunctionSelected;
  96. using RegVector = SmallVector<unsigned, 16>;
  97. using RegMaskVector = SmallVector<const uint32_t *, 4>;
  98. using RegSet = DenseSet<unsigned>;
  99. using RegMap = DenseMap<unsigned, const MachineInstr *>;
  100. using BlockSet = SmallPtrSet<const MachineBasicBlock *, 8>;
  101. const MachineInstr *FirstTerminator;
  102. BlockSet FunctionBlocks;
  103. BitVector regsReserved;
  104. RegSet regsLive;
  105. RegVector regsDefined, regsDead, regsKilled;
  106. RegMaskVector regMasks;
  107. SlotIndex lastIndex;
  108. // Add Reg and any sub-registers to RV
  109. void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
  110. RV.push_back(Reg);
  111. if (TargetRegisterInfo::isPhysicalRegister(Reg))
  112. for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
  113. RV.push_back(*SubRegs);
  114. }
  115. struct BBInfo {
  116. // Is this MBB reachable from the MF entry point?
  117. bool reachable = false;
  118. // Vregs that must be live in because they are used without being
  119. // defined. Map value is the user.
  120. RegMap vregsLiveIn;
  121. // Regs killed in MBB. They may be defined again, and will then be in both
  122. // regsKilled and regsLiveOut.
  123. RegSet regsKilled;
  124. // Regs defined in MBB and live out. Note that vregs passing through may
  125. // be live out without being mentioned here.
  126. RegSet regsLiveOut;
  127. // Vregs that pass through MBB untouched. This set is disjoint from
  128. // regsKilled and regsLiveOut.
  129. RegSet vregsPassed;
  130. // Vregs that must pass through MBB because they are needed by a successor
  131. // block. This set is disjoint from regsLiveOut.
  132. RegSet vregsRequired;
  133. // Set versions of block's predecessor and successor lists.
  134. BlockSet Preds, Succs;
  135. BBInfo() = default;
  136. // Add register to vregsPassed if it belongs there. Return true if
  137. // anything changed.
  138. bool addPassed(unsigned Reg) {
  139. if (!TargetRegisterInfo::isVirtualRegister(Reg))
  140. return false;
  141. if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
  142. return false;
  143. return vregsPassed.insert(Reg).second;
  144. }
  145. // Same for a full set.
  146. bool addPassed(const RegSet &RS) {
  147. bool changed = false;
  148. for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
  149. if (addPassed(*I))
  150. changed = true;
  151. return changed;
  152. }
  153. // Add register to vregsRequired if it belongs there. Return true if
  154. // anything changed.
  155. bool addRequired(unsigned Reg) {
  156. if (!TargetRegisterInfo::isVirtualRegister(Reg))
  157. return false;
  158. if (regsLiveOut.count(Reg))
  159. return false;
  160. return vregsRequired.insert(Reg).second;
  161. }
  162. // Same for a full set.
  163. bool addRequired(const RegSet &RS) {
  164. bool changed = false;
  165. for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
  166. if (addRequired(*I))
  167. changed = true;
  168. return changed;
  169. }
  170. // Same for a full map.
  171. bool addRequired(const RegMap &RM) {
  172. bool changed = false;
  173. for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
  174. if (addRequired(I->first))
  175. changed = true;
  176. return changed;
  177. }
  178. // Live-out registers are either in regsLiveOut or vregsPassed.
  179. bool isLiveOut(unsigned Reg) const {
  180. return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
  181. }
  182. };
  183. // Extra register info per MBB.
  184. DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
  185. bool isReserved(unsigned Reg) {
  186. return Reg < regsReserved.size() && regsReserved.test(Reg);
  187. }
  188. bool isAllocatable(unsigned Reg) const {
  189. return Reg < TRI->getNumRegs() && TRI->isInAllocatableClass(Reg) &&
  190. !regsReserved.test(Reg);
  191. }
  192. // Analysis information if available
  193. LiveVariables *LiveVars;
  194. LiveIntervals *LiveInts;
  195. LiveStacks *LiveStks;
  196. SlotIndexes *Indexes;
  197. void visitMachineFunctionBefore();
  198. void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
  199. void visitMachineBundleBefore(const MachineInstr *MI);
  200. void visitMachineInstrBefore(const MachineInstr *MI);
  201. void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
  202. void visitMachineInstrAfter(const MachineInstr *MI);
  203. void visitMachineBundleAfter(const MachineInstr *MI);
  204. void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
  205. void visitMachineFunctionAfter();
  206. void report(const char *msg, const MachineFunction *MF);
  207. void report(const char *msg, const MachineBasicBlock *MBB);
  208. void report(const char *msg, const MachineInstr *MI);
  209. void report(const char *msg, const MachineOperand *MO, unsigned MONum,
  210. LLT MOVRegType = LLT{});
  211. void report_context(const LiveInterval &LI) const;
  212. void report_context(const LiveRange &LR, unsigned VRegUnit,
  213. LaneBitmask LaneMask) const;
  214. void report_context(const LiveRange::Segment &S) const;
  215. void report_context(const VNInfo &VNI) const;
  216. void report_context(SlotIndex Pos) const;
  217. void report_context_liverange(const LiveRange &LR) const;
  218. void report_context_lanemask(LaneBitmask LaneMask) const;
  219. void report_context_vreg(unsigned VReg) const;
  220. void report_context_vreg_regunit(unsigned VRegOrRegUnit) const;
  221. void verifyInlineAsm(const MachineInstr *MI);
  222. void checkLiveness(const MachineOperand *MO, unsigned MONum);
  223. void checkLivenessAtUse(const MachineOperand *MO, unsigned MONum,
  224. SlotIndex UseIdx, const LiveRange &LR, unsigned Reg,
  225. LaneBitmask LaneMask = LaneBitmask::getNone());
  226. void checkLivenessAtDef(const MachineOperand *MO, unsigned MONum,
  227. SlotIndex DefIdx, const LiveRange &LR, unsigned Reg,
  228. LaneBitmask LaneMask = LaneBitmask::getNone());
  229. void markReachable(const MachineBasicBlock *MBB);
  230. void calcRegsPassed();
  231. void checkPHIOps(const MachineBasicBlock &MBB);
  232. void calcRegsRequired();
  233. void verifyLiveVariables();
  234. void verifyLiveIntervals();
  235. void verifyLiveInterval(const LiveInterval&);
  236. void verifyLiveRangeValue(const LiveRange&, const VNInfo*, unsigned,
  237. LaneBitmask);
  238. void verifyLiveRangeSegment(const LiveRange&,
  239. const LiveRange::const_iterator I, unsigned,
  240. LaneBitmask);
  241. void verifyLiveRange(const LiveRange&, unsigned,
  242. LaneBitmask LaneMask = LaneBitmask::getNone());
  243. void verifyStackFrame();
  244. void verifySlotIndexes() const;
  245. void verifyProperties(const MachineFunction &MF);
  246. };
  247. struct MachineVerifierPass : public MachineFunctionPass {
  248. static char ID; // Pass ID, replacement for typeid
  249. const std::string Banner;
  250. MachineVerifierPass(std::string banner = std::string())
  251. : MachineFunctionPass(ID), Banner(std::move(banner)) {
  252. initializeMachineVerifierPassPass(*PassRegistry::getPassRegistry());
  253. }
  254. void getAnalysisUsage(AnalysisUsage &AU) const override {
  255. AU.setPreservesAll();
  256. MachineFunctionPass::getAnalysisUsage(AU);
  257. }
  258. bool runOnMachineFunction(MachineFunction &MF) override {
  259. unsigned FoundErrors = MachineVerifier(this, Banner.c_str()).verify(MF);
  260. if (FoundErrors)
  261. report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
  262. return false;
  263. }
  264. };
  265. } // end anonymous namespace
  266. char MachineVerifierPass::ID = 0;
  267. INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
  268. "Verify generated machine code", false, false)
  269. FunctionPass *llvm::createMachineVerifierPass(const std::string &Banner) {
  270. return new MachineVerifierPass(Banner);
  271. }
  272. bool MachineFunction::verify(Pass *p, const char *Banner, bool AbortOnErrors)
  273. const {
  274. MachineFunction &MF = const_cast<MachineFunction&>(*this);
  275. unsigned FoundErrors = MachineVerifier(p, Banner).verify(MF);
  276. if (AbortOnErrors && FoundErrors)
  277. report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
  278. return FoundErrors == 0;
  279. }
  280. void MachineVerifier::verifySlotIndexes() const {
  281. if (Indexes == nullptr)
  282. return;
  283. // Ensure the IdxMBB list is sorted by slot indexes.
  284. SlotIndex Last;
  285. for (SlotIndexes::MBBIndexIterator I = Indexes->MBBIndexBegin(),
  286. E = Indexes->MBBIndexEnd(); I != E; ++I) {
  287. assert(!Last.isValid() || I->first > Last);
  288. Last = I->first;
  289. }
  290. }
  291. void MachineVerifier::verifyProperties(const MachineFunction &MF) {
  292. // If a pass has introduced virtual registers without clearing the
  293. // NoVRegs property (or set it without allocating the vregs)
  294. // then report an error.
  295. if (MF.getProperties().hasProperty(
  296. MachineFunctionProperties::Property::NoVRegs) &&
  297. MRI->getNumVirtRegs())
  298. report("Function has NoVRegs property but there are VReg operands", &MF);
  299. }
  300. unsigned MachineVerifier::verify(MachineFunction &MF) {
  301. foundErrors = 0;
  302. this->MF = &MF;
  303. TM = &MF.getTarget();
  304. TII = MF.getSubtarget().getInstrInfo();
  305. TRI = MF.getSubtarget().getRegisterInfo();
  306. MRI = &MF.getRegInfo();
  307. const bool isFunctionFailedISel = MF.getProperties().hasProperty(
  308. MachineFunctionProperties::Property::FailedISel);
  309. isFunctionRegBankSelected =
  310. !isFunctionFailedISel &&
  311. MF.getProperties().hasProperty(
  312. MachineFunctionProperties::Property::RegBankSelected);
  313. isFunctionSelected = !isFunctionFailedISel &&
  314. MF.getProperties().hasProperty(
  315. MachineFunctionProperties::Property::Selected);
  316. LiveVars = nullptr;
  317. LiveInts = nullptr;
  318. LiveStks = nullptr;
  319. Indexes = nullptr;
  320. if (PASS) {
  321. LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
  322. // We don't want to verify LiveVariables if LiveIntervals is available.
  323. if (!LiveInts)
  324. LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
  325. LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
  326. Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
  327. }
  328. verifySlotIndexes();
  329. verifyProperties(MF);
  330. visitMachineFunctionBefore();
  331. for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
  332. MFI!=MFE; ++MFI) {
  333. visitMachineBasicBlockBefore(&*MFI);
  334. // Keep track of the current bundle header.
  335. const MachineInstr *CurBundle = nullptr;
  336. // Do we expect the next instruction to be part of the same bundle?
  337. bool InBundle = false;
  338. for (MachineBasicBlock::const_instr_iterator MBBI = MFI->instr_begin(),
  339. MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI) {
  340. if (MBBI->getParent() != &*MFI) {
  341. report("Bad instruction parent pointer", &*MFI);
  342. errs() << "Instruction: " << *MBBI;
  343. continue;
  344. }
  345. // Check for consistent bundle flags.
  346. if (InBundle && !MBBI->isBundledWithPred())
  347. report("Missing BundledPred flag, "
  348. "BundledSucc was set on predecessor",
  349. &*MBBI);
  350. if (!InBundle && MBBI->isBundledWithPred())
  351. report("BundledPred flag is set, "
  352. "but BundledSucc not set on predecessor",
  353. &*MBBI);
  354. // Is this a bundle header?
  355. if (!MBBI->isInsideBundle()) {
  356. if (CurBundle)
  357. visitMachineBundleAfter(CurBundle);
  358. CurBundle = &*MBBI;
  359. visitMachineBundleBefore(CurBundle);
  360. } else if (!CurBundle)
  361. report("No bundle header", &*MBBI);
  362. visitMachineInstrBefore(&*MBBI);
  363. for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
  364. const MachineInstr &MI = *MBBI;
  365. const MachineOperand &Op = MI.getOperand(I);
  366. if (Op.getParent() != &MI) {
  367. // Make sure to use correct addOperand / RemoveOperand / ChangeTo
  368. // functions when replacing operands of a MachineInstr.
  369. report("Instruction has operand with wrong parent set", &MI);
  370. }
  371. visitMachineOperand(&Op, I);
  372. }
  373. visitMachineInstrAfter(&*MBBI);
  374. // Was this the last bundled instruction?
  375. InBundle = MBBI->isBundledWithSucc();
  376. }
  377. if (CurBundle)
  378. visitMachineBundleAfter(CurBundle);
  379. if (InBundle)
  380. report("BundledSucc flag set on last instruction in block", &MFI->back());
  381. visitMachineBasicBlockAfter(&*MFI);
  382. }
  383. visitMachineFunctionAfter();
  384. // Clean up.
  385. regsLive.clear();
  386. regsDefined.clear();
  387. regsDead.clear();
  388. regsKilled.clear();
  389. regMasks.clear();
  390. MBBInfoMap.clear();
  391. return foundErrors;
  392. }
  393. void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
  394. assert(MF);
  395. errs() << '\n';
  396. if (!foundErrors++) {
  397. if (Banner)
  398. errs() << "# " << Banner << '\n';
  399. if (LiveInts != nullptr)
  400. LiveInts->print(errs());
  401. else
  402. MF->print(errs(), Indexes);
  403. }
  404. errs() << "*** Bad machine code: " << msg << " ***\n"
  405. << "- function: " << MF->getName() << "\n";
  406. }
  407. void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
  408. assert(MBB);
  409. report(msg, MBB->getParent());
  410. errs() << "- basic block: " << printMBBReference(*MBB) << ' '
  411. << MBB->getName() << " (" << (const void *)MBB << ')';
  412. if (Indexes)
  413. errs() << " [" << Indexes->getMBBStartIdx(MBB)
  414. << ';' << Indexes->getMBBEndIdx(MBB) << ')';
  415. errs() << '\n';
  416. }
  417. void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
  418. assert(MI);
  419. report(msg, MI->getParent());
  420. errs() << "- instruction: ";
  421. if (Indexes && Indexes->hasIndex(*MI))
  422. errs() << Indexes->getInstructionIndex(*MI) << '\t';
  423. MI->print(errs(), /*SkipOpers=*/true);
  424. }
  425. void MachineVerifier::report(const char *msg, const MachineOperand *MO,
  426. unsigned MONum, LLT MOVRegType) {
  427. assert(MO);
  428. report(msg, MO->getParent());
  429. errs() << "- operand " << MONum << ": ";
  430. MO->print(errs(), MOVRegType, TRI);
  431. errs() << "\n";
  432. }
  433. void MachineVerifier::report_context(SlotIndex Pos) const {
  434. errs() << "- at: " << Pos << '\n';
  435. }
  436. void MachineVerifier::report_context(const LiveInterval &LI) const {
  437. errs() << "- interval: " << LI << '\n';
  438. }
  439. void MachineVerifier::report_context(const LiveRange &LR, unsigned VRegUnit,
  440. LaneBitmask LaneMask) const {
  441. report_context_liverange(LR);
  442. report_context_vreg_regunit(VRegUnit);
  443. if (LaneMask.any())
  444. report_context_lanemask(LaneMask);
  445. }
  446. void MachineVerifier::report_context(const LiveRange::Segment &S) const {
  447. errs() << "- segment: " << S << '\n';
  448. }
  449. void MachineVerifier::report_context(const VNInfo &VNI) const {
  450. errs() << "- ValNo: " << VNI.id << " (def " << VNI.def << ")\n";
  451. }
  452. void MachineVerifier::report_context_liverange(const LiveRange &LR) const {
  453. errs() << "- liverange: " << LR << '\n';
  454. }
  455. void MachineVerifier::report_context_vreg(unsigned VReg) const {
  456. errs() << "- v. register: " << printReg(VReg, TRI) << '\n';
  457. }
  458. void MachineVerifier::report_context_vreg_regunit(unsigned VRegOrUnit) const {
  459. if (TargetRegisterInfo::isVirtualRegister(VRegOrUnit)) {
  460. report_context_vreg(VRegOrUnit);
  461. } else {
  462. errs() << "- regunit: " << printRegUnit(VRegOrUnit, TRI) << '\n';
  463. }
  464. }
  465. void MachineVerifier::report_context_lanemask(LaneBitmask LaneMask) const {
  466. errs() << "- lanemask: " << PrintLaneMask(LaneMask) << '\n';
  467. }
  468. void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
  469. BBInfo &MInfo = MBBInfoMap[MBB];
  470. if (!MInfo.reachable) {
  471. MInfo.reachable = true;
  472. for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
  473. SuE = MBB->succ_end(); SuI != SuE; ++SuI)
  474. markReachable(*SuI);
  475. }
  476. }
  477. void MachineVerifier::visitMachineFunctionBefore() {
  478. lastIndex = SlotIndex();
  479. regsReserved = MRI->reservedRegsFrozen() ? MRI->getReservedRegs()
  480. : TRI->getReservedRegs(*MF);
  481. if (!MF->empty())
  482. markReachable(&MF->front());
  483. // Build a set of the basic blocks in the function.
  484. FunctionBlocks.clear();
  485. for (const auto &MBB : *MF) {
  486. FunctionBlocks.insert(&MBB);
  487. BBInfo &MInfo = MBBInfoMap[&MBB];
  488. MInfo.Preds.insert(MBB.pred_begin(), MBB.pred_end());
  489. if (MInfo.Preds.size() != MBB.pred_size())
  490. report("MBB has duplicate entries in its predecessor list.", &MBB);
  491. MInfo.Succs.insert(MBB.succ_begin(), MBB.succ_end());
  492. if (MInfo.Succs.size() != MBB.succ_size())
  493. report("MBB has duplicate entries in its successor list.", &MBB);
  494. }
  495. // Check that the register use lists are sane.
  496. MRI->verifyUseLists();
  497. if (!MF->empty())
  498. verifyStackFrame();
  499. }
  500. // Does iterator point to a and b as the first two elements?
  501. static bool matchPair(MachineBasicBlock::const_succ_iterator i,
  502. const MachineBasicBlock *a, const MachineBasicBlock *b) {
  503. if (*i == a)
  504. return *++i == b;
  505. if (*i == b)
  506. return *++i == a;
  507. return false;
  508. }
  509. void
  510. MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
  511. FirstTerminator = nullptr;
  512. if (!MF->getProperties().hasProperty(
  513. MachineFunctionProperties::Property::NoPHIs) && MRI->tracksLiveness()) {
  514. // If this block has allocatable physical registers live-in, check that
  515. // it is an entry block or landing pad.
  516. for (const auto &LI : MBB->liveins()) {
  517. if (isAllocatable(LI.PhysReg) && !MBB->isEHPad() &&
  518. MBB->getIterator() != MBB->getParent()->begin()) {
  519. report("MBB has allocatable live-in, but isn't entry or landing-pad.", MBB);
  520. }
  521. }
  522. }
  523. // Count the number of landing pad successors.
  524. SmallPtrSet<MachineBasicBlock*, 4> LandingPadSuccs;
  525. for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
  526. E = MBB->succ_end(); I != E; ++I) {
  527. if ((*I)->isEHPad())
  528. LandingPadSuccs.insert(*I);
  529. if (!FunctionBlocks.count(*I))
  530. report("MBB has successor that isn't part of the function.", MBB);
  531. if (!MBBInfoMap[*I].Preds.count(MBB)) {
  532. report("Inconsistent CFG", MBB);
  533. errs() << "MBB is not in the predecessor list of the successor "
  534. << printMBBReference(*(*I)) << ".\n";
  535. }
  536. }
  537. // Check the predecessor list.
  538. for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(),
  539. E = MBB->pred_end(); I != E; ++I) {
  540. if (!FunctionBlocks.count(*I))
  541. report("MBB has predecessor that isn't part of the function.", MBB);
  542. if (!MBBInfoMap[*I].Succs.count(MBB)) {
  543. report("Inconsistent CFG", MBB);
  544. errs() << "MBB is not in the successor list of the predecessor "
  545. << printMBBReference(*(*I)) << ".\n";
  546. }
  547. }
  548. const MCAsmInfo *AsmInfo = TM->getMCAsmInfo();
  549. const BasicBlock *BB = MBB->getBasicBlock();
  550. const Function &F = MF->getFunction();
  551. if (LandingPadSuccs.size() > 1 &&
  552. !(AsmInfo &&
  553. AsmInfo->getExceptionHandlingType() == ExceptionHandling::SjLj &&
  554. BB && isa<SwitchInst>(BB->getTerminator())) &&
  555. !isFuncletEHPersonality(classifyEHPersonality(F.getPersonalityFn())))
  556. report("MBB has more than one landing pad successor", MBB);
  557. // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
  558. MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
  559. SmallVector<MachineOperand, 4> Cond;
  560. if (!TII->analyzeBranch(*const_cast<MachineBasicBlock *>(MBB), TBB, FBB,
  561. Cond)) {
  562. // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
  563. // check whether its answers match up with reality.
  564. if (!TBB && !FBB) {
  565. // Block falls through to its successor.
  566. MachineFunction::const_iterator MBBI = MBB->getIterator();
  567. ++MBBI;
  568. if (MBBI == MF->end()) {
  569. // It's possible that the block legitimately ends with a noreturn
  570. // call or an unreachable, in which case it won't actually fall
  571. // out the bottom of the function.
  572. } else if (MBB->succ_size() == LandingPadSuccs.size()) {
  573. // It's possible that the block legitimately ends with a noreturn
  574. // call or an unreachable, in which case it won't actuall fall
  575. // out of the block.
  576. } else if (MBB->succ_size() != 1+LandingPadSuccs.size()) {
  577. report("MBB exits via unconditional fall-through but doesn't have "
  578. "exactly one CFG successor!", MBB);
  579. } else if (!MBB->isSuccessor(&*MBBI)) {
  580. report("MBB exits via unconditional fall-through but its successor "
  581. "differs from its CFG successor!", MBB);
  582. }
  583. if (!MBB->empty() && MBB->back().isBarrier() &&
  584. !TII->isPredicated(MBB->back())) {
  585. report("MBB exits via unconditional fall-through but ends with a "
  586. "barrier instruction!", MBB);
  587. }
  588. if (!Cond.empty()) {
  589. report("MBB exits via unconditional fall-through but has a condition!",
  590. MBB);
  591. }
  592. } else if (TBB && !FBB && Cond.empty()) {
  593. // Block unconditionally branches somewhere.
  594. // If the block has exactly one successor, that happens to be a
  595. // landingpad, accept it as valid control flow.
  596. if (MBB->succ_size() != 1+LandingPadSuccs.size() &&
  597. (MBB->succ_size() != 1 || LandingPadSuccs.size() != 1 ||
  598. *MBB->succ_begin() != *LandingPadSuccs.begin())) {
  599. report("MBB exits via unconditional branch but doesn't have "
  600. "exactly one CFG successor!", MBB);
  601. } else if (!MBB->isSuccessor(TBB)) {
  602. report("MBB exits via unconditional branch but the CFG "
  603. "successor doesn't match the actual successor!", MBB);
  604. }
  605. if (MBB->empty()) {
  606. report("MBB exits via unconditional branch but doesn't contain "
  607. "any instructions!", MBB);
  608. } else if (!MBB->back().isBarrier()) {
  609. report("MBB exits via unconditional branch but doesn't end with a "
  610. "barrier instruction!", MBB);
  611. } else if (!MBB->back().isTerminator()) {
  612. report("MBB exits via unconditional branch but the branch isn't a "
  613. "terminator instruction!", MBB);
  614. }
  615. } else if (TBB && !FBB && !Cond.empty()) {
  616. // Block conditionally branches somewhere, otherwise falls through.
  617. MachineFunction::const_iterator MBBI = MBB->getIterator();
  618. ++MBBI;
  619. if (MBBI == MF->end()) {
  620. report("MBB conditionally falls through out of function!", MBB);
  621. } else if (MBB->succ_size() == 1) {
  622. // A conditional branch with only one successor is weird, but allowed.
  623. if (&*MBBI != TBB)
  624. report("MBB exits via conditional branch/fall-through but only has "
  625. "one CFG successor!", MBB);
  626. else if (TBB != *MBB->succ_begin())
  627. report("MBB exits via conditional branch/fall-through but the CFG "
  628. "successor don't match the actual successor!", MBB);
  629. } else if (MBB->succ_size() != 2) {
  630. report("MBB exits via conditional branch/fall-through but doesn't have "
  631. "exactly two CFG successors!", MBB);
  632. } else if (!matchPair(MBB->succ_begin(), TBB, &*MBBI)) {
  633. report("MBB exits via conditional branch/fall-through but the CFG "
  634. "successors don't match the actual successors!", MBB);
  635. }
  636. if (MBB->empty()) {
  637. report("MBB exits via conditional branch/fall-through but doesn't "
  638. "contain any instructions!", MBB);
  639. } else if (MBB->back().isBarrier()) {
  640. report("MBB exits via conditional branch/fall-through but ends with a "
  641. "barrier instruction!", MBB);
  642. } else if (!MBB->back().isTerminator()) {
  643. report("MBB exits via conditional branch/fall-through but the branch "
  644. "isn't a terminator instruction!", MBB);
  645. }
  646. } else if (TBB && FBB) {
  647. // Block conditionally branches somewhere, otherwise branches
  648. // somewhere else.
  649. if (MBB->succ_size() == 1) {
  650. // A conditional branch with only one successor is weird, but allowed.
  651. if (FBB != TBB)
  652. report("MBB exits via conditional branch/branch through but only has "
  653. "one CFG successor!", MBB);
  654. else if (TBB != *MBB->succ_begin())
  655. report("MBB exits via conditional branch/branch through but the CFG "
  656. "successor don't match the actual successor!", MBB);
  657. } else if (MBB->succ_size() != 2) {
  658. report("MBB exits via conditional branch/branch but doesn't have "
  659. "exactly two CFG successors!", MBB);
  660. } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
  661. report("MBB exits via conditional branch/branch but the CFG "
  662. "successors don't match the actual successors!", MBB);
  663. }
  664. if (MBB->empty()) {
  665. report("MBB exits via conditional branch/branch but doesn't "
  666. "contain any instructions!", MBB);
  667. } else if (!MBB->back().isBarrier()) {
  668. report("MBB exits via conditional branch/branch but doesn't end with a "
  669. "barrier instruction!", MBB);
  670. } else if (!MBB->back().isTerminator()) {
  671. report("MBB exits via conditional branch/branch but the branch "
  672. "isn't a terminator instruction!", MBB);
  673. }
  674. if (Cond.empty()) {
  675. report("MBB exits via conditinal branch/branch but there's no "
  676. "condition!", MBB);
  677. }
  678. } else {
  679. report("AnalyzeBranch returned invalid data!", MBB);
  680. }
  681. }
  682. regsLive.clear();
  683. if (MRI->tracksLiveness()) {
  684. for (const auto &LI : MBB->liveins()) {
  685. if (!TargetRegisterInfo::isPhysicalRegister(LI.PhysReg)) {
  686. report("MBB live-in list contains non-physical register", MBB);
  687. continue;
  688. }
  689. for (MCSubRegIterator SubRegs(LI.PhysReg, TRI, /*IncludeSelf=*/true);
  690. SubRegs.isValid(); ++SubRegs)
  691. regsLive.insert(*SubRegs);
  692. }
  693. }
  694. const MachineFrameInfo &MFI = MF->getFrameInfo();
  695. BitVector PR = MFI.getPristineRegs(*MF);
  696. for (unsigned I : PR.set_bits()) {
  697. for (MCSubRegIterator SubRegs(I, TRI, /*IncludeSelf=*/true);
  698. SubRegs.isValid(); ++SubRegs)
  699. regsLive.insert(*SubRegs);
  700. }
  701. regsKilled.clear();
  702. regsDefined.clear();
  703. if (Indexes)
  704. lastIndex = Indexes->getMBBStartIdx(MBB);
  705. }
  706. // This function gets called for all bundle headers, including normal
  707. // stand-alone unbundled instructions.
  708. void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
  709. if (Indexes && Indexes->hasIndex(*MI)) {
  710. SlotIndex idx = Indexes->getInstructionIndex(*MI);
  711. if (!(idx > lastIndex)) {
  712. report("Instruction index out of order", MI);
  713. errs() << "Last instruction was at " << lastIndex << '\n';
  714. }
  715. lastIndex = idx;
  716. }
  717. // Ensure non-terminators don't follow terminators.
  718. // Ignore predicated terminators formed by if conversion.
  719. // FIXME: If conversion shouldn't need to violate this rule.
  720. if (MI->isTerminator() && !TII->isPredicated(*MI)) {
  721. if (!FirstTerminator)
  722. FirstTerminator = MI;
  723. } else if (FirstTerminator) {
  724. report("Non-terminator instruction after the first terminator", MI);
  725. errs() << "First terminator was:\t" << *FirstTerminator;
  726. }
  727. }
  728. // The operands on an INLINEASM instruction must follow a template.
  729. // Verify that the flag operands make sense.
  730. void MachineVerifier::verifyInlineAsm(const MachineInstr *MI) {
  731. // The first two operands on INLINEASM are the asm string and global flags.
  732. if (MI->getNumOperands() < 2) {
  733. report("Too few operands on inline asm", MI);
  734. return;
  735. }
  736. if (!MI->getOperand(0).isSymbol())
  737. report("Asm string must be an external symbol", MI);
  738. if (!MI->getOperand(1).isImm())
  739. report("Asm flags must be an immediate", MI);
  740. // Allowed flags are Extra_HasSideEffects = 1, Extra_IsAlignStack = 2,
  741. // Extra_AsmDialect = 4, Extra_MayLoad = 8, and Extra_MayStore = 16,
  742. // and Extra_IsConvergent = 32.
  743. if (!isUInt<6>(MI->getOperand(1).getImm()))
  744. report("Unknown asm flags", &MI->getOperand(1), 1);
  745. static_assert(InlineAsm::MIOp_FirstOperand == 2, "Asm format changed");
  746. unsigned OpNo = InlineAsm::MIOp_FirstOperand;
  747. unsigned NumOps;
  748. for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) {
  749. const MachineOperand &MO = MI->getOperand(OpNo);
  750. // There may be implicit ops after the fixed operands.
  751. if (!MO.isImm())
  752. break;
  753. NumOps = 1 + InlineAsm::getNumOperandRegisters(MO.getImm());
  754. }
  755. if (OpNo > MI->getNumOperands())
  756. report("Missing operands in last group", MI);
  757. // An optional MDNode follows the groups.
  758. if (OpNo < MI->getNumOperands() && MI->getOperand(OpNo).isMetadata())
  759. ++OpNo;
  760. // All trailing operands must be implicit registers.
  761. for (unsigned e = MI->getNumOperands(); OpNo < e; ++OpNo) {
  762. const MachineOperand &MO = MI->getOperand(OpNo);
  763. if (!MO.isReg() || !MO.isImplicit())
  764. report("Expected implicit register after groups", &MO, OpNo);
  765. }
  766. }
  767. void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
  768. const MCInstrDesc &MCID = MI->getDesc();
  769. if (MI->getNumOperands() < MCID.getNumOperands()) {
  770. report("Too few operands", MI);
  771. errs() << MCID.getNumOperands() << " operands expected, but "
  772. << MI->getNumOperands() << " given.\n";
  773. }
  774. if (MI->isPHI() && MF->getProperties().hasProperty(
  775. MachineFunctionProperties::Property::NoPHIs))
  776. report("Found PHI instruction with NoPHIs property set", MI);
  777. // Check the tied operands.
  778. if (MI->isInlineAsm())
  779. verifyInlineAsm(MI);
  780. // Check the MachineMemOperands for basic consistency.
  781. for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
  782. E = MI->memoperands_end();
  783. I != E; ++I) {
  784. if ((*I)->isLoad() && !MI->mayLoad())
  785. report("Missing mayLoad flag", MI);
  786. if ((*I)->isStore() && !MI->mayStore())
  787. report("Missing mayStore flag", MI);
  788. }
  789. // Debug values must not have a slot index.
  790. // Other instructions must have one, unless they are inside a bundle.
  791. if (LiveInts) {
  792. bool mapped = !LiveInts->isNotInMIMap(*MI);
  793. if (MI->isDebugInstr()) {
  794. if (mapped)
  795. report("Debug instruction has a slot index", MI);
  796. } else if (MI->isInsideBundle()) {
  797. if (mapped)
  798. report("Instruction inside bundle has a slot index", MI);
  799. } else {
  800. if (!mapped)
  801. report("Missing slot index", MI);
  802. }
  803. }
  804. if (isPreISelGenericOpcode(MCID.getOpcode())) {
  805. if (isFunctionSelected)
  806. report("Unexpected generic instruction in a Selected function", MI);
  807. // Check types.
  808. SmallVector<LLT, 4> Types;
  809. for (unsigned I = 0; I < MCID.getNumOperands(); ++I) {
  810. if (!MCID.OpInfo[I].isGenericType())
  811. continue;
  812. // Generic instructions specify type equality constraints between some of
  813. // their operands. Make sure these are consistent.
  814. size_t TypeIdx = MCID.OpInfo[I].getGenericTypeIndex();
  815. Types.resize(std::max(TypeIdx + 1, Types.size()));
  816. const MachineOperand *MO = &MI->getOperand(I);
  817. LLT OpTy = MRI->getType(MO->getReg());
  818. // Don't report a type mismatch if there is no actual mismatch, only a
  819. // type missing, to reduce noise:
  820. if (OpTy.isValid()) {
  821. // Only the first valid type for a type index will be printed: don't
  822. // overwrite it later so it's always clear which type was expected:
  823. if (!Types[TypeIdx].isValid())
  824. Types[TypeIdx] = OpTy;
  825. else if (Types[TypeIdx] != OpTy)
  826. report("Type mismatch in generic instruction", MO, I, OpTy);
  827. } else {
  828. // Generic instructions must have types attached to their operands.
  829. report("Generic instruction is missing a virtual register type", MO, I);
  830. }
  831. }
  832. // Generic opcodes must not have physical register operands.
  833. for (unsigned I = 0; I < MI->getNumOperands(); ++I) {
  834. const MachineOperand *MO = &MI->getOperand(I);
  835. if (MO->isReg() && TargetRegisterInfo::isPhysicalRegister(MO->getReg()))
  836. report("Generic instruction cannot have physical register", MO, I);
  837. }
  838. }
  839. StringRef ErrorInfo;
  840. if (!TII->verifyInstruction(*MI, ErrorInfo))
  841. report(ErrorInfo.data(), MI);
  842. // Verify properties of various specific instruction types
  843. switch(MI->getOpcode()) {
  844. default:
  845. break;
  846. case TargetOpcode::G_LOAD:
  847. case TargetOpcode::G_STORE:
  848. // Generic loads and stores must have a single MachineMemOperand
  849. // describing that access.
  850. if (!MI->hasOneMemOperand())
  851. report("Generic instruction accessing memory must have one mem operand",
  852. MI);
  853. break;
  854. case TargetOpcode::G_PHI: {
  855. LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
  856. if (!DstTy.isValid() ||
  857. !std::all_of(MI->operands_begin() + 1, MI->operands_end(),
  858. [this, &DstTy](const MachineOperand &MO) {
  859. if (!MO.isReg())
  860. return true;
  861. LLT Ty = MRI->getType(MO.getReg());
  862. if (!Ty.isValid() || (Ty != DstTy))
  863. return false;
  864. return true;
  865. }))
  866. report("Generic Instruction G_PHI has operands with incompatible/missing "
  867. "types",
  868. MI);
  869. break;
  870. }
  871. case TargetOpcode::G_SEXT:
  872. case TargetOpcode::G_ZEXT:
  873. case TargetOpcode::G_ANYEXT:
  874. case TargetOpcode::G_TRUNC:
  875. case TargetOpcode::G_FPEXT:
  876. case TargetOpcode::G_FPTRUNC: {
  877. // Number of operands and presense of types is already checked (and
  878. // reported in case of any issues), so no need to report them again. As
  879. // we're trying to report as many issues as possible at once, however, the
  880. // instructions aren't guaranteed to have the right number of operands or
  881. // types attached to them at this point
  882. assert(MCID.getNumOperands() == 2 && "Expected 2 operands G_*{EXT,TRUNC}");
  883. if (MI->getNumOperands() < MCID.getNumOperands())
  884. break;
  885. LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
  886. LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
  887. if (!DstTy.isValid() || !SrcTy.isValid())
  888. break;
  889. LLT DstElTy = DstTy.isVector() ? DstTy.getElementType() : DstTy;
  890. LLT SrcElTy = SrcTy.isVector() ? SrcTy.getElementType() : SrcTy;
  891. if (DstElTy.isPointer() || SrcElTy.isPointer())
  892. report("Generic extend/truncate can not operate on pointers", MI);
  893. if (DstTy.isVector() != SrcTy.isVector()) {
  894. report("Generic extend/truncate must be all-vector or all-scalar", MI);
  895. // Generally we try to report as many issues as possible at once, but in
  896. // this case it's not clear what should we be comparing the size of the
  897. // scalar with: the size of the whole vector or its lane. Instead of
  898. // making an arbitrary choice and emitting not so helpful message, let's
  899. // avoid the extra noise and stop here.
  900. break;
  901. }
  902. if (DstTy.isVector() && DstTy.getNumElements() != SrcTy.getNumElements())
  903. report("Generic vector extend/truncate must preserve number of lanes",
  904. MI);
  905. unsigned DstSize = DstElTy.getSizeInBits();
  906. unsigned SrcSize = SrcElTy.getSizeInBits();
  907. switch (MI->getOpcode()) {
  908. default:
  909. if (DstSize <= SrcSize)
  910. report("Generic extend has destination type no larger than source", MI);
  911. break;
  912. case TargetOpcode::G_TRUNC:
  913. case TargetOpcode::G_FPTRUNC:
  914. if (DstSize >= SrcSize)
  915. report("Generic truncate has destination type no smaller than source",
  916. MI);
  917. break;
  918. }
  919. break;
  920. }
  921. case TargetOpcode::COPY: {
  922. if (foundErrors)
  923. break;
  924. const MachineOperand &DstOp = MI->getOperand(0);
  925. const MachineOperand &SrcOp = MI->getOperand(1);
  926. LLT DstTy = MRI->getType(DstOp.getReg());
  927. LLT SrcTy = MRI->getType(SrcOp.getReg());
  928. if (SrcTy.isValid() && DstTy.isValid()) {
  929. // If both types are valid, check that the types are the same.
  930. if (SrcTy != DstTy) {
  931. report("Copy Instruction is illegal with mismatching types", MI);
  932. errs() << "Def = " << DstTy << ", Src = " << SrcTy << "\n";
  933. }
  934. }
  935. if (SrcTy.isValid() || DstTy.isValid()) {
  936. // If one of them have valid types, let's just check they have the same
  937. // size.
  938. unsigned SrcSize = TRI->getRegSizeInBits(SrcOp.getReg(), *MRI);
  939. unsigned DstSize = TRI->getRegSizeInBits(DstOp.getReg(), *MRI);
  940. assert(SrcSize && "Expecting size here");
  941. assert(DstSize && "Expecting size here");
  942. if (SrcSize != DstSize)
  943. if (!DstOp.getSubReg() && !SrcOp.getSubReg()) {
  944. report("Copy Instruction is illegal with mismatching sizes", MI);
  945. errs() << "Def Size = " << DstSize << ", Src Size = " << SrcSize
  946. << "\n";
  947. }
  948. }
  949. break;
  950. }
  951. case TargetOpcode::STATEPOINT:
  952. if (!MI->getOperand(StatepointOpers::IDPos).isImm() ||
  953. !MI->getOperand(StatepointOpers::NBytesPos).isImm() ||
  954. !MI->getOperand(StatepointOpers::NCallArgsPos).isImm())
  955. report("meta operands to STATEPOINT not constant!", MI);
  956. break;
  957. auto VerifyStackMapConstant = [&](unsigned Offset) {
  958. if (!MI->getOperand(Offset).isImm() ||
  959. MI->getOperand(Offset).getImm() != StackMaps::ConstantOp ||
  960. !MI->getOperand(Offset + 1).isImm())
  961. report("stack map constant to STATEPOINT not well formed!", MI);
  962. };
  963. const unsigned VarStart = StatepointOpers(MI).getVarIdx();
  964. VerifyStackMapConstant(VarStart + StatepointOpers::CCOffset);
  965. VerifyStackMapConstant(VarStart + StatepointOpers::FlagsOffset);
  966. VerifyStackMapConstant(VarStart + StatepointOpers::NumDeoptOperandsOffset);
  967. // TODO: verify we have properly encoded deopt arguments
  968. };
  969. }
  970. void
  971. MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
  972. const MachineInstr *MI = MO->getParent();
  973. const MCInstrDesc &MCID = MI->getDesc();
  974. unsigned NumDefs = MCID.getNumDefs();
  975. if (MCID.getOpcode() == TargetOpcode::PATCHPOINT)
  976. NumDefs = (MONum == 0 && MO->isReg()) ? NumDefs : 0;
  977. // The first MCID.NumDefs operands must be explicit register defines
  978. if (MONum < NumDefs) {
  979. const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
  980. if (!MO->isReg())
  981. report("Explicit definition must be a register", MO, MONum);
  982. else if (!MO->isDef() && !MCOI.isOptionalDef())
  983. report("Explicit definition marked as use", MO, MONum);
  984. else if (MO->isImplicit())
  985. report("Explicit definition marked as implicit", MO, MONum);
  986. } else if (MONum < MCID.getNumOperands()) {
  987. const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
  988. // Don't check if it's the last operand in a variadic instruction. See,
  989. // e.g., LDM_RET in the arm back end.
  990. if (MO->isReg() &&
  991. !(MI->isVariadic() && MONum == MCID.getNumOperands()-1)) {
  992. if (MO->isDef() && !MCOI.isOptionalDef())
  993. report("Explicit operand marked as def", MO, MONum);
  994. if (MO->isImplicit())
  995. report("Explicit operand marked as implicit", MO, MONum);
  996. }
  997. int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO);
  998. if (TiedTo != -1) {
  999. if (!MO->isReg())
  1000. report("Tied use must be a register", MO, MONum);
  1001. else if (!MO->isTied())
  1002. report("Operand should be tied", MO, MONum);
  1003. else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum))
  1004. report("Tied def doesn't match MCInstrDesc", MO, MONum);
  1005. else if (TargetRegisterInfo::isPhysicalRegister(MO->getReg())) {
  1006. const MachineOperand &MOTied = MI->getOperand(TiedTo);
  1007. if (!MOTied.isReg())
  1008. report("Tied counterpart must be a register", &MOTied, TiedTo);
  1009. else if (TargetRegisterInfo::isPhysicalRegister(MOTied.getReg()) &&
  1010. MO->getReg() != MOTied.getReg())
  1011. report("Tied physical registers must match.", &MOTied, TiedTo);
  1012. }
  1013. } else if (MO->isReg() && MO->isTied())
  1014. report("Explicit operand should not be tied", MO, MONum);
  1015. } else {
  1016. // ARM adds %reg0 operands to indicate predicates. We'll allow that.
  1017. if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg())
  1018. report("Extra explicit operand on non-variadic instruction", MO, MONum);
  1019. }
  1020. switch (MO->getType()) {
  1021. case MachineOperand::MO_Register: {
  1022. const unsigned Reg = MO->getReg();
  1023. if (!Reg)
  1024. return;
  1025. if (MRI->tracksLiveness() && !MI->isDebugValue())
  1026. checkLiveness(MO, MONum);
  1027. // Verify the consistency of tied operands.
  1028. if (MO->isTied()) {
  1029. unsigned OtherIdx = MI->findTiedOperandIdx(MONum);
  1030. const MachineOperand &OtherMO = MI->getOperand(OtherIdx);
  1031. if (!OtherMO.isReg())
  1032. report("Must be tied to a register", MO, MONum);
  1033. if (!OtherMO.isTied())
  1034. report("Missing tie flags on tied operand", MO, MONum);
  1035. if (MI->findTiedOperandIdx(OtherIdx) != MONum)
  1036. report("Inconsistent tie links", MO, MONum);
  1037. if (MONum < MCID.getNumDefs()) {
  1038. if (OtherIdx < MCID.getNumOperands()) {
  1039. if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO))
  1040. report("Explicit def tied to explicit use without tie constraint",
  1041. MO, MONum);
  1042. } else {
  1043. if (!OtherMO.isImplicit())
  1044. report("Explicit def should be tied to implicit use", MO, MONum);
  1045. }
  1046. }
  1047. }
  1048. // Verify two-address constraints after leaving SSA form.
  1049. unsigned DefIdx;
  1050. if (!MRI->isSSA() && MO->isUse() &&
  1051. MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
  1052. Reg != MI->getOperand(DefIdx).getReg())
  1053. report("Two-address instruction operands must be identical", MO, MONum);
  1054. // Check register classes.
  1055. unsigned SubIdx = MO->getSubReg();
  1056. if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
  1057. if (SubIdx) {
  1058. report("Illegal subregister index for physical register", MO, MONum);
  1059. return;
  1060. }
  1061. if (MONum < MCID.getNumOperands()) {
  1062. if (const TargetRegisterClass *DRC =
  1063. TII->getRegClass(MCID, MONum, TRI, *MF)) {
  1064. if (!DRC->contains(Reg)) {
  1065. report("Illegal physical register for instruction", MO, MONum);
  1066. errs() << printReg(Reg, TRI) << " is not a "
  1067. << TRI->getRegClassName(DRC) << " register.\n";
  1068. }
  1069. }
  1070. }
  1071. if (MO->isRenamable()) {
  1072. if (MRI->isReserved(Reg)) {
  1073. report("isRenamable set on reserved register", MO, MONum);
  1074. return;
  1075. }
  1076. }
  1077. } else {
  1078. // Virtual register.
  1079. const TargetRegisterClass *RC = MRI->getRegClassOrNull(Reg);
  1080. if (!RC) {
  1081. // This is a generic virtual register.
  1082. // If we're post-Select, we can't have gvregs anymore.
  1083. if (isFunctionSelected) {
  1084. report("Generic virtual register invalid in a Selected function",
  1085. MO, MONum);
  1086. return;
  1087. }
  1088. // The gvreg must have a type and it must not have a SubIdx.
  1089. LLT Ty = MRI->getType(Reg);
  1090. if (!Ty.isValid()) {
  1091. report("Generic virtual register must have a valid type", MO,
  1092. MONum);
  1093. return;
  1094. }
  1095. const RegisterBank *RegBank = MRI->getRegBankOrNull(Reg);
  1096. // If we're post-RegBankSelect, the gvreg must have a bank.
  1097. if (!RegBank && isFunctionRegBankSelected) {
  1098. report("Generic virtual register must have a bank in a "
  1099. "RegBankSelected function",
  1100. MO, MONum);
  1101. return;
  1102. }
  1103. // Make sure the register fits into its register bank if any.
  1104. if (RegBank && Ty.isValid() &&
  1105. RegBank->getSize() < Ty.getSizeInBits()) {
  1106. report("Register bank is too small for virtual register", MO,
  1107. MONum);
  1108. errs() << "Register bank " << RegBank->getName() << " too small("
  1109. << RegBank->getSize() << ") to fit " << Ty.getSizeInBits()
  1110. << "-bits\n";
  1111. return;
  1112. }
  1113. if (SubIdx) {
  1114. report("Generic virtual register does not subregister index", MO,
  1115. MONum);
  1116. return;
  1117. }
  1118. // If this is a target specific instruction and this operand
  1119. // has register class constraint, the virtual register must
  1120. // comply to it.
  1121. if (!isPreISelGenericOpcode(MCID.getOpcode()) &&
  1122. MONum < MCID.getNumOperands() &&
  1123. TII->getRegClass(MCID, MONum, TRI, *MF)) {
  1124. report("Virtual register does not match instruction constraint", MO,
  1125. MONum);
  1126. errs() << "Expect register class "
  1127. << TRI->getRegClassName(
  1128. TII->getRegClass(MCID, MONum, TRI, *MF))
  1129. << " but got nothing\n";
  1130. return;
  1131. }
  1132. break;
  1133. }
  1134. if (SubIdx) {
  1135. const TargetRegisterClass *SRC =
  1136. TRI->getSubClassWithSubReg(RC, SubIdx);
  1137. if (!SRC) {
  1138. report("Invalid subregister index for virtual register", MO, MONum);
  1139. errs() << "Register class " << TRI->getRegClassName(RC)
  1140. << " does not support subreg index " << SubIdx << "\n";
  1141. return;
  1142. }
  1143. if (RC != SRC) {
  1144. report("Invalid register class for subregister index", MO, MONum);
  1145. errs() << "Register class " << TRI->getRegClassName(RC)
  1146. << " does not fully support subreg index " << SubIdx << "\n";
  1147. return;
  1148. }
  1149. }
  1150. if (MONum < MCID.getNumOperands()) {
  1151. if (const TargetRegisterClass *DRC =
  1152. TII->getRegClass(MCID, MONum, TRI, *MF)) {
  1153. if (SubIdx) {
  1154. const TargetRegisterClass *SuperRC =
  1155. TRI->getLargestLegalSuperClass(RC, *MF);
  1156. if (!SuperRC) {
  1157. report("No largest legal super class exists.", MO, MONum);
  1158. return;
  1159. }
  1160. DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
  1161. if (!DRC) {
  1162. report("No matching super-reg register class.", MO, MONum);
  1163. return;
  1164. }
  1165. }
  1166. if (!RC->hasSuperClassEq(DRC)) {
  1167. report("Illegal virtual register for instruction", MO, MONum);
  1168. errs() << "Expected a " << TRI->getRegClassName(DRC)
  1169. << " register, but got a " << TRI->getRegClassName(RC)
  1170. << " register\n";
  1171. }
  1172. }
  1173. }
  1174. }
  1175. break;
  1176. }
  1177. case MachineOperand::MO_RegisterMask:
  1178. regMasks.push_back(MO->getRegMask());
  1179. break;
  1180. case MachineOperand::MO_MachineBasicBlock:
  1181. if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
  1182. report("PHI operand is not in the CFG", MO, MONum);
  1183. break;
  1184. case MachineOperand::MO_FrameIndex:
  1185. if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
  1186. LiveInts && !LiveInts->isNotInMIMap(*MI)) {
  1187. int FI = MO->getIndex();
  1188. LiveInterval &LI = LiveStks->getInterval(FI);
  1189. SlotIndex Idx = LiveInts->getInstructionIndex(*MI);
  1190. bool stores = MI->mayStore();
  1191. bool loads = MI->mayLoad();
  1192. // For a memory-to-memory move, we need to check if the frame
  1193. // index is used for storing or loading, by inspecting the
  1194. // memory operands.
  1195. if (stores && loads) {
  1196. for (auto *MMO : MI->memoperands()) {
  1197. const PseudoSourceValue *PSV = MMO->getPseudoValue();
  1198. if (PSV == nullptr) continue;
  1199. const FixedStackPseudoSourceValue *Value =
  1200. dyn_cast<FixedStackPseudoSourceValue>(PSV);
  1201. if (Value == nullptr) continue;
  1202. if (Value->getFrameIndex() != FI) continue;
  1203. if (MMO->isStore())
  1204. loads = false;
  1205. else
  1206. stores = false;
  1207. break;
  1208. }
  1209. if (loads == stores)
  1210. report("Missing fixed stack memoperand.", MI);
  1211. }
  1212. if (loads && !LI.liveAt(Idx.getRegSlot(true))) {
  1213. report("Instruction loads from dead spill slot", MO, MONum);
  1214. errs() << "Live stack: " << LI << '\n';
  1215. }
  1216. if (stores && !LI.liveAt(Idx.getRegSlot())) {
  1217. report("Instruction stores to dead spill slot", MO, MONum);
  1218. errs() << "Live stack: " << LI << '\n';
  1219. }
  1220. }
  1221. break;
  1222. default:
  1223. break;
  1224. }
  1225. }
  1226. void MachineVerifier::checkLivenessAtUse(const MachineOperand *MO,
  1227. unsigned MONum, SlotIndex UseIdx, const LiveRange &LR, unsigned VRegOrUnit,
  1228. LaneBitmask LaneMask) {
  1229. LiveQueryResult LRQ = LR.Query(UseIdx);
  1230. // Check if we have a segment at the use, note however that we only need one
  1231. // live subregister range, the others may be dead.
  1232. if (!LRQ.valueIn() && LaneMask.none()) {
  1233. report("No live segment at use", MO, MONum);
  1234. report_context_liverange(LR);
  1235. report_context_vreg_regunit(VRegOrUnit);
  1236. report_context(UseIdx);
  1237. }
  1238. if (MO->isKill() && !LRQ.isKill()) {
  1239. report("Live range continues after kill flag", MO, MONum);
  1240. report_context_liverange(LR);
  1241. report_context_vreg_regunit(VRegOrUnit);
  1242. if (LaneMask.any())
  1243. report_context_lanemask(LaneMask);
  1244. report_context(UseIdx);
  1245. }
  1246. }
  1247. void MachineVerifier::checkLivenessAtDef(const MachineOperand *MO,
  1248. unsigned MONum, SlotIndex DefIdx, const LiveRange &LR, unsigned VRegOrUnit,
  1249. LaneBitmask LaneMask) {
  1250. if (const VNInfo *VNI = LR.getVNInfoAt(DefIdx)) {
  1251. assert(VNI && "NULL valno is not allowed");
  1252. if (VNI->def != DefIdx) {
  1253. report("Inconsistent valno->def", MO, MONum);
  1254. report_context_liverange(LR);
  1255. report_context_vreg_regunit(VRegOrUnit);
  1256. if (LaneMask.any())
  1257. report_context_lanemask(LaneMask);
  1258. report_context(*VNI);
  1259. report_context(DefIdx);
  1260. }
  1261. } else {
  1262. report("No live segment at def", MO, MONum);
  1263. report_context_liverange(LR);
  1264. report_context_vreg_regunit(VRegOrUnit);
  1265. if (LaneMask.any())
  1266. report_context_lanemask(LaneMask);
  1267. report_context(DefIdx);
  1268. }
  1269. // Check that, if the dead def flag is present, LiveInts agree.
  1270. if (MO->isDead()) {
  1271. LiveQueryResult LRQ = LR.Query(DefIdx);
  1272. if (!LRQ.isDeadDef()) {
  1273. // In case of physregs we can have a non-dead definition on another
  1274. // operand.
  1275. bool otherDef = false;
  1276. if (!TargetRegisterInfo::isVirtualRegister(VRegOrUnit)) {
  1277. const MachineInstr &MI = *MO->getParent();
  1278. for (const MachineOperand &MO : MI.operands()) {
  1279. if (!MO.isReg() || !MO.isDef() || MO.isDead())
  1280. continue;
  1281. unsigned Reg = MO.getReg();
  1282. for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
  1283. if (*Units == VRegOrUnit) {
  1284. otherDef = true;
  1285. break;
  1286. }
  1287. }
  1288. }
  1289. }
  1290. if (!otherDef) {
  1291. report("Live range continues after dead def flag", MO, MONum);
  1292. report_context_liverange(LR);
  1293. report_context_vreg_regunit(VRegOrUnit);
  1294. if (LaneMask.any())
  1295. report_context_lanemask(LaneMask);
  1296. }
  1297. }
  1298. }
  1299. }
  1300. void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
  1301. const MachineInstr *MI = MO->getParent();
  1302. const unsigned Reg = MO->getReg();
  1303. // Both use and def operands can read a register.
  1304. if (MO->readsReg()) {
  1305. if (MO->isKill())
  1306. addRegWithSubRegs(regsKilled, Reg);
  1307. // Check that LiveVars knows this kill.
  1308. if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg) &&
  1309. MO->isKill()) {
  1310. LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
  1311. if (!is_contained(VI.Kills, MI))
  1312. report("Kill missing from LiveVariables", MO, MONum);
  1313. }
  1314. // Check LiveInts liveness and kill.
  1315. if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
  1316. SlotIndex UseIdx = LiveInts->getInstructionIndex(*MI);
  1317. // Check the cached regunit intervals.
  1318. if (TargetRegisterInfo::isPhysicalRegister(Reg) && !isReserved(Reg)) {
  1319. for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
  1320. if (MRI->isReservedRegUnit(*Units))
  1321. continue;
  1322. if (const LiveRange *LR = LiveInts->getCachedRegUnit(*Units))
  1323. checkLivenessAtUse(MO, MONum, UseIdx, *LR, *Units);
  1324. }
  1325. }
  1326. if (TargetRegisterInfo::isVirtualRegister(Reg)) {
  1327. if (LiveInts->hasInterval(Reg)) {
  1328. // This is a virtual register interval.
  1329. const LiveInterval &LI = LiveInts->getInterval(Reg);
  1330. checkLivenessAtUse(MO, MONum, UseIdx, LI, Reg);
  1331. if (LI.hasSubRanges() && !MO->isDef()) {
  1332. unsigned SubRegIdx = MO->getSubReg();
  1333. LaneBitmask MOMask = SubRegIdx != 0
  1334. ? TRI->getSubRegIndexLaneMask(SubRegIdx)
  1335. : MRI->getMaxLaneMaskForVReg(Reg);
  1336. LaneBitmask LiveInMask;
  1337. for (const LiveInterval::SubRange &SR : LI.subranges()) {
  1338. if ((MOMask & SR.LaneMask).none())
  1339. continue;
  1340. checkLivenessAtUse(MO, MONum, UseIdx, SR, Reg, SR.LaneMask);
  1341. LiveQueryResult LRQ = SR.Query(UseIdx);
  1342. if (LRQ.valueIn())
  1343. LiveInMask |= SR.LaneMask;
  1344. }
  1345. // At least parts of the register has to be live at the use.
  1346. if ((LiveInMask & MOMask).none()) {
  1347. report("No live subrange at use", MO, MONum);
  1348. report_context(LI);
  1349. report_context(UseIdx);
  1350. }
  1351. }
  1352. } else {
  1353. report("Virtual register has no live interval", MO, MONum);
  1354. }
  1355. }
  1356. }
  1357. // Use of a dead register.
  1358. if (!regsLive.count(Reg)) {
  1359. if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
  1360. // Reserved registers may be used even when 'dead'.
  1361. bool Bad = !isReserved(Reg);
  1362. // We are fine if just any subregister has a defined value.
  1363. if (Bad) {
  1364. for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid();
  1365. ++SubRegs) {
  1366. if (regsLive.count(*SubRegs)) {
  1367. Bad = false;
  1368. break;
  1369. }
  1370. }
  1371. }
  1372. // If there is an additional implicit-use of a super register we stop
  1373. // here. By definition we are fine if the super register is not
  1374. // (completely) dead, if the complete super register is dead we will
  1375. // get a report for its operand.
  1376. if (Bad) {
  1377. for (const MachineOperand &MOP : MI->uses()) {
  1378. if (!MOP.isReg())
  1379. continue;
  1380. if (!MOP.isImplicit())
  1381. continue;
  1382. for (MCSubRegIterator SubRegs(MOP.getReg(), TRI); SubRegs.isValid();
  1383. ++SubRegs) {
  1384. if (*SubRegs == Reg) {
  1385. Bad = false;
  1386. break;
  1387. }
  1388. }
  1389. }
  1390. }
  1391. if (Bad)
  1392. report("Using an undefined physical register", MO, MONum);
  1393. } else if (MRI->def_empty(Reg)) {
  1394. report("Reading virtual register without a def", MO, MONum);
  1395. } else {
  1396. BBInfo &MInfo = MBBInfoMap[MI->getParent()];
  1397. // We don't know which virtual registers are live in, so only complain
  1398. // if vreg was killed in this MBB. Otherwise keep track of vregs that
  1399. // must be live in. PHI instructions are handled separately.
  1400. if (MInfo.regsKilled.count(Reg))
  1401. report("Using a killed virtual register", MO, MONum);
  1402. else if (!MI->isPHI())
  1403. MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
  1404. }
  1405. }
  1406. }
  1407. if (MO->isDef()) {
  1408. // Register defined.
  1409. // TODO: verify that earlyclobber ops are not used.
  1410. if (MO->isDead())
  1411. addRegWithSubRegs(regsDead, Reg);
  1412. else
  1413. addRegWithSubRegs(regsDefined, Reg);
  1414. // Verify SSA form.
  1415. if (MRI->isSSA() && TargetRegisterInfo::isVirtualRegister(Reg) &&
  1416. std::next(MRI->def_begin(Reg)) != MRI->def_end())
  1417. report("Multiple virtual register defs in SSA form", MO, MONum);
  1418. // Check LiveInts for a live segment, but only for virtual registers.
  1419. if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
  1420. SlotIndex DefIdx = LiveInts->getInstructionIndex(*MI);
  1421. DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber());
  1422. if (TargetRegisterInfo::isVirtualRegister(Reg)) {
  1423. if (LiveInts->hasInterval(Reg)) {
  1424. const LiveInterval &LI = LiveInts->getInterval(Reg);
  1425. checkLivenessAtDef(MO, MONum, DefIdx, LI, Reg);
  1426. if (LI.hasSubRanges()) {
  1427. unsigned SubRegIdx = MO->getSubReg();
  1428. LaneBitmask MOMask = SubRegIdx != 0
  1429. ? TRI->getSubRegIndexLaneMask(SubRegIdx)
  1430. : MRI->getMaxLaneMaskForVReg(Reg);
  1431. for (const LiveInterval::SubRange &SR : LI.subranges()) {
  1432. if ((SR.LaneMask & MOMask).none())
  1433. continue;
  1434. checkLivenessAtDef(MO, MONum, DefIdx, SR, Reg, SR.LaneMask);
  1435. }
  1436. }
  1437. } else {
  1438. report("Virtual register has no Live interval", MO, MONum);
  1439. }
  1440. }
  1441. }
  1442. }
  1443. }
  1444. void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {}
  1445. // This function gets called after visiting all instructions in a bundle. The
  1446. // argument points to the bundle header.
  1447. // Normal stand-alone instructions are also considered 'bundles', and this
  1448. // function is called for all of them.
  1449. void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
  1450. BBInfo &MInfo = MBBInfoMap[MI->getParent()];
  1451. set_union(MInfo.regsKilled, regsKilled);
  1452. set_subtract(regsLive, regsKilled); regsKilled.clear();
  1453. // Kill any masked registers.
  1454. while (!regMasks.empty()) {
  1455. const uint32_t *Mask = regMasks.pop_back_val();
  1456. for (RegSet::iterator I = regsLive.begin(), E = regsLive.end(); I != E; ++I)
  1457. if (TargetRegisterInfo::isPhysicalRegister(*I) &&
  1458. MachineOperand::clobbersPhysReg(Mask, *I))
  1459. regsDead.push_back(*I);
  1460. }
  1461. set_subtract(regsLive, regsDead); regsDead.clear();
  1462. set_union(regsLive, regsDefined); regsDefined.clear();
  1463. }
  1464. void
  1465. MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
  1466. MBBInfoMap[MBB].regsLiveOut = regsLive;
  1467. regsLive.clear();
  1468. if (Indexes) {
  1469. SlotIndex stop = Indexes->getMBBEndIdx(MBB);
  1470. if (!(stop > lastIndex)) {
  1471. report("Block ends before last instruction index", MBB);
  1472. errs() << "Block ends at " << stop
  1473. << " last instruction was at " << lastIndex << '\n';
  1474. }
  1475. lastIndex = stop;
  1476. }
  1477. }
  1478. // Calculate the largest possible vregsPassed sets. These are the registers that
  1479. // can pass through an MBB live, but may not be live every time. It is assumed
  1480. // that all vregsPassed sets are empty before the call.
  1481. void MachineVerifier::calcRegsPassed() {
  1482. // First push live-out regs to successors' vregsPassed. Remember the MBBs that
  1483. // have any vregsPassed.
  1484. SmallPtrSet<const MachineBasicBlock*, 8> todo;
  1485. for (const auto &MBB : *MF) {
  1486. BBInfo &MInfo = MBBInfoMap[&MBB];
  1487. if (!MInfo.reachable)
  1488. continue;
  1489. for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
  1490. SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
  1491. BBInfo &SInfo = MBBInfoMap[*SuI];
  1492. if (SInfo.addPassed(MInfo.regsLiveOut))
  1493. todo.insert(*SuI);
  1494. }
  1495. }
  1496. // Iteratively push vregsPassed to successors. This will converge to the same
  1497. // final state regardless of DenseSet iteration order.
  1498. while (!todo.empty()) {
  1499. const MachineBasicBlock *MBB = *todo.begin();
  1500. todo.erase(MBB);
  1501. BBInfo &MInfo = MBBInfoMap[MBB];
  1502. for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
  1503. SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
  1504. if (*SuI == MBB)
  1505. continue;
  1506. BBInfo &SInfo = MBBInfoMap[*SuI];
  1507. if (SInfo.addPassed(MInfo.vregsPassed))
  1508. todo.insert(*SuI);
  1509. }
  1510. }
  1511. }
  1512. // Calculate the set of virtual registers that must be passed through each basic
  1513. // block in order to satisfy the requirements of successor blocks. This is very
  1514. // similar to calcRegsPassed, only backwards.
  1515. void MachineVerifier::calcRegsRequired() {
  1516. // First push live-in regs to predecessors' vregsRequired.
  1517. SmallPtrSet<const MachineBasicBlock*, 8> todo;
  1518. for (const auto &MBB : *MF) {
  1519. BBInfo &MInfo = MBBInfoMap[&MBB];
  1520. for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(),
  1521. PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
  1522. BBInfo &PInfo = MBBInfoMap[*PrI];
  1523. if (PInfo.addRequired(MInfo.vregsLiveIn))
  1524. todo.insert(*PrI);
  1525. }
  1526. }
  1527. // Iteratively push vregsRequired to predecessors. This will converge to the
  1528. // same final state regardless of DenseSet iteration order.
  1529. while (!todo.empty()) {
  1530. const MachineBasicBlock *MBB = *todo.begin();
  1531. todo.erase(MBB);
  1532. BBInfo &MInfo = MBBInfoMap[MBB];
  1533. for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
  1534. PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
  1535. if (*PrI == MBB)
  1536. continue;
  1537. BBInfo &SInfo = MBBInfoMap[*PrI];
  1538. if (SInfo.addRequired(MInfo.vregsRequired))
  1539. todo.insert(*PrI);
  1540. }
  1541. }
  1542. }
  1543. // Check PHI instructions at the beginning of MBB. It is assumed that
  1544. // calcRegsPassed has been run so BBInfo::isLiveOut is valid.
  1545. void MachineVerifier::checkPHIOps(const MachineBasicBlock &MBB) {
  1546. BBInfo &MInfo = MBBInfoMap[&MBB];
  1547. SmallPtrSet<const MachineBasicBlock*, 8> seen;
  1548. for (const MachineInstr &Phi : MBB) {
  1549. if (!Phi.isPHI())
  1550. break;
  1551. seen.clear();
  1552. const MachineOperand &MODef = Phi.getOperand(0);
  1553. if (!MODef.isReg() || !MODef.isDef()) {
  1554. report("Expected first PHI operand to be a register def", &MODef, 0);
  1555. continue;
  1556. }
  1557. if (MODef.isTied() || MODef.isImplicit() || MODef.isInternalRead() ||
  1558. MODef.isEarlyClobber() || MODef.isDebug())
  1559. report("Unexpected flag on PHI operand", &MODef, 0);
  1560. unsigned DefReg = MODef.getReg();
  1561. if (!TargetRegisterInfo::isVirtualRegister(DefReg))
  1562. report("Expected first PHI operand to be a virtual register", &MODef, 0);
  1563. for (unsigned I = 1, E = Phi.getNumOperands(); I != E; I += 2) {
  1564. const MachineOperand &MO0 = Phi.getOperand(I);
  1565. if (!MO0.isReg()) {
  1566. report("Expected PHI operand to be a register", &MO0, I);
  1567. continue;
  1568. }
  1569. if (MO0.isImplicit() || MO0.isInternalRead() || MO0.isEarlyClobber() ||
  1570. MO0.isDebug() || MO0.isTied())
  1571. report("Unexpected flag on PHI operand", &MO0, I);
  1572. const MachineOperand &MO1 = Phi.getOperand(I + 1);
  1573. if (!MO1.isMBB()) {
  1574. report("Expected PHI operand to be a basic block", &MO1, I + 1);
  1575. continue;
  1576. }
  1577. const MachineBasicBlock &Pre = *MO1.getMBB();
  1578. if (!Pre.isSuccessor(&MBB)) {
  1579. report("PHI input is not a predecessor block", &MO1, I + 1);
  1580. continue;
  1581. }
  1582. if (MInfo.reachable) {
  1583. seen.insert(&Pre);
  1584. BBInfo &PrInfo = MBBInfoMap[&Pre];
  1585. if (!MO0.isUndef() && PrInfo.reachable &&
  1586. !PrInfo.isLiveOut(MO0.getReg()))
  1587. report("PHI operand is not live-out from predecessor", &MO0, I);
  1588. }
  1589. }
  1590. // Did we see all predecessors?
  1591. if (MInfo.reachable) {
  1592. for (MachineBasicBlock *Pred : MBB.predecessors()) {
  1593. if (!seen.count(Pred)) {
  1594. report("Missing PHI operand", &Phi);
  1595. errs() << printMBBReference(*Pred)
  1596. << " is a predecessor according to the CFG.\n";
  1597. }
  1598. }
  1599. }
  1600. }
  1601. }
  1602. void MachineVerifier::visitMachineFunctionAfter() {
  1603. calcRegsPassed();
  1604. for (const MachineBasicBlock &MBB : *MF)
  1605. checkPHIOps(MBB);
  1606. // Now check liveness info if available
  1607. calcRegsRequired();
  1608. // Check for killed virtual registers that should be live out.
  1609. for (const auto &MBB : *MF) {
  1610. BBInfo &MInfo = MBBInfoMap[&MBB];
  1611. for (RegSet::iterator
  1612. I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
  1613. ++I)
  1614. if (MInfo.regsKilled.count(*I)) {
  1615. report("Virtual register killed in block, but needed live out.", &MBB);
  1616. errs() << "Virtual register " << printReg(*I)
  1617. << " is used after the block.\n";
  1618. }
  1619. }
  1620. if (!MF->empty()) {
  1621. BBInfo &MInfo = MBBInfoMap[&MF->front()];
  1622. for (RegSet::iterator
  1623. I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
  1624. ++I) {
  1625. report("Virtual register defs don't dominate all uses.", MF);
  1626. report_context_vreg(*I);
  1627. }
  1628. }
  1629. if (LiveVars)
  1630. verifyLiveVariables();
  1631. if (LiveInts)
  1632. verifyLiveIntervals();
  1633. }
  1634. void MachineVerifier::verifyLiveVariables() {
  1635. assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
  1636. for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
  1637. unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
  1638. LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
  1639. for (const auto &MBB : *MF) {
  1640. BBInfo &MInfo = MBBInfoMap[&MBB];
  1641. // Our vregsRequired should be identical to LiveVariables' AliveBlocks
  1642. if (MInfo.vregsRequired.count(Reg)) {
  1643. if (!VI.AliveBlocks.test(MBB.getNumber())) {
  1644. report("LiveVariables: Block missing from AliveBlocks", &MBB);
  1645. errs() << "Virtual register " << printReg(Reg)
  1646. << " must be live through the block.\n";
  1647. }
  1648. } else {
  1649. if (VI.AliveBlocks.test(MBB.getNumber())) {
  1650. report("LiveVariables: Block should not be in AliveBlocks", &MBB);
  1651. errs() << "Virtual register " << printReg(Reg)
  1652. << " is not needed live through the block.\n";
  1653. }
  1654. }
  1655. }
  1656. }
  1657. }
  1658. void MachineVerifier::verifyLiveIntervals() {
  1659. assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
  1660. for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
  1661. unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
  1662. // Spilling and splitting may leave unused registers around. Skip them.
  1663. if (MRI->reg_nodbg_empty(Reg))
  1664. continue;
  1665. if (!LiveInts->hasInterval(Reg)) {
  1666. report("Missing live interval for virtual register", MF);
  1667. errs() << printReg(Reg, TRI) << " still has defs or uses\n";
  1668. continue;
  1669. }
  1670. const LiveInterval &LI = LiveInts->getInterval(Reg);
  1671. assert(Reg == LI.reg && "Invalid reg to interval mapping");
  1672. verifyLiveInterval(LI);
  1673. }
  1674. // Verify all the cached regunit intervals.
  1675. for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
  1676. if (const LiveRange *LR = LiveInts->getCachedRegUnit(i))
  1677. verifyLiveRange(*LR, i);
  1678. }
  1679. void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
  1680. const VNInfo *VNI, unsigned Reg,
  1681. LaneBitmask LaneMask) {
  1682. if (VNI->isUnused())
  1683. return;
  1684. const VNInfo *DefVNI = LR.getVNInfoAt(VNI->def);
  1685. if (!DefVNI) {
  1686. report("Value not live at VNInfo def and not marked unused", MF);
  1687. report_context(LR, Reg, LaneMask);
  1688. report_context(*VNI);
  1689. return;
  1690. }
  1691. if (DefVNI != VNI) {
  1692. report("Live segment at def has different VNInfo", MF);
  1693. report_context(LR, Reg, LaneMask);
  1694. report_context(*VNI);
  1695. return;
  1696. }
  1697. const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
  1698. if (!MBB) {
  1699. report("Invalid VNInfo definition index", MF);
  1700. report_context(LR, Reg, LaneMask);
  1701. report_context(*VNI);
  1702. return;
  1703. }
  1704. if (VNI->isPHIDef()) {
  1705. if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
  1706. report("PHIDef VNInfo is not defined at MBB start", MBB);
  1707. report_context(LR, Reg, LaneMask);
  1708. report_context(*VNI);
  1709. }
  1710. return;
  1711. }
  1712. // Non-PHI def.
  1713. const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
  1714. if (!MI) {
  1715. report("No instruction at VNInfo def index", MBB);
  1716. report_context(LR, Reg, LaneMask);
  1717. report_context(*VNI);
  1718. return;
  1719. }
  1720. if (Reg != 0) {
  1721. bool hasDef = false;
  1722. bool isEarlyClobber = false;
  1723. for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
  1724. if (!MOI->isReg() || !MOI->isDef())
  1725. continue;
  1726. if (TargetRegisterInfo::isVirtualRegister(Reg)) {
  1727. if (MOI->getReg() != Reg)
  1728. continue;
  1729. } else {
  1730. if (!TargetRegisterInfo::isPhysicalRegister(MOI->getReg()) ||
  1731. !TRI->hasRegUnit(MOI->getReg(), Reg))
  1732. continue;
  1733. }
  1734. if (LaneMask.any() &&
  1735. (TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())
  1736. continue;
  1737. hasDef = true;
  1738. if (MOI->isEarlyClobber())
  1739. isEarlyClobber = true;
  1740. }
  1741. if (!hasDef) {
  1742. report("Defining instruction does not modify register", MI);
  1743. report_context(LR, Reg, LaneMask);
  1744. report_context(*VNI);
  1745. }
  1746. // Early clobber defs begin at USE slots, but other defs must begin at
  1747. // DEF slots.
  1748. if (isEarlyClobber) {
  1749. if (!VNI->def.isEarlyClobber()) {
  1750. report("Early clobber def must be at an early-clobber slot", MBB);
  1751. report_context(LR, Reg, LaneMask);
  1752. report_context(*VNI);
  1753. }
  1754. } else if (!VNI->def.isRegister()) {
  1755. report("Non-PHI, non-early clobber def must be at a register slot", MBB);
  1756. report_context(LR, Reg, LaneMask);
  1757. report_context(*VNI);
  1758. }
  1759. }
  1760. }
  1761. void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
  1762. const LiveRange::const_iterator I,
  1763. unsigned Reg, LaneBitmask LaneMask)
  1764. {
  1765. const LiveRange::Segment &S = *I;
  1766. const VNInfo *VNI = S.valno;
  1767. assert(VNI && "Live segment has no valno");
  1768. if (VNI->id >= LR.getNumValNums() || VNI != LR.getValNumInfo(VNI->id)) {
  1769. report("Foreign valno in live segment", MF);
  1770. report_context(LR, Reg, LaneMask);
  1771. report_context(S);
  1772. report_context(*VNI);
  1773. }
  1774. if (VNI->isUnused()) {
  1775. report("Live segment valno is marked unused", MF);
  1776. report_context(LR, Reg, LaneMask);
  1777. report_context(S);
  1778. }
  1779. const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(S.start);
  1780. if (!MBB) {
  1781. report("Bad start of live segment, no basic block", MF);
  1782. report_context(LR, Reg, LaneMask);
  1783. report_context(S);
  1784. return;
  1785. }
  1786. SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
  1787. if (S.start != MBBStartIdx && S.start != VNI->def) {
  1788. report("Live segment must begin at MBB entry or valno def", MBB);
  1789. report_context(LR, Reg, LaneMask);
  1790. report_context(S);
  1791. }
  1792. const MachineBasicBlock *EndMBB =
  1793. LiveInts->getMBBFromIndex(S.end.getPrevSlot());
  1794. if (!EndMBB) {
  1795. report("Bad end of live segment, no basic block", MF);
  1796. report_context(LR, Reg, LaneMask);
  1797. report_context(S);
  1798. return;
  1799. }
  1800. // No more checks for live-out segments.
  1801. if (S.end == LiveInts->getMBBEndIdx(EndMBB))
  1802. return;
  1803. // RegUnit intervals are allowed dead phis.
  1804. if (!TargetRegisterInfo::isVirtualRegister(Reg) && VNI->isPHIDef() &&
  1805. S.start == VNI->def && S.end == VNI->def.getDeadSlot())
  1806. return;
  1807. // The live segment is ending inside EndMBB
  1808. const MachineInstr *MI =
  1809. LiveInts->getInstructionFromIndex(S.end.getPrevSlot());
  1810. if (!MI) {
  1811. report("Live segment doesn't end at a valid instruction", EndMBB);
  1812. report_context(LR, Reg, LaneMask);
  1813. report_context(S);
  1814. return;
  1815. }
  1816. // The block slot must refer to a basic block boundary.
  1817. if (S.end.isBlock()) {
  1818. report("Live segment ends at B slot of an instruction", EndMBB);
  1819. report_context(LR, Reg, LaneMask);
  1820. report_context(S);
  1821. }
  1822. if (S.end.isDead()) {
  1823. // Segment ends on the dead slot.
  1824. // That means there must be a dead def.
  1825. if (!SlotIndex::isSameInstr(S.start, S.end)) {
  1826. report("Live segment ending at dead slot spans instructions", EndMBB);
  1827. report_context(LR, Reg, LaneMask);
  1828. report_context(S);
  1829. }
  1830. }
  1831. // A live segment can only end at an early-clobber slot if it is being
  1832. // redefined by an early-clobber def.
  1833. if (S.end.isEarlyClobber()) {
  1834. if (I+1 == LR.end() || (I+1)->start != S.end) {
  1835. report("Live segment ending at early clobber slot must be "
  1836. "redefined by an EC def in the same instruction", EndMBB);
  1837. report_context(LR, Reg, LaneMask);
  1838. report_context(S);
  1839. }
  1840. }
  1841. // The following checks only apply to virtual registers. Physreg liveness
  1842. // is too weird to check.
  1843. if (TargetRegisterInfo::isVirtualRegister(Reg)) {
  1844. // A live segment can end with either a redefinition, a kill flag on a
  1845. // use, or a dead flag on a def.
  1846. bool hasRead = false;
  1847. bool hasSubRegDef = false;
  1848. bool hasDeadDef = false;
  1849. for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
  1850. if (!MOI->isReg() || MOI->getReg() != Reg)
  1851. continue;
  1852. unsigned Sub = MOI->getSubReg();
  1853. LaneBitmask SLM = Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub)
  1854. : LaneBitmask::getAll();
  1855. if (MOI->isDef()) {
  1856. if (Sub != 0) {
  1857. hasSubRegDef = true;
  1858. // An operand %0:sub0 reads %0:sub1..n. Invert the lane
  1859. // mask for subregister defs. Read-undef defs will be handled by
  1860. // readsReg below.
  1861. SLM = ~SLM;
  1862. }
  1863. if (MOI->isDead())
  1864. hasDeadDef = true;
  1865. }
  1866. if (LaneMask.any() && (LaneMask & SLM).none())
  1867. continue;
  1868. if (MOI->readsReg())
  1869. hasRead = true;
  1870. }
  1871. if (S.end.isDead()) {
  1872. // Make sure that the corresponding machine operand for a "dead" live
  1873. // range has the dead flag. We cannot perform this check for subregister
  1874. // liveranges as partially dead values are allowed.
  1875. if (LaneMask.none() && !hasDeadDef) {
  1876. report("Instruction ending live segment on dead slot has no dead flag",
  1877. MI);
  1878. report_context(LR, Reg, LaneMask);
  1879. report_context(S);
  1880. }
  1881. } else {
  1882. if (!hasRead) {
  1883. // When tracking subregister liveness, the main range must start new
  1884. // values on partial register writes, even if there is no read.
  1885. if (!MRI->shouldTrackSubRegLiveness(Reg) || LaneMask.any() ||
  1886. !hasSubRegDef) {
  1887. report("Instruction ending live segment doesn't read the register",
  1888. MI);
  1889. report_context(LR, Reg, LaneMask);
  1890. report_context(S);
  1891. }
  1892. }
  1893. }
  1894. }
  1895. // Now check all the basic blocks in this live segment.
  1896. MachineFunction::const_iterator MFI = MBB->getIterator();
  1897. // Is this live segment the beginning of a non-PHIDef VN?
  1898. if (S.start == VNI->def && !VNI->isPHIDef()) {
  1899. // Not live-in to any blocks.
  1900. if (MBB == EndMBB)
  1901. return;
  1902. // Skip this block.
  1903. ++MFI;
  1904. }
  1905. while (true) {
  1906. assert(LiveInts->isLiveInToMBB(LR, &*MFI));
  1907. // We don't know how to track physregs into a landing pad.
  1908. if (!TargetRegisterInfo::isVirtualRegister(Reg) &&
  1909. MFI->isEHPad()) {
  1910. if (&*MFI == EndMBB)
  1911. break;
  1912. ++MFI;
  1913. continue;
  1914. }
  1915. // Is VNI a PHI-def in the current block?
  1916. bool IsPHI = VNI->isPHIDef() &&
  1917. VNI->def == LiveInts->getMBBStartIdx(&*MFI);
  1918. // Check that VNI is live-out of all predecessors.
  1919. for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(),
  1920. PE = MFI->pred_end(); PI != PE; ++PI) {
  1921. SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI);
  1922. const VNInfo *PVNI = LR.getVNInfoBefore(PEnd);
  1923. // All predecessors must have a live-out value. However for a phi
  1924. // instruction with subregister intervals
  1925. // only one of the subregisters (not necessarily the current one) needs to
  1926. // be defined.
  1927. if (!PVNI && (LaneMask.none() || !IsPHI) ) {
  1928. report("Register not marked live out of predecessor", *PI);
  1929. report_context(LR, Reg, LaneMask);
  1930. report_context(*VNI);
  1931. errs() << " live into " << printMBBReference(*MFI) << '@'
  1932. << LiveInts->getMBBStartIdx(&*MFI) << ", not live before "
  1933. << PEnd << '\n';
  1934. continue;
  1935. }
  1936. // Only PHI-defs can take different predecessor values.
  1937. if (!IsPHI && PVNI != VNI) {
  1938. report("Different value live out of predecessor", *PI);
  1939. report_context(LR, Reg, LaneMask);
  1940. errs() << "Valno #" << PVNI->id << " live out of "
  1941. << printMBBReference(*(*PI)) << '@' << PEnd << "\nValno #"
  1942. << VNI->id << " live into " << printMBBReference(*MFI) << '@'
  1943. << LiveInts->getMBBStartIdx(&*MFI) << '\n';
  1944. }
  1945. }
  1946. if (&*MFI == EndMBB)
  1947. break;
  1948. ++MFI;
  1949. }
  1950. }
  1951. void MachineVerifier::verifyLiveRange(const LiveRange &LR, unsigned Reg,
  1952. LaneBitmask LaneMask) {
  1953. for (const VNInfo *VNI : LR.valnos)
  1954. verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
  1955. for (LiveRange::const_iterator I = LR.begin(), E = LR.end(); I != E; ++I)
  1956. verifyLiveRangeSegment(LR, I, Reg, LaneMask);
  1957. }
  1958. void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
  1959. unsigned Reg = LI.reg;
  1960. assert(TargetRegisterInfo::isVirtualRegister(Reg));
  1961. verifyLiveRange(LI, Reg);
  1962. LaneBitmask Mask;
  1963. LaneBitmask MaxMask = MRI->getMaxLaneMaskForVReg(Reg);
  1964. for (const LiveInterval::SubRange &SR : LI.subranges()) {
  1965. if ((Mask & SR.LaneMask).any()) {
  1966. report("Lane masks of sub ranges overlap in live interval", MF);
  1967. report_context(LI);
  1968. }
  1969. if ((SR.LaneMask & ~MaxMask).any()) {
  1970. report("Subrange lanemask is invalid", MF);
  1971. report_context(LI);
  1972. }
  1973. if (SR.empty()) {
  1974. report("Subrange must not be empty", MF);
  1975. report_context(SR, LI.reg, SR.LaneMask);
  1976. }
  1977. Mask |= SR.LaneMask;
  1978. verifyLiveRange(SR, LI.reg, SR.LaneMask);
  1979. if (!LI.covers(SR)) {
  1980. report("A Subrange is not covered by the main range", MF);
  1981. report_context(LI);
  1982. }
  1983. }
  1984. // Check the LI only has one connected component.
  1985. ConnectedVNInfoEqClasses ConEQ(*LiveInts);
  1986. unsigned NumComp = ConEQ.Classify(LI);
  1987. if (NumComp > 1) {
  1988. report("Multiple connected components in live interval", MF);
  1989. report_context(LI);
  1990. for (unsigned comp = 0; comp != NumComp; ++comp) {
  1991. errs() << comp << ": valnos";
  1992. for (LiveInterval::const_vni_iterator I = LI.vni_begin(),
  1993. E = LI.vni_end(); I!=E; ++I)
  1994. if (comp == ConEQ.getEqClass(*I))
  1995. errs() << ' ' << (*I)->id;
  1996. errs() << '\n';
  1997. }
  1998. }
  1999. }
  2000. namespace {
  2001. // FrameSetup and FrameDestroy can have zero adjustment, so using a single
  2002. // integer, we can't tell whether it is a FrameSetup or FrameDestroy if the
  2003. // value is zero.
  2004. // We use a bool plus an integer to capture the stack state.
  2005. struct StackStateOfBB {
  2006. StackStateOfBB() = default;
  2007. StackStateOfBB(int EntryVal, int ExitVal, bool EntrySetup, bool ExitSetup) :
  2008. EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup),
  2009. ExitIsSetup(ExitSetup) {}
  2010. // Can be negative, which means we are setting up a frame.
  2011. int EntryValue = 0;
  2012. int ExitValue = 0;
  2013. bool EntryIsSetup = false;
  2014. bool ExitIsSetup = false;
  2015. };
  2016. } // end anonymous namespace
  2017. /// Make sure on every path through the CFG, a FrameSetup <n> is always followed
  2018. /// by a FrameDestroy <n>, stack adjustments are identical on all
  2019. /// CFG edges to a merge point, and frame is destroyed at end of a return block.
  2020. void MachineVerifier::verifyStackFrame() {
  2021. unsigned FrameSetupOpcode = TII->getCallFrameSetupOpcode();
  2022. unsigned FrameDestroyOpcode = TII->getCallFrameDestroyOpcode();
  2023. if (FrameSetupOpcode == ~0u && FrameDestroyOpcode == ~0u)
  2024. return;
  2025. SmallVector<StackStateOfBB, 8> SPState;
  2026. SPState.resize(MF->getNumBlockIDs());
  2027. df_iterator_default_set<const MachineBasicBlock*> Reachable;
  2028. // Visit the MBBs in DFS order.
  2029. for (df_ext_iterator<const MachineFunction *,
  2030. df_iterator_default_set<const MachineBasicBlock *>>
  2031. DFI = df_ext_begin(MF, Reachable), DFE = df_ext_end(MF, Reachable);
  2032. DFI != DFE; ++DFI) {
  2033. const MachineBasicBlock *MBB = *DFI;
  2034. StackStateOfBB BBState;
  2035. // Check the exit state of the DFS stack predecessor.
  2036. if (DFI.getPathLength() >= 2) {
  2037. const MachineBasicBlock *StackPred = DFI.getPath(DFI.getPathLength() - 2);
  2038. assert(Reachable.count(StackPred) &&
  2039. "DFS stack predecessor is already visited.\n");
  2040. BBState.EntryValue = SPState[StackPred->getNumber()].ExitValue;
  2041. BBState.EntryIsSetup = SPState[StackPred->getNumber()].ExitIsSetup;
  2042. BBState.ExitValue = BBState.EntryValue;
  2043. BBState.ExitIsSetup = BBState.EntryIsSetup;
  2044. }
  2045. // Update stack state by checking contents of MBB.
  2046. for (const auto &I : *MBB) {
  2047. if (I.getOpcode() == FrameSetupOpcode) {
  2048. if (BBState.ExitIsSetup)
  2049. report("FrameSetup is after another FrameSetup", &I);
  2050. BBState.ExitValue -= TII->getFrameTotalSize(I);
  2051. BBState.ExitIsSetup = true;
  2052. }
  2053. if (I.getOpcode() == FrameDestroyOpcode) {
  2054. int Size = TII->getFrameTotalSize(I);
  2055. if (!BBState.ExitIsSetup)
  2056. report("FrameDestroy is not after a FrameSetup", &I);
  2057. int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
  2058. BBState.ExitValue;
  2059. if (BBState.ExitIsSetup && AbsSPAdj != Size) {
  2060. report("FrameDestroy <n> is after FrameSetup <m>", &I);
  2061. errs() << "FrameDestroy <" << Size << "> is after FrameSetup <"
  2062. << AbsSPAdj << ">.\n";
  2063. }
  2064. BBState.ExitValue += Size;
  2065. BBState.ExitIsSetup = false;
  2066. }
  2067. }
  2068. SPState[MBB->getNumber()] = BBState;
  2069. // Make sure the exit state of any predecessor is consistent with the entry
  2070. // state.
  2071. for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(),
  2072. E = MBB->pred_end(); I != E; ++I) {
  2073. if (Reachable.count(*I) &&
  2074. (SPState[(*I)->getNumber()].ExitValue != BBState.EntryValue ||
  2075. SPState[(*I)->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
  2076. report("The exit stack state of a predecessor is inconsistent.", MBB);
  2077. errs() << "Predecessor " << printMBBReference(*(*I))
  2078. << " has exit state (" << SPState[(*I)->getNumber()].ExitValue
  2079. << ", " << SPState[(*I)->getNumber()].ExitIsSetup << "), while "
  2080. << printMBBReference(*MBB) << " has entry state ("
  2081. << BBState.EntryValue << ", " << BBState.EntryIsSetup << ").\n";
  2082. }
  2083. }
  2084. // Make sure the entry state of any successor is consistent with the exit
  2085. // state.
  2086. for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
  2087. E = MBB->succ_end(); I != E; ++I) {
  2088. if (Reachable.count(*I) &&
  2089. (SPState[(*I)->getNumber()].EntryValue != BBState.ExitValue ||
  2090. SPState[(*I)->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
  2091. report("The entry stack state of a successor is inconsistent.", MBB);
  2092. errs() << "Successor " << printMBBReference(*(*I))
  2093. << " has entry state (" << SPState[(*I)->getNumber()].EntryValue
  2094. << ", " << SPState[(*I)->getNumber()].EntryIsSetup << "), while "
  2095. << printMBBReference(*MBB) << " has exit state ("
  2096. << BBState.ExitValue << ", " << BBState.ExitIsSetup << ").\n";
  2097. }
  2098. }
  2099. // Make sure a basic block with return ends with zero stack adjustment.
  2100. if (!MBB->empty() && MBB->back().isReturn()) {
  2101. if (BBState.ExitIsSetup)
  2102. report("A return block ends with a FrameSetup.", MBB);
  2103. if (BBState.ExitValue)
  2104. report("A return block ends with a nonzero stack adjustment.", MBB);
  2105. }
  2106. }
  2107. }