 Craig Topper
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99a4c92625
[Subtarget] Merge ProcSched and ProcDesc arrays in MCSubtargetInfo into a single array.
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6 years ago |
|
Craig Topper
|
8bc601fd43
[Subtarget] Create a separate SubtargetSubtargetKV struct for ProcDesc to remove fields from the stack tables that aren't needed for CPUs
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6 years ago |
 Andrea Di Biagio
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ab6a729325
[AsmPrinter] Remove hidden flag -print-schedule.
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6 years ago |
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Andrea Di Biagio
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6b6a90fb85
[MC][X86] Correctly model additional operand latency caused by transfer delays from the integer to the floating point unit.
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6 years ago |
 Chandler Carruth
|
6b547686c5
Update the file headers across all of the LLVM projects in the monorepo
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6 years ago |
 Sanjay Patel
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863443f97f
[CodeGen] assume max/default throughput for unspecified instructions
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7 years ago |
|
Andrea Di Biagio
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ae5fb65ace
[MCSchedule] Add the ability to compute the latency and throughput information for MCInst.
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7 years ago |
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Andrea Di Biagio
|
b5e23d13a5
[MC] Moved all the remaining logic that computed instruction latency and reciprocal throughput from TargetSchedModel to MCSchedModel.
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7 years ago |
|
Sanjay Patel
|
e599ceafb8
[TargetSchedule] shrink interface for init(); NFCI
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7 years ago |
|
Sanjay Patel
|
a816f42e4d
[CodeGen] allow printing of zero latency in sched comments
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7 years ago |
|
Chandler Carruth
|
fd5a8723ce
Introduce the "retpoline" x86 mitigation technique for variant #2 of the speculative execution vulnerabilities disclosed today, specifically identified by CVE-2017-5715, "Branch Target Injection", and is one of the two halves to Spectre..
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7 years ago |
 Matthias Braun
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5d9e10f443
AArch64: Fix emergency spillslot being out of reach for large callframes
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7 years ago |
|
Matthias Braun
|
682df3f9a2
Revert "AArch64: Fix emergency spillslot being out of reach for large callframes"
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7 years ago |
|
Matthias Braun
|
11adaf9955
AArch64: Fix emergency spillslot being out of reach for large callframes
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7 years ago |
 David Blaikie
|
e3a9b4ce3a
Fix a bunch more layering of CodeGen headers that are in Target
|
7 years ago |
|
David Blaikie
|
48319238e4
Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering
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7 years ago |
 Marina Yatsina
|
b76f989d6b
Add logic to greedy reg alloc to avoid bad eviction chains
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7 years ago |
 Andrew V. Tischenko
|
052dd78cb3
Support itineraries in TargetSubtargetInfo::getSchedInfoStr - Now if the given instr does not have sched model then we try to calculate the latecy/throughput with help of itineraries.
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8 years ago |
 Eugene Zelenko
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810d1a08bd
[Target] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
|
8 years ago |
|
Chandler Carruth
|
e3e43d9d57
Sort the remaining #include lines in include/... and lib/....
|
8 years ago |
|
Andrew V. Tischenko
|
3796561c6e
This patch closes PR#32216: Better testing of schedule model instruction latencies/throughputs.
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8 years ago |
|
Matthias Braun
|
e436226fa3
TargetSubtargetInfo: Move implementation to lib/CodeGen; NFC
|
8 years ago |
