 Craig Topper
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ae55bf36c6
[SelectionDAGBuilder] Teach gather/scatter getUniformBase to look through vector zeroinitializer indices in addition to scalar zeroes.
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6 years ago |
 Cullen Rhodes
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2d85110820
[SelectionDAG] Extend base addressing modes supported by MGATHER/MSCATTER
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6 years ago |
 Guillaume Chatelet
|
0845c69be9
[LLVM][Alignment] Introduce Alignment Type
|
6 years ago |
 Bill Wendling
|
30c0b52ad3
Emit diagnostic if an inline asm constraint requires an immediate
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6 years ago |
 Daniel Sanders
|
c7a3c5c5d1
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC
|
6 years ago |
 Christudasan Devadasan
|
1df2388495
Added address-space mangling for stack related intrinsics
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6 years ago |
 Oliver Stannard
|
ca15d41cf2
[IPRA][ARM] Make use of the "returned" parameter attribute
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6 years ago |
 Matt Arsenault
|
7b0d5fb54f
DAG: Handle dbg_value for arguments split into multiple subregs
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6 years ago |
 Evgeniy Stepanov
|
4fca50d47d
Basic codegen for MTE stack tagging.
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6 years ago |
 Tim Northover
|
2a2e351b9d
OpaquePtr: use byval accessor instead of inspecting pointer type. NFC.
|
6 years ago |
|
Tim Northover
|
39dc171242
OpaquePtr: add Type parameter to Loads analysis API.
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6 years ago |
 Francis Visoiu Mistrih
|
0eaa652ef0
[CodeGen] Make branch funnels pass the machine verifier
|
6 years ago |
 James Molloy
|
755e158b41
[SelectionDAG] Propagate alias metadata to target intrinsic nodes
|
6 years ago |
 Benjamin Kramer
|
0ca3c92d55
[SelectionDAG] Do minnum->minimum at legalization time instead of building time
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6 years ago |
|
Matt Arsenault
|
a2b05bc24d
CodeGen: Introduce a class for registers
|
6 years ago |
|
Matt Arsenault
|
5b56cc85b0
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
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6 years ago |
 Sander de Smalen
|
a813b38069
Change semantics of fadd/fmul vector reductions.
|
6 years ago |
|
Francis Visoiu Mistrih
|
c030038e73
[FastISel] Skip creating unnecessary vregs for arguments
|
6 years ago |
 Amara Emerson
|
27a3c6c8d9
Factor out SelectionDAG's switch analysis and lowering into a separate component.
|
6 years ago |
 Ulrich Weigand
|
ef54162998
Allow target to handle STRICT floating-point nodes
|
6 years ago |
|
Tim Northover
|
ee9bd50401
IR: make getParamByValType Just Work. NFC.
|
6 years ago |
 Johannes Doerfert
|
ba95ced434
[SelectionDAG][FIX] Allow "returned" arguments to be bit-casted
|
6 years ago |
|
Tim Northover
|
a8aa168ce3
Reapply: IR: add optional type to 'byval' function parameters
|
6 years ago |
|
Tim Northover
|
3d26f10b85
Revert "IR: add optional type to 'byval' function parameters"
|
6 years ago |
|
Tim Northover
|
aef2b1ac1a
IR: add optional type to 'byval' function parameters
|
6 years ago |
 Adhemerval Zanella
|
29f026d977
[CodeGen] Add lrint/llrint builtins
|
6 years ago |
 Alexander Timofeev
|
d224ecc383
[AMDGPU] Divergence driven ISel. Assign register class for cross block values according to the divergence.
|
6 years ago |
 Peter Collingbourne
|
d7a83f9517
Revert r361644, "[AMDGPU] Divergence driven ISel. Assign register class for cross block values according to the divergence."
|
6 years ago |
|
Alexander Timofeev
|
6a29119c95
[AMDGPU] Divergence driven ISel. Assign register class for cross block values according to the divergence.
|
6 years ago |
|
Tim Northover
|
14ed588ce0
CodeGen: factor out swifterror value tracking.
|
6 years ago |
