[CodeGen] Always use `printReg` to print registers in both MIR and debug

output

As part of the unification of the debug format and the MIR format,
always use `printReg` to print all kinds of registers.

Updated the tests using '_' instead of '%noreg' until we decide which
one we want to be the default one.

Differential Revision: https://reviews.llvm.org/D40421

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319445 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/AggressiveAntiDepBreaker.cpp

@@ -141,7 +141,7 @@ AggressiveAntiDepBreaker::AggressiveAntiDepBreaker(
 
   DEBUG(dbgs() << "AntiDep Critical-Path Registers:");
   DEBUG(for (unsigned r : CriticalPathSet.set_bits())
-          dbgs() << " " << TRI->getName(r));
+          dbgs() << " " << printReg(r, TRI));
   DEBUG(dbgs() << '\n');
 }
 
@@ -216,7 +216,7 @@ void AggressiveAntiDepBreaker::Observe(MachineInstr &MI, unsigned Count,
     // schedule region).
     if (State->IsLive(Reg)) {
       DEBUG(if (State->GetGroup(Reg) != 0)
-              dbgs() << " " << TRI->getName(Reg) << "=g" <<
+              dbgs() << " " << printReg(Reg, TRI) << "=g" <<
                 State->GetGroup(Reg) << "->g0(region live-out)");
       State->UnionGroups(Reg, 0);
     } else if ((DefIndices[Reg] < InsertPosIndex)
@@ -323,7 +323,7 @@ void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx,
     RegRefs.erase(Reg);
     State->LeaveGroup(Reg);
     DEBUG(if (header) {
-        dbgs() << header << TRI->getName(Reg); header = nullptr; });
+        dbgs() << header << printReg(Reg, TRI); header = nullptr; });
     DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << tag);
     // Repeat for subregisters. Note that we only do this if the superregister
     // was not live because otherwise, regardless whether we have an explicit
@@ -337,8 +337,8 @@ void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx,
         RegRefs.erase(SubregReg);
         State->LeaveGroup(SubregReg);
         DEBUG(if (header) {
-            dbgs() << header << TRI->getName(Reg); header = nullptr; });
-        DEBUG(dbgs() << " " << TRI->getName(SubregReg) << "->g" <<
+            dbgs() << header << printReg(Reg, TRI); header = nullptr; });
+        DEBUG(dbgs() << " " << printReg(SubregReg, TRI) << "->g" <<
               State->GetGroup(SubregReg) << tag);
       }
     }
@@ -374,7 +374,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction(
     unsigned Reg = MO.getReg();
     if (Reg == 0) continue;
 
-    DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" << State->GetGroup(Reg));
+    DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg));
 
     // If MI's defs have a special allocation requirement, don't allow
     // any def registers to be changed. Also assume all registers
@@ -393,8 +393,8 @@ void AggressiveAntiDepBreaker::PrescanInstruction(
       unsigned AliasReg = *AI;
       if (State->IsLive(AliasReg)) {
         State->UnionGroups(Reg, AliasReg);
-        DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via " <<
-              TRI->getName(AliasReg) << ")");
+        DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via "
+                     << printReg(AliasReg, TRI) << ")");
       }
     }
 
@@ -469,8 +469,7 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr &MI,
     unsigned Reg = MO.getReg();
     if (Reg == 0) continue;
 
-    DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" <<
-          State->GetGroup(Reg));
+    DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg));
 
     // It wasn't previously live but now it is, this is a kill. Forget
     // the previous live-range information and start a new live-range
@@ -505,10 +504,10 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr &MI,
       if (Reg == 0) continue;
 
       if (FirstReg != 0) {
-        DEBUG(dbgs() << "=" << TRI->getName(Reg));
+        DEBUG(dbgs() << "=" << printReg(Reg, TRI));
         State->UnionGroups(FirstReg, Reg);
       } else {
-        DEBUG(dbgs() << " " << TRI->getName(Reg));
+        DEBUG(dbgs() << " " << printReg(Reg, TRI));
         FirstReg = Reg;
       }
     }
@@ -574,7 +573,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
 
     // If Reg has any references, then collect possible rename regs
     if (RegRefs.count(Reg) > 0) {
-      DEBUG(dbgs() << "\t\t" << TRI->getName(Reg) << ":");
+      DEBUG(dbgs() << "\t\t" << printReg(Reg, TRI) << ":");
 
       BitVector &BV = RenameRegisterMap[Reg];
       assert(BV.empty());
@@ -583,7 +582,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
       DEBUG({
         dbgs() << " ::";
         for (unsigned r : BV.set_bits())
-          dbgs() << " " << TRI->getName(r);
+          dbgs() << " " << printReg(r, TRI);
         dbgs() << "\n";
       });
     }
@@ -608,8 +607,8 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
     if (renamecnt++ % DebugDiv != DebugMod)
       return false;
 
-    dbgs() << "*** Performing rename " << TRI->getName(SuperReg) <<
-      " for debug ***\n";
+    dbgs() << "*** Performing rename " << printReg(SuperReg, TRI)
+           << " for debug ***\n";
   }
 #endif
 
@@ -646,7 +645,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
     // Don't replace a register with itself.
     if (NewSuperReg == SuperReg) continue;
 
-    DEBUG(dbgs() << " [" << TRI->getName(NewSuperReg) << ':');
+    DEBUG(dbgs() << " [" << printReg(NewSuperReg, TRI) << ':');
     RenameMap.clear();
 
     // For each referenced group register (which must be a SuperReg or
@@ -663,7 +662,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
           NewReg = TRI->getSubReg(NewSuperReg, NewSubRegIdx);
       }
 
-      DEBUG(dbgs() << " " << TRI->getName(NewReg));
+      DEBUG(dbgs() << " " << printReg(NewReg, TRI));
 
       // Check if Reg can be renamed to NewReg.
       if (!RenameRegisterMap[Reg].test(NewReg)) {
@@ -684,7 +683,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
           unsigned AliasReg = *AI;
           if (State->IsLive(AliasReg) ||
               (KillIndices[Reg] > DefIndices[AliasReg])) {
-            DEBUG(dbgs() << "(alias " << TRI->getName(AliasReg) << " live)");
+            DEBUG(dbgs() << "(alias " << printReg(AliasReg, TRI) << " live)");
             found = true;
             break;
           }
@@ -793,7 +792,7 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
   DEBUG(dbgs() << "Available regs:");
   for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
     if (!State->IsLive(Reg))
-      DEBUG(dbgs() << " " << TRI->getName(Reg));
+      DEBUG(dbgs() << " " << printReg(Reg, TRI));
   }
   DEBUG(dbgs() << '\n');
 #endif
@@ -849,7 +848,7 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
             (Edge->getKind() != SDep::Output)) continue;
 
         unsigned AntiDepReg = Edge->getReg();
-        DEBUG(dbgs() << "\tAntidep reg: " << TRI->getName(AntiDepReg));
+        DEBUG(dbgs() << "\tAntidep reg: " << printReg(AntiDepReg, TRI));
         assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
 
         if (!MRI.isAllocatable(AntiDepReg)) {
@@ -952,7 +951,7 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
         std::map<unsigned, unsigned> RenameMap;
         if (FindSuitableFreeRegisters(GroupIndex, RenameOrder, RenameMap)) {
           DEBUG(dbgs() << "\tBreaking anti-dependence edge on "
-                << TRI->getName(AntiDepReg) << ":");
+                       << printReg(AntiDepReg, TRI) << ":");
 
           // Handle each group register...
           for (std::map<unsigned, unsigned>::iterator
@@ -960,9 +959,9 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
             unsigned CurrReg = S->first;
             unsigned NewReg = S->second;
 
-            DEBUG(dbgs() << " " << TRI->getName(CurrReg) << "->" <<
-                  TRI->getName(NewReg) << "(" <<
-                  RegRefs.count(CurrReg) << " refs)");
+            DEBUG(dbgs() << " " << printReg(CurrReg, TRI) << "->"
+                         << printReg(NewReg, TRI) << "("
+                         << RegRefs.count(CurrReg) << " refs)");
 
             // Update the references to the old register CurrReg to
             // refer to the new register NewReg.

lib/CodeGen/CriticalAntiDepBreaker.cpp

@@ -466,7 +466,7 @@ BreakAntiDependencies(const std::vector<SUnit> &SUnits,
     DEBUG(dbgs() << "Available regs:");
     for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
       if (KillIndices[Reg] == ~0u)
-        DEBUG(dbgs() << " " << TRI->getName(Reg));
+        DEBUG(dbgs() << " " << printReg(Reg, TRI));
     }
     DEBUG(dbgs() << '\n');
   }
@@ -646,9 +646,9 @@ BreakAntiDependencies(const std::vector<SUnit> &SUnits,
                                                      LastNewReg[AntiDepReg],
                                                      RC, ForbidRegs)) {
         DEBUG(dbgs() << "Breaking anti-dependence edge on "
-              << TRI->getName(AntiDepReg)
-              << " with " << RegRefs.count(AntiDepReg) << " references"
-              << " using " << TRI->getName(NewReg) << "!\n");
+                     << printReg(AntiDepReg, TRI) << " with "
+                     << RegRefs.count(AntiDepReg) << " references"
+                     << " using " << printReg(NewReg, TRI) << "!\n");
 
         // Update the references to the old register to refer to the new
         // register.

lib/CodeGen/ExecutionDepsFix.cpp

@@ -394,7 +394,7 @@ void ExecutionDepsFix::processDefs(MachineInstr *MI, bool breakDependency,
       continue;
     for (int rx : regIndices(MO.getReg())) {
       // This instruction explicitly defines rx.
-      DEBUG(dbgs() << TRI->getName(RC->getRegister(rx)) << ":\t" << CurInstr
+      DEBUG(dbgs() << printReg(RC->getRegister(rx), TRI) << ":\t" << CurInstr
                    << '\t' << *MI);
 
       if (breakDependency) {

lib/CodeGen/MIRPrinter.cpp

@@ -192,23 +192,10 @@ template <> struct BlockScalarTraits<Module> {
 } // end namespace yaml
 } // end namespace llvm
 
-static void printRegMIR(unsigned Reg, raw_ostream &OS,
-                        const TargetRegisterInfo *TRI) {
-  // TODO: Print Stack Slots.
-  if (!Reg)
-    OS << '_';
-  else if (TargetRegisterInfo::isVirtualRegister(Reg))
-    OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
-  else if (Reg < TRI->getNumRegs())
-    OS << '%' << StringRef(TRI->getName(Reg)).lower();
-  else
-    llvm_unreachable("Can't print this kind of register yet");
-}
-
 static void printRegMIR(unsigned Reg, yaml::StringValue &Dest,
                         const TargetRegisterInfo *TRI) {
   raw_string_ostream OS(Dest.Value);
-  printRegMIR(Reg, OS, TRI);
+  OS << printReg(Reg, TRI);
 }
 
 void MIRPrinter::print(const MachineFunction &MF) {
@@ -262,7 +249,7 @@ static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS,
     if (RegMask[I / 32] & (1u << (I % 32))) {
       if (IsRegInRegMaskFound)
         OS << ',';
-      printRegMIR(I, OS, TRI);
+      OS << printReg(I, TRI);
       IsRegInRegMaskFound = true;
     }
   }
@@ -648,7 +635,7 @@ void MIPrinter::print(const MachineBasicBlock &MBB) {
       if (!First)
         OS << ", ";
       First = false;
-      printRegMIR(LI.PhysReg, OS, &TRI);
+      OS << printReg(LI.PhysReg, &TRI);
       if (!LI.LaneMask.all())
         OS << ":0x" << PrintLaneMask(LI.LaneMask);
     }
@@ -949,7 +936,7 @@ void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
       OS << "early-clobber ";
     if (Op.isDebug())
       OS << "debug-use ";
-    printRegMIR(Reg, OS, TRI);
+    OS << printReg(Reg, TRI);
     // Print the sub register.
     if (Op.getSubReg() != 0)
       OS << '.' << TRI->getSubRegIndexName(Op.getSubReg());
@@ -1041,7 +1028,7 @@ void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
       if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
         if (IsCommaNeeded)
           OS << ", ";
-        printRegMIR(Reg, OS, TRI);
+        OS << printReg(Reg, TRI);
         IsCommaNeeded = true;
       }
     }
@@ -1212,7 +1199,7 @@ static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
     OS << "<badreg>";
     return;
   }
-  printRegMIR(Reg, OS, TRI);
+  OS << printReg(Reg, TRI);
 }
 
 void MIPrinter::print(const MCCFIInstruction &CFI,

lib/CodeGen/MachineVerifier.cpp

@@ -1097,8 +1097,8 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
               TII->getRegClass(MCID, MONum, TRI, *MF)) {
           if (!DRC->contains(Reg)) {
             report("Illegal physical register for instruction", MO, MONum);
-            errs() << TRI->getName(Reg) << " is not a "
-                << TRI->getRegClassName(DRC) << " register.\n";
+            errs() << printReg(Reg, TRI) << " is not a "
+                   << TRI->getRegClassName(DRC) << " register.\n";
           }
         }
       }
@@ -1689,7 +1689,7 @@ void MachineVerifier::visitMachineFunctionAfter() {
       if (MInfo.regsKilled.count(*I)) {
         report("Virtual register killed in block, but needed live out.", &MBB);
         errs() << "Virtual register " << printReg(*I)
-            << " is used after the block.\n";
+               << " is used after the block.\n";
       }
   }
 
@@ -1722,13 +1722,13 @@ void MachineVerifier::verifyLiveVariables() {
         if (!VI.AliveBlocks.test(MBB.getNumber())) {
           report("LiveVariables: Block missing from AliveBlocks", &MBB);
           errs() << "Virtual register " << printReg(Reg)
-              << " must be live through the block.\n";
+                 << " must be live through the block.\n";
         }
       } else {
         if (VI.AliveBlocks.test(MBB.getNumber())) {
           report("LiveVariables: Block should not be in AliveBlocks", &MBB);
           errs() << "Virtual register " << printReg(Reg)
-              << " is not needed live through the block.\n";
+                 << " is not needed live through the block.\n";
         }
       }
     }

lib/CodeGen/RegAllocBasic.cpp

@@ -219,8 +219,8 @@ bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
       Intfs.push_back(Intf);
     }
   }
-  DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) <<
-        " interferences with " << VirtReg << "\n");
+  DEBUG(dbgs() << "spilling " << printReg(PhysReg, TRI)
+               << " interferences with " << VirtReg << "\n");
   assert(!Intfs.empty() && "expected interference");
 
   // Spill each interfering vreg allocated to PhysReg or an alias.

lib/CodeGen/RegAllocFast.cpp

@@ -813,7 +813,7 @@ void RegAllocFast::handleThroughOperands(MachineInstr &MI,
 void RegAllocFast::dumpState() {
   for (unsigned Reg = 1, E = TRI->getNumRegs(); Reg != E; ++Reg) {
     if (PhysRegState[Reg] == regDisabled) continue;
-    dbgs() << " " << TRI->getName(Reg);
+    dbgs() << " " << printReg(Reg, TRI);
     switch(PhysRegState[Reg]) {
     case regFree:
       break;

lib/CodeGen/RegUsageInfoCollector.cpp

@@ -141,7 +141,7 @@ bool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) {
 
   for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg)
     if (MachineOperand::clobbersPhysReg(&(RegMask[0]), PReg))
-      DEBUG(dbgs() << TRI->getName(PReg) << " ");
+      DEBUG(dbgs() << printReg(PReg, TRI) << " ");
 
   DEBUG(dbgs() << " \n----------------------------------------\n");
 

lib/CodeGen/RegisterScavenging.cpp

@@ -288,8 +288,8 @@ bool RegScavenger::isRegUsed(unsigned Reg, bool includeReserved) const {
 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const {
   for (unsigned Reg : *RC) {
     if (!isRegUsed(Reg)) {
-      DEBUG(dbgs() << "Scavenger found unused reg: " << TRI->getName(Reg) <<
-            "\n");
+      DEBUG(dbgs() << "Scavenger found unused reg: " << printReg(Reg, TRI)
+                   << "\n");
       return Reg;
     }
   }
@@ -561,15 +561,15 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
 
   // If we found an unused register there is no reason to spill it.
   if (!isRegUsed(SReg)) {
-    DEBUG(dbgs() << "Scavenged register: " << TRI->getName(SReg) << "\n");
+    DEBUG(dbgs() << "Scavenged register: " << printReg(SReg, TRI) << "\n");
     return SReg;
   }
 
   ScavengedInfo &Scavenged = spill(SReg, *RC, SPAdj, I, UseMI);
   Scavenged.Restore = &*std::prev(UseMI);
 
-  DEBUG(dbgs() << "Scavenged register (with spill): " << TRI->getName(SReg) <<
-        "\n");
+  DEBUG(dbgs() << "Scavenged register (with spill): " << printReg(SReg, TRI)
+               << "\n");
 
   return SReg;
 }
@@ -599,7 +599,7 @@ unsigned RegScavenger::scavengeRegisterBackwards(const TargetRegisterClass &RC,
     Scavenged.Restore = &*std::prev(SpillBefore);
     LiveUnits.removeReg(Reg);
     DEBUG(dbgs() << "Scavenged register with spill: " << printReg(Reg, TRI)
-          << " until " << *SpillBefore);
+                 << " until " << *SpillBefore);
   } else {
     DEBUG(dbgs() << "Scavenged free register: " << printReg(Reg, TRI) << '\n');
   }

lib/CodeGen/RegisterUsageInfo.cpp

@@ -97,7 +97,7 @@ void PhysicalRegisterUsageInfo::print(raw_ostream &OS, const Module *M) const {
 
     for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {
       if (MachineOperand::clobbersPhysReg(&(FPRMPair->second[0]), PReg))
-        OS << TRI->getName(PReg) << " ";
+        OS << printReg(PReg, TRI) << " ";
     }
     OS << "\n";
   }

lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

@@ -1430,10 +1430,12 @@ SUnit *ScheduleDAGRRList::PickNodeToScheduleBottomUp() {
       SmallVector<unsigned, 4> LRegs;
       if (!DelayForLiveRegsBottomUp(CurSU, LRegs))
         break;
-      DEBUG(dbgs() << "    Interfering reg " <<
-            (LRegs[0] == TRI->getNumRegs() ? "CallResource"
-             : TRI->getName(LRegs[0]))
-             << " SU #" << CurSU->NodeNum << '\n');
+      DEBUG(dbgs() << "    Interfering reg ";
+            if (LRegs[0] == TRI->getNumRegs())
+              dbgs() << "CallResource";
+            else
+              dbgs() << printReg(LRegs[0], TRI);
+            dbgs() << " SU #" << CurSU->NodeNum << '\n');
       std::pair<LRegsMapT::iterator, bool> LRegsPair =
         LRegsMap.insert(std::make_pair(CurSU, LRegs));
       if (LRegsPair.second) {

lib/CodeGen/StackMaps.cpp

@@ -193,14 +193,14 @@ void StackMaps::print(raw_ostream &OS) {
       case Location::Register:
         OS << "Register ";
         if (TRI)
-          OS << TRI->getName(Loc.Reg);
+          OS << printReg(Loc.Reg, TRI);
         else
           OS << Loc.Reg;
         break;
       case Location::Direct:
         OS << "Direct ";
         if (TRI)
-          OS << TRI->getName(Loc.Reg);
+          OS << printReg(Loc.Reg, TRI);
         else
           OS << Loc.Reg;
         if (Loc.Offset)
@@ -209,7 +209,7 @@ void StackMaps::print(raw_ostream &OS) {
       case Location::Indirect:
         OS << "Indirect ";
         if (TRI)
-          OS << TRI->getName(Loc.Reg);
+          OS << printReg(Loc.Reg, TRI);
         else
           OS << Loc.Reg;
         OS << "+" << Loc.Offset;
@@ -233,7 +233,7 @@ void StackMaps::print(raw_ostream &OS) {
     for (const auto &LO : LiveOuts) {
       OS << WSMP << "\t\tLO " << Idx << ": ";
       if (TRI)
-        OS << TRI->getName(LO.Reg);
+        OS << printReg(LO.Reg, TRI);
       else
         OS << LO.Reg;
       OS << "\t[encoding: .short " << LO.DwarfRegNum << ", .byte 0, .byte "

lib/CodeGen/TargetRegisterInfo.cpp

@@ -94,11 +94,14 @@ Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI,
       OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
     else if (TargetRegisterInfo::isVirtualRegister(Reg))
       OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
-    else if (TRI && Reg < TRI->getNumRegs()) {
+    else if (!TRI)
+      OS << '%' << "physreg" << Reg;
+    else if (Reg < TRI->getNumRegs()) {
       OS << '%';
       printLowerCase(TRI->getName(Reg), OS);
     } else
-      OS << "%physreg" << Reg;
+      llvm_unreachable("Register kind is unsupported.");
+
     if (SubIdx) {
       if (TRI)
         OS << ':' << TRI->getSubRegIndexName(SubIdx);

lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp

@@ -538,7 +538,7 @@ bool AArch64A57FPLoadBalancing::colorChain(Chain *G, Color C,
     DEBUG(dbgs() << "Scavenging (thus coloring) failed!\n");
     return false;
   }
-  DEBUG(dbgs() << " - Scavenged register: " << TRI->getName(Reg) << "\n");
+  DEBUG(dbgs() << " - Scavenged register: " << printReg(Reg, TRI) << "\n");
 
   std::map<unsigned, unsigned> Substs;
   for (MachineInstr &I : *G) {
@@ -611,8 +611,8 @@ void AArch64A57FPLoadBalancing::scanInstruction(
     // unit.
     unsigned DestReg = MI->getOperand(0).getReg();
 
-    DEBUG(dbgs() << "New chain started for register "
-          << TRI->getName(DestReg) << " at " << *MI);
+    DEBUG(dbgs() << "New chain started for register " << printReg(DestReg, TRI)
+                 << " at " << *MI);
 
     auto G = llvm::make_unique<Chain>(MI, Idx, getColor(DestReg));
     ActiveChains[DestReg] = G.get();
@@ -632,7 +632,7 @@ void AArch64A57FPLoadBalancing::scanInstruction(
 
     if (ActiveChains.find(AccumReg) != ActiveChains.end()) {
       DEBUG(dbgs() << "Chain found for accumulator register "
-            << TRI->getName(AccumReg) << " in MI " << *MI);
+                   << printReg(AccumReg, TRI) << " in MI " << *MI);
 
       // For simplicity we only chain together sequences of MULs/MLAs where the
       // accumulator register is killed on each instruction. This means we don't
@@ -657,7 +657,7 @@ void AArch64A57FPLoadBalancing::scanInstruction(
     }
 
     DEBUG(dbgs() << "Creating new chain for dest register "
-          << TRI->getName(DestReg) << "\n");
+                 << printReg(DestReg, TRI) << "\n");
     auto G = llvm::make_unique<Chain>(MI, Idx, getColor(DestReg));
     ActiveChains[DestReg] = G.get();
     AllChains.push_back(std::move(G));
@@ -685,8 +685,8 @@ maybeKillChain(MachineOperand &MO, unsigned Idx,
 
     // If this is a KILL of a current chain, record it.
     if (MO.isKill() && ActiveChains.find(MO.getReg()) != ActiveChains.end()) {
-      DEBUG(dbgs() << "Kill seen for chain " << TRI->getName(MO.getReg())
-            << "\n");
+      DEBUG(dbgs() << "Kill seen for chain " << printReg(MO.getReg(), TRI)
+                   << "\n");
       ActiveChains[MO.getReg()]->setKill(MI, Idx, /*Immutable=*/MO.isTied());
     }
     ActiveChains.erase(MO.getReg());
@@ -697,7 +697,7 @@ maybeKillChain(MachineOperand &MO, unsigned Idx,
          I != E;) {
       if (MO.clobbersPhysReg(I->first)) {
         DEBUG(dbgs() << "Kill (regmask) seen for chain "
-              << TRI->getName(I->first) << "\n");
+                     << printReg(I->first, TRI) << "\n");
         I->second->setKill(MI, Idx, /*Immutable=*/true);
         ActiveChains.erase(I++);
       } else

lib/Target/AArch64/AArch64FrameLowering.cpp

@@ -1060,9 +1060,9 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
       StrOpc = RPI.isPaired() ? AArch64::STPXi : AArch64::STRXui;
     else
       StrOpc = RPI.isPaired() ? AArch64::STPDi : AArch64::STRDui;
-    DEBUG(dbgs() << "CSR spill: (" << TRI->getName(Reg1);
+    DEBUG(dbgs() << "CSR spill: (" << printReg(Reg1, TRI);
           if (RPI.isPaired())
-            dbgs() << ", " << TRI->getName(Reg2);
+            dbgs() << ", " << printReg(Reg2, TRI);
           dbgs() << ") -> fi#(" << RPI.FrameIdx;
           if (RPI.isPaired())
             dbgs() << ", " << RPI.FrameIdx+1;
@@ -1123,9 +1123,9 @@ bool AArch64FrameLowering::restoreCalleeSavedRegisters(
       LdrOpc = RPI.isPaired() ? AArch64::LDPXi : AArch64::LDRXui;
     else
       LdrOpc = RPI.isPaired() ? AArch64::LDPDi : AArch64::LDRDui;
-    DEBUG(dbgs() << "CSR restore: (" << TRI->getName(Reg1);
+    DEBUG(dbgs() << "CSR restore: (" << printReg(Reg1, TRI);
           if (RPI.isPaired())
-            dbgs() << ", " << TRI->getName(Reg2);
+            dbgs() << ", " << printReg(Reg2, TRI);
           dbgs() << ") -> fi#(" << RPI.FrameIdx;
           if (RPI.isPaired())
             dbgs() << ", " << RPI.FrameIdx+1;
@@ -1234,7 +1234,7 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
   if (BigStack) {
     if (!ExtraCSSpill && UnspilledCSGPR != AArch64::NoRegister) {
       DEBUG(dbgs() << "Spilling " << printReg(UnspilledCSGPR, RegInfo)
-            << " to get a scratch register.\n");
+                   << " to get a scratch register.\n");
       SavedRegs.set(UnspilledCSGPR);
       // MachO's compact unwind format relies on all registers being stored in
       // pairs, so if we need to spill one extra for BigStack, then we need to

lib/Target/BPF/BPFISelDAGToDAG.cpp

@@ -546,8 +546,7 @@ void BPFDAGToDAGISel::PreprocessTrunc(SDNode *Node,
   if (!RegN || !TargetRegisterInfo::isVirtualRegister(RegN->getReg()))
     return;
   unsigned AndOpReg = RegN->getReg();
-  DEBUG(dbgs() << "Examine %" << TargetRegisterInfo::virtReg2Index(AndOpReg)
-               << '\n');
+  DEBUG(dbgs() << "Examine " << printReg(AndOpReg) << '\n');
 
   // Examine the PHI insns in the MachineBasicBlock to found out the
   // definitions of this virtual register. At this stage (DAG2DAG

test/CodeGen/AArch64/GlobalISel/debug-insts.ll

@@ -6,7 +6,7 @@
 ; CHECK:    - { id: {{.*}}, name: in.addr, type: default, offset: 0, size: {{.*}}, alignment: {{.*}},
 ; CHECK-NEXT: callee-saved-register: '', callee-saved-restored: true,
 ; CHECK-NEXT: di-variable: '!11', di-expression: '!DIExpression()',
-; CHECK: DBG_VALUE debug-use %0(s32), debug-use _, !11, !DIExpression(), debug-location !12
+; CHECK: DBG_VALUE debug-use %0(s32), debug-use %noreg, !11, !DIExpression(), debug-location !12
 define void @debug_declare(i32 %in) #0 !dbg !7 {
 entry:
   %in.addr = alloca i32, align 4
@@ -17,7 +17,7 @@ entry:
 }
 
 ; CHECK-LABEL: name: debug_declare_vla
-; CHECK: DBG_VALUE debug-use %{{[0-9]+}}(p0), debug-use _, !14, !DIExpression(), debug-location !15
+; CHECK: DBG_VALUE debug-use %{{[0-9]+}}(p0), debug-use %noreg, !14, !DIExpression(), debug-location !15
 define void @debug_declare_vla(i32 %in) #0 !dbg !13 {
 entry:
   %vla.addr = alloca i32, i32 %in
@@ -29,16 +29,16 @@ entry:
 ; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w0
 define void @debug_value(i32 %in) #0 !dbg !16 {
   %addr = alloca i32
-; CHECK: DBG_VALUE debug-use [[IN]](s32), debug-use _, !17, !DIExpression(), debug-location !18
+; CHECK: DBG_VALUE debug-use [[IN]](s32), debug-use %noreg, !17, !DIExpression(), debug-location !18
   call void @llvm.dbg.value(metadata i32 %in, i64 0, metadata !17, metadata !DIExpression()), !dbg !18
   store i32 %in, i32* %addr
-; CHECK: DBG_VALUE debug-use %1(p0), debug-use _, !17, !DIExpression(DW_OP_deref), debug-location !18
+; CHECK: DBG_VALUE debug-use %1(p0), debug-use %noreg, !17, !DIExpression(DW_OP_deref), debug-location !18
   call void @llvm.dbg.value(metadata i32* %addr, i64 0, metadata !17, metadata !DIExpression(DW_OP_deref)), !dbg !18
 ; CHECK: DBG_VALUE 123, 0, !17, !DIExpression(), debug-location !18
   call void @llvm.dbg.value(metadata i32 123, i64 0, metadata !17, metadata !DIExpression()), !dbg !18
 ; CHECK: DBG_VALUE float 1.000000e+00, 0, !17, !DIExpression(), debug-location !18
   call void @llvm.dbg.value(metadata float 1.000000e+00, i64 0, metadata !17, metadata !DIExpression()), !dbg !18
-; CHECK: DBG_VALUE _, 0, !17, !DIExpression(), debug-location !18
+; CHECK: DBG_VALUE %noreg, 0, !17, !DIExpression(), debug-location !18
   call void @llvm.dbg.value(metadata i32* null, i64 0, metadata !17, metadata !DIExpression()), !dbg !18
   ret void
 }

test/CodeGen/AArch64/GlobalISel/regbankselect-dbg-value.mir

@@ -36,9 +36,9 @@ body: |
   bb.0:
     liveins: %w0
     %0:_(s32) = COPY %w0
-    ; CHECK: DBG_VALUE debug-use %0(s32), debug-use _, !7, !DIExpression(), debug-location !9
-    DBG_VALUE debug-use %0(s32), debug-use _, !7, !DIExpression(), debug-location !9
+    ; CHECK: DBG_VALUE debug-use %0(s32), debug-use %noreg, !7, !DIExpression(), debug-location !9
+    DBG_VALUE debug-use %0(s32), debug-use %noreg, !7, !DIExpression(), debug-location !9
 
-    ; CHECK: DBG_VALUE _, 0, !7, !DIExpression(), debug-location !9
-    DBG_VALUE _, 0, !7, !DIExpression(), debug-location !9
+    ; CHECK: DBG_VALUE %noreg, 0, !7, !DIExpression(), debug-location !9
+    DBG_VALUE %noreg, 0, !7, !DIExpression(), debug-location !9
 ...

test/CodeGen/AArch64/GlobalISel/select-dbg-value.mir

@@ -46,11 +46,11 @@ body: |
     ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
     ; CHECK: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY]]
     ; CHECK: %w0 = COPY [[ADDWrr]]
-    ; CHECK: DBG_VALUE debug-use [[ADDWrr]], debug-use _, !7, !DIExpression(), debug-location !9
+    ; CHECK: DBG_VALUE debug-use [[ADDWrr]], debug-use %noreg, !7, !DIExpression(), debug-location !9
     %0:gpr(s32) = COPY %w0
     %1:gpr(s32) = G_ADD %0, %0
     %w0 = COPY %1(s32)
-    DBG_VALUE debug-use %1(s32), debug-use _, !7, !DIExpression(), debug-location !9
+    DBG_VALUE debug-use %1(s32), debug-use %noreg, !7, !DIExpression(), debug-location !9
 ...
 
 ---
@@ -62,7 +62,7 @@ body: |
     liveins: %w0
     ; CHECK-LABEL: name: test_dbg_value_dead
     ; CHECK-NOT: COPY
-    ; CHECK: DBG_VALUE debug-use _, debug-use _, !7, !DIExpression(), debug-location !9
+    ; CHECK: DBG_VALUE debug-use %noreg, debug-use %noreg, !7, !DIExpression(), debug-location !9
     %0:gpr(s32) = COPY %w0
-    DBG_VALUE debug-use %0(s32), debug-use _, !7, !DIExpression(), debug-location !9
+    DBG_VALUE debug-use %0(s32), debug-use %noreg, !7, !DIExpression(), debug-location !9
 ...

test/CodeGen/AArch64/machine-outliner-remarks.ll

@@ -120,4 +120,4 @@ attributes #0 = { noredzone nounwind ssp uwtable "no-frame-pointer-elim"="false"
 !26 = !DILocation(line: 29, column: 9, scope: !18)
 !27 = distinct !DISubprogram(name: "bar", scope: !1, file: !1, line: 35, type: !9, isLocal: false, isDefinition: true, scopeLine: 35, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2)
 !33 = !DILocation(line: 36, column: 1, scope: !27)
-!35 = !DILocation(line: 38, column: 1, scope: !27)
+!35 = !DILocation(line: 38, column: 1, scope: !27)

test/CodeGen/AMDGPU/fadd.ll

@@ -72,4 +72,4 @@ define amdgpu_kernel void @fadd_0_nsz_attr_f32(float addrspace(1)* %out, float %
 }
 
 attributes #0 = { nounwind }
-attributes #1 = { nounwind "no-signed-zeros-fp-math"="true" }
+attributes #1 = { nounwind "no-signed-zeros-fp-math"="true" }

test/CodeGen/AMDGPU/inserted-wait-states.mir

@@ -548,7 +548,7 @@ body:             |
 
     %flat_scr_lo = S_ADD_U32 %sgpr6, %sgpr9, implicit-def %scc
     %flat_scr_hi = S_ADDC_U32 %sgpr7, 0, implicit-def %scc, implicit %scc
-    DBG_VALUE _, 2, !5, !11, debug-location !12
+    DBG_VALUE %noreg, 2, !5, !11, debug-location !12
     %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr4_sgpr5, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
     dead %sgpr6_sgpr7 = KILL %sgpr4_sgpr5
     %sgpr8 = S_MOV_B32 %sgpr5

test/CodeGen/AMDGPU/promote-alloca-to-lds-select.ll

@@ -130,4 +130,4 @@ bb:
 }
 
 attributes #0 = { norecurse nounwind "amdgpu-waves-per-eu"="1,1" }
-attributes #1 = { norecurse nounwind }
+attributes #1 = { norecurse nounwind }

test/CodeGen/AMDGPU/regcoalesce-dbg.mir

@@ -63,7 +63,7 @@ body:             |
     %19.sub1 = COPY killed %18
     %10 = S_MOV_B32 61440
     %11 = S_MOV_B32 0
-    DBG_VALUE debug-use %11, debug-use _, !1, !8, debug-location !9
+    DBG_VALUE debug-use %11, debug-use %noreg, !1, !8, debug-location !9
     undef %12.sub0 = COPY killed %11
     %12.sub1 = COPY killed %10
     undef %13.sub0_sub1 = COPY killed %4

test/CodeGen/ARM/ARMLoadStoreDBG.mir

@@ -120,40 +120,40 @@ body:             |
   bb.0.entry:
     liveins: %r0, %r1, %r2, %r3, %lr, %r7
 
-    DBG_VALUE debug-use %r0, debug-use _, !18, !27, debug-location !28
-    DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28
-    DBG_VALUE debug-use %r2, debug-use _, !20, !27, debug-location !28
-    DBG_VALUE debug-use %r3, debug-use _, !21, !27, debug-location !28
-    t2CMPri %r3, 4, 14, _, implicit-def %cpsr, debug-location !31
+    DBG_VALUE debug-use %r0, debug-use %noreg, !18, !27, debug-location !28
+    DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
+    DBG_VALUE debug-use %r2, debug-use %noreg, !20, !27, debug-location !28
+    DBG_VALUE debug-use %r3, debug-use %noreg, !21, !27, debug-location !28
+    t2CMPri %r3, 4, 14, %noreg, implicit-def %cpsr, debug-location !31
     t2Bcc %bb.2.if.end, 2, killed %cpsr
 
   bb.1:
     liveins: %lr, %r7
 
-    DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28
-    %r0 = t2MOVi -1, 14, _, _
-    DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28
-    tBX_RET 14, _, implicit %r0, debug-location !34
+    DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
+    %r0 = t2MOVi -1, 14, %noreg, %noreg
+    DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
+    tBX_RET 14, %noreg, implicit %r0, debug-location !34
 
   bb.2.if.end:
     liveins: %r0, %r2, %r3, %r7, %lr
 
-    %sp = frame-setup t2STMDB_UPD %sp, 14, _, killed %r7, killed %lr
+    %sp = frame-setup t2STMDB_UPD %sp, 14, %noreg, killed %r7, killed %lr
     frame-setup CFI_INSTRUCTION def_cfa_offset 8
     frame-setup CFI_INSTRUCTION offset %lr, -4
     frame-setup CFI_INSTRUCTION offset %r7, -8
-    DBG_VALUE debug-use %r0, debug-use _, !18, !27, debug-location !28
-    DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28
-    DBG_VALUE debug-use %r2, debug-use _, !20, !27, debug-location !28
-    DBG_VALUE debug-use %r3, debug-use _, !21, !27, debug-location !28
+    DBG_VALUE debug-use %r0, debug-use %noreg, !18, !27, debug-location !28
+    DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
+    DBG_VALUE debug-use %r2, debug-use %noreg, !20, !27, debug-location !28
+    DBG_VALUE debug-use %r3, debug-use %noreg, !21, !27, debug-location !28
     %r1 = COPY killed %r2, debug-location !32
-    DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28
+    DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
     %r2 = COPY killed %r3, debug-location !32
-    tBL 14, _, @g, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit-def %sp, debug-location !32
-    %r0 = t2MOVi 0, 14, _, _
-    %sp = t2LDMIA_UPD %sp, 14, _, def %r7, def %lr
-    tBX_RET 14, _, implicit %r0, debug-location !34
+    tBL 14, %noreg, @g, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit-def %sp, debug-location !32
+    %r0 = t2MOVi 0, 14, %noreg, %noreg
+    %sp = t2LDMIA_UPD %sp, 14, %noreg, def %r7, def %lr
+    tBX_RET 14, %noreg, implicit %r0, debug-location !34
 # Verify that the DBG_VALUE is ignored.
-# CHECK: %sp = t2LDMIA_RET %sp, 14, _, def %r7, def %pc, implicit %r0
+# CHECK: %sp = t2LDMIA_RET %sp, 14, %noreg, def %r7, def %pc, implicit %r0
 
 ...

test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll

@@ -7,11 +7,11 @@ define arm_aapcscc void @test_indirect_call(void() *%fptr) {
 ; V5T: %[[FPTR:[0-9]+]]:gpr(p0) = COPY %r0
 ; V4T: %[[FPTR:[0-9]+]]:tgpr(p0) = COPY %r0
 ; NOV4T: %[[FPTR:[0-9]+]]:tgpr(p0) = COPY %r0
-; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
 ; V5T: BLX %[[FPTR]](p0), csr_aapcs, implicit-def %lr, implicit %sp
 ; V4T: BX_CALL %[[FPTR]](p0), csr_aapcs, implicit-def %lr, implicit %sp
 ; NOV4T: BMOVPCRX_CALL %[[FPTR]](p0), csr_aapcs, implicit-def %lr, implicit %sp
-; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
 entry:
   notail call arm_aapcscc void %fptr()
   ret void
@@ -21,9 +21,9 @@ declare arm_aapcscc void @call_target()
 
 define arm_aapcscc void @test_direct_call() {
 ; CHECK-LABEL: name: test_direct_call
-; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
 ; CHECK: BL @call_target, csr_aapcs, implicit-def %lr, implicit %sp
-; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
 entry:
   notail call arm_aapcscc void @call_target()
   ret void

test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir

@@ -50,13 +50,13 @@ body:             |
 
     %3(s32) = G_MUL %0, %1
     %4(s32) = G_ADD %3, %2
-    ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, _, _
+    ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, %noreg, %noreg
 
     %r0 = COPY %4(s32)
     ; CHECK: %r0 = COPY [[VREGR]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_mla_commutative
@@ -84,13 +84,13 @@ body:             |
 
     %3(s32) = G_MUL %0, %1
     %4(s32) = G_ADD %2, %3
-    ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, _, _
+    ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, %noreg, %noreg
 
     %r0 = COPY %4(s32)
     ; CHECK: %r0 = COPY [[VREGR]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_mla_v5
@@ -118,13 +118,13 @@ body:             |
 
     %3(s32) = G_MUL %0, %1
     %4(s32) = G_ADD %3, %2
-    ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLAv5 [[VREGX]], [[VREGY]], [[VREGZ]], 14, _, _
+    ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLAv5 [[VREGX]], [[VREGY]], [[VREGZ]], 14, %noreg, %noreg
 
     %r0 = COPY %4(s32)
     ; CHECK: %r0 = COPY [[VREGR]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_mls
@@ -152,13 +152,13 @@ body:             |
 
     %3(s32) = G_MUL %0, %1
     %4(s32) = G_SUB %2, %3
-    ; CHECK: [[VREGR:%[0-9]+]]:gpr = MLS [[VREGX]], [[VREGY]], [[VREGZ]], 14, _
+    ; CHECK: [[VREGR:%[0-9]+]]:gpr = MLS [[VREGX]], [[VREGY]], [[VREGZ]], 14, %noreg
 
     %r0 = COPY %4(s32)
     ; CHECK: %r0 = COPY [[VREGR]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_no_mls
@@ -186,14 +186,14 @@ body:             |
 
     %3(s32) = G_MUL %0, %1
     %4(s32) = G_SUB %2, %3
-    ; CHECK: [[VREGM:%[0-9]+]]:gprnopc = MULv5 [[VREGX]], [[VREGY]], 14, _, _
-    ; CHECK: [[VREGR:%[0-9]+]]:gpr = SUBrr [[VREGZ]], [[VREGM]], 14, _, _
+    ; CHECK: [[VREGM:%[0-9]+]]:gprnopc = MULv5 [[VREGX]], [[VREGY]], 14, %noreg, %noreg
+    ; CHECK: [[VREGR:%[0-9]+]]:gpr = SUBrr [[VREGZ]], [[VREGM]], 14, %noreg, %noreg
 
     %r0 = COPY %4(s32)
     ; CHECK: %r0 = COPY [[VREGR]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_shifts_to_revsh
@@ -238,8 +238,8 @@ body:             |
     %r0 = COPY %9(s32)
     ; CHECK: %r0 = COPY [[VREGR]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_shifts_to_revsh_commutative
@@ -284,8 +284,8 @@ body:             |
     %r0 = COPY %9(s32)
     ; CHECK: %r0 = COPY [[VREGR]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_shifts_no_revsh_features
@@ -329,7 +329,7 @@ body:             |
 
     %r0 = COPY %9(s32)
 
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_shifts_no_revsh_constants
@@ -373,7 +373,7 @@ body:             |
 
     %r0 = COPY %9(s32)
 
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_bicrr
@@ -400,13 +400,13 @@ body:             |
     %2(s32) = G_CONSTANT i32 -1
     %3(s32) = G_XOR %1, %2
     %4(s32) = G_AND %0, %3
-    ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICrr [[VREGX]], [[VREGY]], 14, _, _
+    ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICrr [[VREGX]], [[VREGY]], 14, %noreg, %noreg
 
     %r0 = COPY %4(s32)
     ; CHECK: %r0 = COPY [[VREGR]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_bicrr_commutative
@@ -433,13 +433,13 @@ body:             |
     %2(s32) = G_CONSTANT i32 -1
     %3(s32) = G_XOR %1, %2
     %4(s32) = G_AND %3, %0
-    ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICrr [[VREGX]], [[VREGY]], 14, _, _
+    ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICrr [[VREGX]], [[VREGY]], 14, %noreg, %noreg
 
     %r0 = COPY %4(s32)
     ; CHECK: %r0 = COPY [[VREGR]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_bicri
@@ -471,13 +471,13 @@ body:             |
     %2(s32) = G_CONSTANT i32 -1
     %3(s32) = G_XOR %1, %2
     %4(s32) = G_AND %0, %3
-    ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, _, _
+    ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, %noreg, %noreg
 
     %r0 = COPY %4(s32)
     ; CHECK: %r0 = COPY [[VREGR]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_bicri_commutative_xor
@@ -504,13 +504,13 @@ body:             |
     %2(s32) = G_CONSTANT i32 -1
     %3(s32) = G_XOR %2, %1
     %4(s32) = G_AND %0, %3
-    ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, _, _
+    ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, %noreg, %noreg
 
     %r0 = COPY %4(s32)
     ; CHECK: %r0 = COPY [[VREGR]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_bicri_commutative_and
@@ -537,13 +537,13 @@ body:             |
     %2(s32) = G_CONSTANT i32 -1
     %3(s32) = G_XOR %1, %2
     %4(s32) = G_AND %3, %0
-    ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, _, _
+    ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, %noreg, %noreg
 
     %r0 = COPY %4(s32)
     ; CHECK: %r0 = COPY [[VREGR]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_bicri_commutative_both
@@ -570,11 +570,11 @@ body:             |
     %2(s32) = G_CONSTANT i32 -1
     %3(s32) = G_XOR %2, %1
     %4(s32) = G_AND %3, %0
-    ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, _, _
+    ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, %noreg, %noreg
 
     %r0 = COPY %4(s32)
     ; CHECK: %r0 = COPY [[VREGR]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...

test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir

@@ -81,13 +81,13 @@ body:             |
     ; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr = COPY [[VREG]]
 
     %2(s32) = G_ZEXT %1(s1)
-    ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = ANDri [[VREGTRUNC]], 1, 14, _, _
+    ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = ANDri [[VREGTRUNC]], 1, 14, %noreg, %noreg
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGEXT]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_trunc_and_sext_s1
@@ -111,14 +111,14 @@ body:             |
     ; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr = COPY [[VREG]]
 
     %2(s32) = G_SEXT %1(s1)
-    ; CHECK: [[VREGAND:%[0-9]+]]:gpr = ANDri [[VREGTRUNC]], 1, 14, _, _
-    ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = RSBri [[VREGAND]], 0, 14, _, _
+    ; CHECK: [[VREGAND:%[0-9]+]]:gpr = ANDri [[VREGTRUNC]], 1, 14, %noreg, %noreg
+    ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = RSBri [[VREGAND]], 0, 14, %noreg, %noreg
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGEXT]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_trunc_and_sext_s8
@@ -142,13 +142,13 @@ body:             |
     ; CHECK: [[VREGTRUNC:%[0-9]+]]:gprnopc = COPY [[VREG]]
 
     %2(s32) = G_SEXT %1(s8)
-    ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = SXTB [[VREGTRUNC]], 0, 14, _
+    ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = SXTB [[VREGTRUNC]], 0, 14, %noreg
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGEXT]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_trunc_and_zext_s16
@@ -172,13 +172,13 @@ body:             |
     ; CHECK: [[VREGTRUNC:%[0-9]+]]:gprnopc = COPY [[VREG]]
 
     %2(s32) = G_ZEXT %1(s16)
-    ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = UXTH [[VREGTRUNC]], 0, 14, _
+    ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = UXTH [[VREGTRUNC]], 0, 14, %noreg
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGEXT]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_trunc_and_anyext_s8
@@ -207,8 +207,8 @@ body:             |
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGEXT]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_trunc_and_anyext_s16
@@ -237,8 +237,8 @@ body:             |
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGEXT]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_add_s32
@@ -262,13 +262,13 @@ body:             |
     ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
 
     %2(s32) = G_ADD %0, %1
-    ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDrr [[VREGX]], [[VREGY]], 14, _, _
+    ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDrr [[VREGX]], [[VREGY]], 14, %noreg, %noreg
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGSUM]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_add_fold_imm_s32
@@ -290,13 +290,13 @@ body:             |
 
     %1(s32) = G_CONSTANT i32 255
     %2(s32) = G_ADD %0, %1
-    ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDri [[VREGX]], 255, 14, _, _
+    ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDri [[VREGX]], 255, 14, %noreg, %noreg
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGSUM]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_add_no_fold_imm_s32
@@ -317,16 +317,16 @@ body:             |
     ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
 
     %1(s32) = G_CONSTANT i32 65535
-    ; CHECK: [[VREGY:%[0-9]+]]:gpr = MOVi16 65535, 14, _
+    ; CHECK: [[VREGY:%[0-9]+]]:gpr = MOVi16 65535, 14, %noreg
 
     %2(s32) = G_ADD %0, %1
-    ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDrr [[VREGX]], [[VREGY]], 14, _, _
+    ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDrr [[VREGX]], [[VREGY]], 14, %noreg, %noreg
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGSUM]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_fadd_s32
@@ -350,13 +350,13 @@ body:             |
     ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY %s1
 
     %2(s32) = G_FADD %0, %1
-    ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VADDS [[VREGX]], [[VREGY]], 14, _
+    ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VADDS [[VREGX]], [[VREGY]], 14, %noreg
 
     %s0 = COPY %2(s32)
     ; CHECK: %s0 = COPY [[VREGSUM]]
 
-    BX_RET 14, _, implicit %s0
-    ; CHECK: BX_RET 14, _, implicit %s0
+    BX_RET 14, %noreg, implicit %s0
+    ; CHECK: BX_RET 14, %noreg, implicit %s0
 ...
 ---
 name:            test_fadd_s64
@@ -380,13 +380,13 @@ body:             |
     ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY %d1
 
     %2(s64) = G_FADD %0, %1
-    ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VADDD [[VREGX]], [[VREGY]], 14, _
+    ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VADDD [[VREGX]], [[VREGY]], 14, %noreg
 
     %d0 = COPY %2(s64)
     ; CHECK: %d0 = COPY [[VREGSUM]]
 
-    BX_RET 14, _, implicit %d0
-    ; CHECK: BX_RET 14, _, implicit %d0
+    BX_RET 14, %noreg, implicit %d0
+    ; CHECK: BX_RET 14, %noreg, implicit %d0
 ...
 ---
 name:            test_fsub_s32
@@ -410,13 +410,13 @@ body:             |
     ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY %s1
 
     %2(s32) = G_FSUB %0, %1
-    ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VSUBS [[VREGX]], [[VREGY]], 14, _
+    ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VSUBS [[VREGX]], [[VREGY]], 14, %noreg
 
     %s0 = COPY %2(s32)
     ; CHECK: %s0 = COPY [[VREGSUM]]
 
-    BX_RET 14, _, implicit %s0
-    ; CHECK: BX_RET 14, _, implicit %s0
+    BX_RET 14, %noreg, implicit %s0
+    ; CHECK: BX_RET 14, %noreg, implicit %s0
 ...
 ---
 name:            test_fsub_s64
@@ -440,13 +440,13 @@ body:             |
     ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY %d1
 
     %2(s64) = G_FSUB %0, %1
-    ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VSUBD [[VREGX]], [[VREGY]], 14, _
+    ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VSUBD [[VREGX]], [[VREGY]], 14, %noreg
 
     %d0 = COPY %2(s64)
     ; CHECK: %d0 = COPY [[VREGSUM]]
 
-    BX_RET 14, _, implicit %d0
-    ; CHECK: BX_RET 14, _, implicit %d0
+    BX_RET 14, %noreg, implicit %d0
+    ; CHECK: BX_RET 14, %noreg, implicit %d0
 ...
 ---
 name:            test_fmul_s32
@@ -470,13 +470,13 @@ body:             |
     ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY %s1
 
     %2(s32) = G_FMUL %0, %1
-    ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VMULS [[VREGX]], [[VREGY]], 14, _
+    ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VMULS [[VREGX]], [[VREGY]], 14, %noreg
 
     %s0 = COPY %2(s32)
     ; CHECK: %s0 = COPY [[VREGSUM]]
 
-    BX_RET 14, _, implicit %s0
-    ; CHECK: BX_RET 14, _, implicit %s0
+    BX_RET 14, %noreg, implicit %s0
+    ; CHECK: BX_RET 14, %noreg, implicit %s0
 ...
 ---
 name:            test_fmul_s64
@@ -500,13 +500,13 @@ body:             |
     ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY %d1
 
     %2(s64) = G_FMUL %0, %1
-    ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VMULD [[VREGX]], [[VREGY]], 14, _
+    ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VMULD [[VREGX]], [[VREGY]], 14, %noreg
 
     %d0 = COPY %2(s64)
     ; CHECK: %d0 = COPY [[VREGSUM]]
 
-    BX_RET 14, _, implicit %d0
-    ; CHECK: BX_RET 14, _, implicit %d0
+    BX_RET 14, %noreg, implicit %d0
+    ; CHECK: BX_RET 14, %noreg, implicit %d0
 ...
 ---
 name:            test_fdiv_s32
@@ -530,13 +530,13 @@ body:             |
     ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY %s1
 
     %2(s32) = G_FDIV %0, %1
-    ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VDIVS [[VREGX]], [[VREGY]], 14, _
+    ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VDIVS [[VREGX]], [[VREGY]], 14, %noreg
 
     %s0 = COPY %2(s32)
     ; CHECK: %s0 = COPY [[VREGSUM]]
 
-    BX_RET 14, _, implicit %s0
-    ; CHECK: BX_RET 14, _, implicit %s0
+    BX_RET 14, %noreg, implicit %s0
+    ; CHECK: BX_RET 14, %noreg, implicit %s0
 ...
 ---
 name:            test_fdiv_s64
@@ -560,13 +560,13 @@ body:             |
     ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY %d1
 
     %2(s64) = G_FDIV %0, %1
-    ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VDIVD [[VREGX]], [[VREGY]], 14, _
+    ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VDIVD [[VREGX]], [[VREGY]], 14, %noreg
 
     %d0 = COPY %2(s64)
     ; CHECK: %d0 = COPY [[VREGSUM]]
 
-    BX_RET 14, _, implicit %d0
-    ; CHECK: BX_RET 14, _, implicit %d0
+    BX_RET 14, %noreg, implicit %d0
+    ; CHECK: BX_RET 14, %noreg, implicit %d0
 ...
 ---
 name:            test_sub_s32
@@ -590,13 +590,13 @@ body:             |
     ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
 
     %2(s32) = G_SUB %0, %1
-    ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SUBrr [[VREGX]], [[VREGY]], 14, _, _
+    ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SUBrr [[VREGX]], [[VREGY]], 14, %noreg, %noreg
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGRES]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_sub_imm_s32
@@ -618,13 +618,13 @@ body:             |
 
     %1(s32) = G_CONSTANT i32 17
     %2(s32) = G_SUB %0, %1
-    ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SUBri [[VREGX]], 17, 14, _, _
+    ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SUBri [[VREGX]], 17, 14, %noreg, %noreg
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGRES]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_sub_rev_imm_s32
@@ -646,13 +646,13 @@ body:             |
 
     %1(s32) = G_CONSTANT i32 17
     %2(s32) = G_SUB %1, %0
-    ; CHECK: [[VREGRES:%[0-9]+]]:gpr = RSBri [[VREGX]], 17, 14, _, _
+    ; CHECK: [[VREGRES:%[0-9]+]]:gpr = RSBri [[VREGX]], 17, 14, %noreg, %noreg
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGRES]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_mul_s32
@@ -676,13 +676,13 @@ body:             |
     ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
 
     %2(s32) = G_MUL %0, %1
-    ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MUL [[VREGX]], [[VREGY]], 14, _, _
+    ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MUL [[VREGX]], [[VREGY]], 14, %noreg, %noreg
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGRES]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_mulv5_s32
@@ -706,13 +706,13 @@ body:             |
     ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
 
     %2(s32) = G_MUL %0, %1
-    ; CHECK: early-clobber [[VREGRES:%[0-9]+]]:gprnopc = MULv5 [[VREGX]], [[VREGY]], 14, _, _
+    ; CHECK: early-clobber [[VREGRES:%[0-9]+]]:gprnopc = MULv5 [[VREGX]], [[VREGY]], 14, %noreg, %noreg
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGRES]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_sdiv_s32
@@ -736,13 +736,13 @@ body:             |
     ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
 
     %2(s32) = G_SDIV %0, %1
-    ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SDIV [[VREGX]], [[VREGY]], 14, _
+    ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SDIV [[VREGX]], [[VREGY]], 14, %noreg
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGRES]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_udiv_s32
@@ -766,13 +766,13 @@ body:             |
     ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
 
     %2(s32) = G_UDIV %0, %1
-    ; CHECK: [[VREGRES:%[0-9]+]]:gpr = UDIV [[VREGX]], [[VREGY]], 14, _
+    ; CHECK: [[VREGRES:%[0-9]+]]:gpr = UDIV [[VREGX]], [[VREGY]], 14, %noreg
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGRES]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_lshr_s32
@@ -796,13 +796,13 @@ body:             |
     ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
 
     %2(s32) = G_LSHR %0, %1
-    ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 3, 14, _, _
+    ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 3, 14, %noreg, %noreg
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGRES]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_ashr_s32
@@ -826,13 +826,13 @@ body:             |
     ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
 
     %2(s32) = G_ASHR %0, %1
-    ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 1, 14, _, _
+    ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 1, 14, %noreg, %noreg
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGRES]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_shl_s32
@@ -856,13 +856,13 @@ body:             |
     ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
 
     %2(s32) = G_SHL %0, %1
-    ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 2, 14, _, _
+    ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 2, 14, %noreg, %noreg
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGRES]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_load_from_stack
@@ -888,19 +888,19 @@ body:             |
     liveins: %r0, %r1, %r2, %r3
 
     %0(p0) = G_FRAME_INDEX %fixed-stack.2
-    ; CHECK: [[FI32VREG:%[0-9]+]]:gpr = ADDri %fixed-stack.[[FI32]], 0, 14, _, _
+    ; CHECK: [[FI32VREG:%[0-9]+]]:gpr = ADDri %fixed-stack.[[FI32]], 0, 14, %noreg, %noreg
 
     %1(s32) = G_LOAD %0(p0) :: (load 4)
-    ; CHECK: [[LD32VREG:%[0-9]+]]:gpr = LDRi12 [[FI32VREG]], 0, 14, _
+    ; CHECK: [[LD32VREG:%[0-9]+]]:gpr = LDRi12 [[FI32VREG]], 0, 14, %noreg
 
     %r0 = COPY %1
     ; CHECK: %r0 = COPY [[LD32VREG]]
 
     %2(p0) = G_FRAME_INDEX %fixed-stack.0
-    ; CHECK: [[FI1VREG:%[0-9]+]]:gpr = ADDri %fixed-stack.[[FI1]], 0, 14, _, _
+    ; CHECK: [[FI1VREG:%[0-9]+]]:gpr = ADDri %fixed-stack.[[FI1]], 0, 14, %noreg, %noreg
 
     %3(s1) = G_LOAD %2(p0) :: (load 1)
-    ; CHECK: [[LD1VREG:%[0-9]+]]:gprnopc = LDRBi12 [[FI1VREG]], 0, 14, _
+    ; CHECK: [[LD1VREG:%[0-9]+]]:gprnopc = LDRBi12 [[FI1VREG]], 0, 14, %noreg
 
     %4(s32) = G_ANYEXT %3(s1)
     ; CHECK: [[RES:%[0-9]+]]:gpr = COPY [[LD1VREG]]
@@ -908,8 +908,8 @@ body:             |
     %r0 = COPY %4
     ; CHECK: %r0 = COPY [[RES]]
 
-    BX_RET 14, _
-    ; CHECK: BX_RET 14, _
+    BX_RET 14, %noreg
+    ; CHECK: BX_RET 14, %noreg
 ...
 ---
 name:            test_load_f32
@@ -929,13 +929,13 @@ body:             |
     ; CHECK: %[[P:[0-9]+]]:gpr = COPY %r0
 
     %1(s32) = G_LOAD %0(p0) :: (load 4)
-    ; CHECK: %[[V:[0-9]+]]:spr = VLDRS %[[P]], 0, 14, _
+    ; CHECK: %[[V:[0-9]+]]:spr = VLDRS %[[P]], 0, 14, %noreg
 
     %s0 = COPY %1
     ; CHECK: %s0 = COPY %[[V]]
 
-    BX_RET 14, _, implicit %s0
-    ; CHECK: BX_RET 14, _, implicit %s0
+    BX_RET 14, %noreg, implicit %s0
+    ; CHECK: BX_RET 14, %noreg, implicit %s0
 ...
 ---
 name:            test_load_f64
@@ -955,13 +955,13 @@ body:             |
     ; CHECK: %[[P:[0-9]+]]:gpr = COPY %r0
 
     %1(s64) = G_LOAD %0(p0) :: (load 8)
-    ; CHECK: %[[V:[0-9]+]]:dpr = VLDRD %[[P]], 0, 14, _
+    ; CHECK: %[[V:[0-9]+]]:dpr = VLDRD %[[P]], 0, 14, %noreg
 
     %d0 = COPY %1
     ; CHECK: %d0 = COPY %[[V]]
 
-    BX_RET 14, _, implicit %d0
-    ; CHECK: BX_RET 14, _, implicit %d0
+    BX_RET 14, %noreg, implicit %d0
+    ; CHECK: BX_RET 14, %noreg, implicit %d0
 ...
 ---
 name:            test_stores
@@ -995,21 +995,21 @@ body:             |
     %2(s16) = G_TRUNC %3(s32)
 
     G_STORE %1(s8), %0(p0) :: (store 1)
-    ; CHECK: STRBi12 %[[I8]], %[[P]], 0, 14, _
+    ; CHECK: STRBi12 %[[I8]], %[[P]], 0, 14, %noreg
 
     G_STORE %2(s16), %0(p0) :: (store 2)
-    ; CHECK: STRH %[[I16]], %[[P]], _, 0, 14, _
+    ; CHECK: STRH %[[I16]], %[[P]], %noreg, 0, 14, %noreg
 
     G_STORE %3(s32), %0(p0) :: (store 4)
-    ; CHECK: STRi12 %[[I32]], %[[P]], 0, 14, _
+    ; CHECK: STRi12 %[[I32]], %[[P]], 0, 14, %noreg
 
     G_STORE %4(s32), %0(p0) :: (store 4)
-    ; CHECK: VSTRS %[[F32]], %[[P]], 0, 14, _
+    ; CHECK: VSTRS %[[F32]], %[[P]], 0, 14, %noreg
 
     G_STORE %5(s64), %0(p0) :: (store 8)
-    ; CHECK: VSTRD %[[F64]], %[[P]], 0, 14, _
+    ; CHECK: VSTRD %[[F64]], %[[P]], 0, 14, %noreg
 
-    BX_RET 14, _
+    BX_RET 14, %noreg
 ...
 ---
 name:            test_gep
@@ -1033,10 +1033,10 @@ body:             |
     ; CHECK: %[[OFF:[0-9]+]]:gpr = COPY %r1
 
     %2(p0) = G_GEP %0, %1(s32)
-    ; CHECK: %[[GEP:[0-9]+]]:gpr = ADDrr %[[PTR]], %[[OFF]], 14, _, _
+    ; CHECK: %[[GEP:[0-9]+]]:gpr = ADDrr %[[PTR]], %[[OFF]], 14, %noreg, %noreg
 
     %r0 = COPY %2(p0)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_constant_imm
@@ -1050,10 +1050,10 @@ registers:
 body:             |
   bb.0:
     %0(s32) = G_CONSTANT 42
-    ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 42, 14, _, _
+    ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 42, 14, %noreg, %noreg
 
     %r0 = COPY %0(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_constant_cimm
@@ -1069,10 +1069,10 @@ body:             |
     ; Adding a type on G_CONSTANT changes its operand from an Imm into a CImm.
     ; We still want to see the same thing in the output though.
     %0(s32) = G_CONSTANT i32 42
-    ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 42, 14, _, _
+    ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 42, 14, %noreg, %noreg
 
     %r0 = COPY %0(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_select_s32
@@ -1100,14 +1100,14 @@ body:             |
     ; CHECK: [[VREGC:%[0-9]+]]:gpr = COPY [[VREGY]]
 
     %3(s32) = G_SELECT %2(s1),  %0, %1
-    ; CHECK: CMPri [[VREGC]], 0, 14, _, implicit-def %cpsr
+    ; CHECK: CMPri [[VREGC]], 0, 14, %noreg, implicit-def %cpsr
     ; CHECK: [[RES:%[0-9]+]]:gpr = MOVCCr [[VREGX]], [[VREGY]], 0, %cpsr
 
     %r0 = COPY %3(s32)
     ; CHECK: %r0 = COPY [[RES]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_select_ptr
@@ -1139,14 +1139,14 @@ body:             |
     ; CHECK: [[VREGD:%[0-9]+]]:gpr = COPY [[VREGC]]
 
     %4(p0) = G_SELECT %3(s1),  %0, %1
-    ; CHECK: CMPri [[VREGD]], 0, 14, _, implicit-def %cpsr
+    ; CHECK: CMPri [[VREGD]], 0, 14, %noreg, implicit-def %cpsr
     ; CHECK: [[RES:%[0-9]+]]:gpr = MOVCCr [[VREGX]], [[VREGY]], 0, %cpsr
 
     %r0 = COPY %4(p0)
     ; CHECK: %r0 = COPY [[RES]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_br
@@ -1170,7 +1170,7 @@ body:             |
     ; CHECK: [[COND:%[0-9]+]]:gpr = COPY [[COND32]]
 
     G_BRCOND %1(s1), %bb.1
-    ; CHECK: TSTri [[COND]], 1, 14, _, implicit-def %cpsr
+    ; CHECK: TSTri [[COND]], 1, 14, %noreg, implicit-def %cpsr
     ; CHECK: Bcc %bb.1, 1, %cpsr
     G_BR %bb.2
     ; CHECK: B %bb.2
@@ -1185,8 +1185,8 @@ body:             |
   bb.2:
   ; CHECK: bb.2
 
-    BX_RET 14, _
-    ; CHECK: BX_RET 14, _
+    BX_RET 14, %noreg
+    ; CHECK: BX_RET 14, %noreg
 ...
 ---
 name:            test_soft_fp_double
@@ -1223,6 +1223,6 @@ body:             |
     %r1 = COPY %4
     ; CHECK: %r1 = COPY [[OUT2]]
 
-    BX_RET 14, _, implicit %r0, implicit %r1
-    ; CHECK: BX_RET 14, _, implicit %r0, implicit %r1
+    BX_RET 14, %noreg, implicit %r0, implicit %r1
+    ; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
 ...

test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll

@@ -3,7 +3,7 @@
 
 define void @test_void_return() {
 ; CHECK-LABEL: name: test_void_return
-; CHECK: BX_RET 14, _
+; CHECK: BX_RET 14, %noreg
 entry:
   ret void
 }
@@ -18,7 +18,7 @@ define signext i1 @test_add_i1(i1 %x, i1 %y) {
 ; CHECK: [[SUM:%[0-9]+]]:_(s1) = G_ADD [[VREGX]], [[VREGY]]
 ; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_SEXT [[SUM]]
 ; CHECK: %r0 = COPY [[EXT]](s32)
-; CHECK: BX_RET 14, _, implicit %r0
+; CHECK: BX_RET 14, %noreg, implicit %r0
 entry:
   %sum = add i1 %x, %y
   ret i1 %sum
@@ -34,7 +34,7 @@ define i8 @test_add_i8(i8 %x, i8 %y) {
 ; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGX]], [[VREGY]]
 ; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
 ; CHECK: %r0 = COPY [[SUM_EXT]](s32)
-; CHECK: BX_RET 14, _, implicit %r0
+; CHECK: BX_RET 14, %noreg, implicit %r0
 entry:
   %sum = add i8 %x, %y
   ret i8 %sum
@@ -50,7 +50,7 @@ define i8 @test_sub_i8(i8 %x, i8 %y) {
 ; CHECK: [[RES:%[0-9]+]]:_(s8) = G_SUB [[VREGX]], [[VREGY]]
 ; CHECK: [[RES_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]]
 ; CHECK: %r0 = COPY [[RES_EXT]](s32)
-; CHECK: BX_RET 14, _, implicit %r0
+; CHECK: BX_RET 14, %noreg, implicit %r0
 entry:
   %res = sub i8 %x, %y
   ret i8 %res
@@ -63,7 +63,7 @@ define signext i8 @test_return_sext_i8(i8 %x) {
 ; CHECK: [[VREG:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR0]]
 ; CHECK: [[VREGEXT:%[0-9]+]]:_(s32) = G_SEXT [[VREG]]
 ; CHECK: %r0 = COPY [[VREGEXT]](s32)
-; CHECK: BX_RET 14, _, implicit %r0
+; CHECK: BX_RET 14, %noreg, implicit %r0
 entry:
   ret i8 %x
 }
@@ -78,7 +78,7 @@ define i16 @test_add_i16(i16 %x, i16 %y) {
 ; CHECK: [[SUM:%[0-9]+]]:_(s16) = G_ADD [[VREGX]], [[VREGY]]
 ; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
 ; CHECK: %r0 = COPY [[SUM_EXT]](s32)
-; CHECK: BX_RET 14, _, implicit %r0
+; CHECK: BX_RET 14, %noreg, implicit %r0
 entry:
   %sum = add i16 %x, %y
   ret i16 %sum
@@ -94,7 +94,7 @@ define i16 @test_sub_i16(i16 %x, i16 %y) {
 ; CHECK: [[RES:%[0-9]+]]:_(s16) = G_SUB [[VREGX]], [[VREGY]]
 ; CHECK: [[RES_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]]
 ; CHECK: %r0 = COPY [[RES_EXT]](s32)
-; CHECK: BX_RET 14, _, implicit %r0
+; CHECK: BX_RET 14, %noreg, implicit %r0
 entry:
   %res = sub i16 %x, %y
   ret i16 %res
@@ -107,7 +107,7 @@ define zeroext i16 @test_return_zext_i16(i16 %x) {
 ; CHECK: [[VREG:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR0]]
 ; CHECK: [[VREGEXT:%[0-9]+]]:_(s32) = G_ZEXT [[VREG]]
 ; CHECK: %r0 = COPY [[VREGEXT]](s32)
-; CHECK: BX_RET 14, _, implicit %r0
+; CHECK: BX_RET 14, %noreg, implicit %r0
 entry:
   ret i16 %x
 }
@@ -119,7 +119,7 @@ define i32 @test_add_i32(i32 %x, i32 %y) {
 ; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s32) = COPY %r1
 ; CHECK: [[SUM:%[0-9]+]]:_(s32) = G_ADD [[VREGX]], [[VREGY]]
 ; CHECK: %r0 = COPY [[SUM]](s32)
-; CHECK: BX_RET 14, _, implicit %r0
+; CHECK: BX_RET 14, %noreg, implicit %r0
 entry:
   %sum = add i32 %x, %y
   ret i32 %sum
@@ -132,7 +132,7 @@ define i32 @test_sub_i32(i32 %x, i32 %y) {
 ; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s32) = COPY %r1
 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_SUB [[VREGX]], [[VREGY]]
 ; CHECK: %r0 = COPY [[RES]](s32)
-; CHECK: BX_RET 14, _, implicit %r0
+; CHECK: BX_RET 14, %noreg, implicit %r0
 entry:
   %res = sub i32 %x, %y
   ret i32 %res
@@ -149,7 +149,7 @@ define i32 @test_stack_args(i32 %p0, i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5
 ; CHECK: [[VREGP5:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]]{{.*}}load 4
 ; CHECK: [[SUM:%[0-9]+]]:_(s32) = G_ADD [[VREGP2]], [[VREGP5]]
 ; CHECK: %r0 = COPY [[SUM]]
-; CHECK: BX_RET 14, _, implicit %r0
+; CHECK: BX_RET 14, %noreg, implicit %r0
 entry:
   %sum = add i32 %p2, %p5
   ret i32 %sum
@@ -170,7 +170,7 @@ define i16 @test_stack_args_signext(i32 %p0, i16 %p1, i8 %p2, i1 %p3,
 ; CHECK: [[SUM:%[0-9]+]]:_(s16) = G_ADD [[VREGP1]], [[VREGP5]]
 ; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
 ; CHECK: %r0 = COPY [[SUM_EXT]](s32)
-; CHECK: BX_RET 14, _, implicit %r0
+; CHECK: BX_RET 14, %noreg, implicit %r0
 entry:
   %sum = add i16 %p1, %p5
   ret i16 %sum
@@ -191,7 +191,7 @@ define i8 @test_stack_args_zeroext(i32 %p0, i16 %p1, i8 %p2, i1 %p3,
 ; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGP2]], [[VREGP4]]
 ; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
 ; CHECK: %r0 = COPY [[SUM_EXT]](s32)
-; CHECK: BX_RET 14, _, implicit %r0
+; CHECK: BX_RET 14, %noreg, implicit %r0
 entry:
   %sum = add i8 %p2, %p4
   ret i8 %sum
@@ -211,7 +211,7 @@ define i8 @test_stack_args_noext(i32 %p0, i16 %p1, i8 %p2, i1 %p3,
 ; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGP2]], [[VREGP4]]
 ; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
 ; CHECK: %r0 = COPY [[SUM_EXT]](s32)
-; CHECK: BX_RET 14, _, implicit %r0
+; CHECK: BX_RET 14, %noreg, implicit %r0
 entry:
   %sum = add i8 %p2, %p4
   ret i8 %sum
@@ -229,7 +229,7 @@ define zeroext i16 @test_stack_args_extend_the_extended(i32 %p0, i16 %p1, i8 %p2
 ; CHECK: [[VREGP5:%[0-9]+]]:_(s16) = G_TRUNC [[VREGP5SEXT]]
 ; CHECK: [[VREGP5ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[VREGP5]]
 ; CHECK: %r0 = COPY [[VREGP5ZEXT]]
-; CHECK: BX_RET 14, _, implicit %r0
+; CHECK: BX_RET 14, %noreg, implicit %r0
 entry:
   ret i16 %p5
 }
@@ -251,7 +251,7 @@ define i32* @test_ptr_ret(i32** %p) {
 ; CHECK: [[VREGP:%[0-9]+]]:_(p0) = COPY %r0
 ; CHECK: [[VREGV:%[0-9]+]]:_(p0) = G_LOAD [[VREGP]](p0){{.*}}load 4
 ; CHECK: %r0 = COPY [[VREGV]]
-; CHECK: BX_RET 14, _, implicit %r0
+; CHECK: BX_RET 14, %noreg, implicit %r0
 entry:
   %v = load i32*, i32** %p
   ret i32* %v
@@ -266,7 +266,7 @@ define i32 @test_ptr_arg_on_stack(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32* %p) {
 ; CHECK: [[VREGP:%[0-9]+]]:_(p0) = G_LOAD [[FIP]](p0){{.*}}load 4
 ; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_LOAD [[VREGP]](p0){{.*}}load 4
 ; CHECK: %r0 = COPY [[VREGV]]
-; CHECK: BX_RET 14, _, implicit %r0
+; CHECK: BX_RET 14, %noreg, implicit %r0
 entry:
   %v = load i32, i32* %p
   ret i32 %v
@@ -284,7 +284,7 @@ define arm_aapcscc float @test_float_aapcscc(float %p0, float %p1, float %p2,
 ; CHECK: [[VREGP5:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]](p0){{.*}}load 4
 ; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_FADD [[VREGP1]], [[VREGP5]]
 ; CHECK: %r0 = COPY [[VREGV]]
-; CHECK: BX_RET 14, _, implicit %r0
+; CHECK: BX_RET 14, %noreg, implicit %r0
 entry:
   %v = fadd float %p1, %p5
   ret float %v
@@ -313,7 +313,7 @@ define arm_aapcs_vfpcc float @test_float_vfpcc(float %p0, float %p1, float %p2,
 ; CHECK: [[VREGQ1:%[0-9]+]]:_(s32) = G_LOAD [[FIQ1]](p0){{.*}}load 4
 ; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_FADD [[VREGP1]], [[VREGQ1]]
 ; CHECK: %s0 = COPY [[VREGV]]
-; CHECK: BX_RET 14, _, implicit %s0
+; CHECK: BX_RET 14, %noreg, implicit %s0
 entry:
   %v = fadd float %p1, %q1
   ret float %v
@@ -334,7 +334,7 @@ define arm_aapcs_vfpcc double @test_double_vfpcc(double %p0, double %p1, double
 ; CHECK: [[VREGQ1:%[0-9]+]]:_(s64) = G_LOAD [[FIQ1]](p0){{.*}}load 8
 ; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP1]], [[VREGQ1]]
 ; CHECK: %d0 = COPY [[VREGV]]
-; CHECK: BX_RET 14, _, implicit %d0
+; CHECK: BX_RET 14, %noreg, implicit %d0
 entry:
   %v = fadd double %p1, %q1
   ret double %v
@@ -360,7 +360,7 @@ define arm_aapcscc double @test_double_aapcscc(double %p0, double %p1, double %p
 ; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
 ; CHECK-DAG: %r0 = COPY [[VREGVLO]]
 ; CHECK-DAG: %r1 = COPY [[VREGVHI]]
-; CHECK: BX_RET 14, _, implicit %r0, implicit %r1
+; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
 entry:
   %v = fadd double %p1, %p5
   ret double %v
@@ -382,7 +382,7 @@ define arm_aapcs_vfpcc double @test_double_gap_vfpcc(double %p0, float %filler,
 ; CHECK: [[VREGQ1:%[0-9]+]]:_(s64) = G_LOAD [[FIQ1]](p0){{.*}}load 8
 ; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP1]], [[VREGQ1]]
 ; CHECK: %d0 = COPY [[VREGV]]
-; CHECK: BX_RET 14, _, implicit %d0
+; CHECK: BX_RET 14, %noreg, implicit %d0
 entry:
   %v = fadd double %p1, %q1
   ret double %v
@@ -405,7 +405,7 @@ define arm_aapcscc double @test_double_gap_aapcscc(float %filler, double %p0,
 ; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
 ; CHECK-DAG: %r0 = COPY [[VREGVLO]]
 ; CHECK-DAG: %r1 = COPY [[VREGVHI]]
-; CHECK: BX_RET 14, _, implicit %r0, implicit %r1
+; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
 entry:
   %v = fadd double %p0, %p1
   ret double %v
@@ -428,7 +428,7 @@ define arm_aapcscc double @test_double_gap2_aapcscc(double %p0, float %filler,
 ; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
 ; CHECK-DAG: %r0 = COPY [[VREGVLO]]
 ; CHECK-DAG: %r1 = COPY [[VREGVHI]]
-; CHECK: BX_RET 14, _, implicit %r0, implicit %r1
+; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
 entry:
   %v = fadd double %p0, %p1
   ret double %v

test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir

@@ -55,7 +55,7 @@ body:             |
     %2(s32) = G_SDIV %0, %1
     ; CHECK: %r0 = COPY [[R]]
     %r0 = COPY %2(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_udiv_i32
@@ -91,7 +91,7 @@ body:             |
     %2(s32) = G_UDIV %0, %1
     ; CHECK: %r0 = COPY [[R]]
     %r0 = COPY %2(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_sdiv_i16
@@ -145,7 +145,7 @@ body:             |
     ; CHECK: %r0 = COPY [[R]]
     %5(s32) = G_SEXT %4(s16)
     %r0 = COPY %5(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_udiv_i16
@@ -197,7 +197,7 @@ body:             |
     ; CHECK: %r0 = COPY [[R]]
     %5(s32) = G_ZEXT %4(s16)
     %r0 = COPY %5(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_sdiv_i8
@@ -251,7 +251,7 @@ body:             |
     ; CHECK: %r0 = COPY [[R]]
     %5(s32) = G_SEXT %4(s8)
     %r0 = COPY %5(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_udiv_i8
@@ -303,7 +303,7 @@ body:             |
     ; CHECK: %r0 = COPY [[R]]
     %5(s32) = G_ZEXT %4(s8)
     %r0 = COPY %5(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_srem_i32
@@ -341,7 +341,7 @@ body:             |
     %2(s32) = G_SREM %0, %1
     ; CHECK: %r0 = COPY [[R]]
     %r0 = COPY %2(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_urem_i32
@@ -379,7 +379,7 @@ body:             |
     %2(s32) = G_UREM %0, %1
     ; CHECK: %r0 = COPY [[R]]
     %r0 = COPY %2(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_srem_i16
@@ -435,7 +435,7 @@ body:             |
     ; CHECK: %r0 = COPY [[R]]
     %5(s32) = G_SEXT %4(s16)
     %r0 = COPY %5(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_urem_i16
@@ -489,7 +489,7 @@ body:             |
     ; CHECK: %r0 = COPY [[R]]
     %5(s32) = G_ZEXT %4(s16)
     %r0 = COPY %5(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_srem_i8
@@ -545,7 +545,7 @@ body:             |
     ; CHECK: %r0 = COPY [[R]]
     %5(s32) = G_SEXT %4(s8)
     %r0 = COPY %5(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_urem_i8
@@ -599,5 +599,5 @@ body:             |
     ; CHECK: %r0 = COPY [[R]]
     %5(s32) = G_ZEXT %4(s8)
     %r0 = COPY %5(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...

test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir

@@ -93,7 +93,7 @@ body:             |
     %2(s32) = G_FREM %0, %1
     ; CHECK: %r0 = COPY [[R]]
     %r0 = COPY %2(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_frem_double
@@ -151,7 +151,7 @@ body:             |
     %7(s32), %8(s32) = G_UNMERGE_VALUES %6(s64)
     %r0 = COPY %7(s32)
     %r1 = COPY %8(s32)
-    BX_RET 14, _, implicit %r0, implicit %r1
+    BX_RET 14, %noreg, implicit %r0, implicit %r1
 ...
 ---
 name:            test_fpow_float
@@ -188,7 +188,7 @@ body:             |
     %2(s32) = G_FPOW %0, %1
     ; CHECK: %r0 = COPY [[R]]
     %r0 = COPY %2(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_fpow_double
@@ -246,7 +246,7 @@ body:             |
     %7(s32), %8(s32) = G_UNMERGE_VALUES %6(s64)
     %r0 = COPY %7(s32)
     %r1 = COPY %8(s32)
-    BX_RET 14, _, implicit %r0, implicit %r1
+    BX_RET 14, %noreg, implicit %r0, implicit %r1
 ...
 ---
 name:            test_fadd_float
@@ -281,7 +281,7 @@ body:             |
     %2(s32) = G_FADD %0, %1
     ; CHECK: %r0 = COPY [[R]]
     %r0 = COPY %2(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_fadd_double
@@ -333,7 +333,7 @@ body:             |
     %7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64)
     %r0 = COPY %7(s32)
     %r1 = COPY %8(s32)
-    BX_RET 14, _, implicit %r0, implicit %r1
+    BX_RET 14, %noreg, implicit %r0, implicit %r1
 ...
 ---
 name:            test_fsub_float
@@ -368,7 +368,7 @@ body:             |
     %2(s32) = G_FSUB %0, %1
     ; CHECK: %r0 = COPY [[R]]
     %r0 = COPY %2(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_fsub_double
@@ -420,7 +420,7 @@ body:             |
     %7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64)
     %r0 = COPY %7(s32)
     %r1 = COPY %8(s32)
-    BX_RET 14, _, implicit %r0, implicit %r1
+    BX_RET 14, %noreg, implicit %r0, implicit %r1
 ...
 ---
 name:            test_fmul_float
@@ -455,7 +455,7 @@ body:             |
     %2(s32) = G_FMUL %0, %1
     ; CHECK: %r0 = COPY [[R]]
     %r0 = COPY %2(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_fmul_double
@@ -507,7 +507,7 @@ body:             |
     %7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64)
     %r0 = COPY %7(s32)
     %r1 = COPY %8(s32)
-    BX_RET 14, _, implicit %r0, implicit %r1
+    BX_RET 14, %noreg, implicit %r0, implicit %r1
 ...
 ---
 name:            test_fdiv_float
@@ -542,7 +542,7 @@ body:             |
     %2(s32) = G_FDIV %0, %1
     ; CHECK: %r0 = COPY [[R]]
     %r0 = COPY %2(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_fdiv_double
@@ -594,7 +594,7 @@ body:             |
     %7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64)
     %r0 = COPY %7(s32)
     %r1 = COPY %8(s32)
-    BX_RET 14, _, implicit %r0, implicit %r1
+    BX_RET 14, %noreg, implicit %r0, implicit %r1
 ...
 ---
 name:            test_fcmp_true_s32
@@ -618,7 +618,7 @@ body:             |
     %2(s1) = G_FCMP floatpred(true), %0(s32), %1
     %3(s32) = G_ZEXT %2(s1)
     %r0 = COPY %3(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
     ; HARD-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
     ; HARD-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
     ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(true), [[X]](s32), [[Y]]
@@ -655,7 +655,7 @@ body:             |
     %2(s1) = G_FCMP floatpred(false), %0(s32), %1
     %3(s32) = G_ZEXT %2(s1)
     %r0 = COPY %3(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
     ; HARD-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
     ; HARD-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
     ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(false), [[X]](s32), [[Y]]
@@ -714,7 +714,7 @@ body:             |
     %3(s32) = G_ZEXT %2(s1)
     %r0 = COPY %3(s32)
     ; CHECK: %r0 = COPY [[REXT]]
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_fcmp_ogt_s32
@@ -760,7 +760,7 @@ body:             |
     %3(s32) = G_ZEXT %2(s1)
     %r0 = COPY %3(s32)
     ; CHECK: %r0 = COPY [[REXT]]
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_fcmp_oge_s32
@@ -806,7 +806,7 @@ body:             |
     %3(s32) = G_ZEXT %2(s1)
     %r0 = COPY %3(s32)
     ; CHECK: %r0 = COPY [[REXT]]
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_fcmp_olt_s32
@@ -852,7 +852,7 @@ body:             |
     %3(s32) = G_ZEXT %2(s1)
     %r0 = COPY %3(s32)
     ; CHECK: %r0 = COPY [[REXT]]
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_fcmp_ole_s32
@@ -898,7 +898,7 @@ body:             |
     %3(s32) = G_ZEXT %2(s1)
     %r0 = COPY %3(s32)
     ; CHECK: %r0 = COPY [[REXT]]
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_fcmp_ord_s32
@@ -938,7 +938,7 @@ body:             |
     ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %3(s32)
     ; CHECK: %r0 = COPY [[REXT]]
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_fcmp_ugt_s32
@@ -979,7 +979,7 @@ body:             |
     ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %3(s32)
     ; CHECK: %r0 = COPY [[REXT]]
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_fcmp_uge_s32
@@ -1020,7 +1020,7 @@ body:             |
     ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %3(s32)
     ; CHECK: %r0 = COPY [[REXT]]
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_fcmp_ult_s32
@@ -1061,7 +1061,7 @@ body:             |
     ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %3(s32)
     ; CHECK: %r0 = COPY [[REXT]]
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_fcmp_ule_s32
@@ -1102,7 +1102,7 @@ body:             |
     ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %3(s32)
     ; CHECK: %r0 = COPY [[REXT]]
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_fcmp_une_s32
@@ -1143,7 +1143,7 @@ body:             |
     ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %3(s32)
     ; CHECK: %r0 = COPY [[REXT]]
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_fcmp_uno_s32
@@ -1189,7 +1189,7 @@ body:             |
     %3(s32) = G_ZEXT %2(s1)
     %r0 = COPY %3(s32)
     ; CHECK: %r0 = COPY [[REXT]]
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_fcmp_one_s32
@@ -1249,7 +1249,7 @@ body:             |
     %3(s32) = G_ZEXT %2(s1)
     %r0 = COPY %3(s32)
     ; CHECK: %r0 = COPY [[REXT]]
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_fcmp_ueq_s32
@@ -1309,7 +1309,7 @@ body:             |
     %3(s32) = G_ZEXT %2(s1)
     %r0 = COPY %3(s32)
     ; CHECK: %r0 = COPY [[REXT]]
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_fcmp_true_s64
@@ -1358,7 +1358,7 @@ body:             |
     %7(s32) = G_ZEXT %6(s1)
     %r0 = COPY %7(s32)
     ; CHECK: %r0 = COPY [[REXT]]
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_fcmp_false_s64
@@ -1408,7 +1408,7 @@ body:             |
     %7(s32) = G_ZEXT %6(s1)
     %r0 = COPY %7(s32)
     ; CHECK: %r0 = COPY [[REXT]]
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_fcmp_oeq_s64
@@ -1468,7 +1468,7 @@ body:             |
     %7(s32) = G_ZEXT %6(s1)
     %r0 = COPY %7(s32)
     ; CHECK: %r0 = COPY [[REXT]]
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_fcmp_ogt_s64
@@ -1528,7 +1528,7 @@ body:             |
     %7(s32) = G_ZEXT %6(s1)
     %r0 = COPY %7(s32)
     ; CHECK: %r0 = COPY [[REXT]]
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_fcmp_oge_s64
@@ -1588,7 +1588,7 @@ body:             |
     %7(s32) = G_ZEXT %6(s1)
     %r0 = COPY %7(s32)
     ; CHECK: %r0 = COPY [[REXT]]
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_fcmp_olt_s64
@@ -1648,7 +1648,7 @@ body:             |
     %7(s32) = G_ZEXT %6(s1)
     %r0 = COPY %7(s32)
     ; CHECK: %r0 = COPY [[REXT]]
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_fcmp_ole_s64
@@ -1708,7 +1708,7 @@ body:             |
     %7(s32) = G_ZEXT %6(s1)
     %r0 = COPY %7(s32)
     ; CHECK: %r0 = COPY [[REXT]]
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_fcmp_ord_s64
@@ -1762,7 +1762,7 @@ body:             |
     ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %7(s32)
     ; CHECK: %r0 = COPY [[REXT]]
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_fcmp_ugt_s64
@@ -1817,7 +1817,7 @@ body:             |
     ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %7(s32)
     ; CHECK: %r0 = COPY [[REXT]]
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_fcmp_uge_s64
@@ -1872,7 +1872,7 @@ body:             |
     ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %7(s32)
     ; CHECK: %r0 = COPY [[REXT]]
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_fcmp_ult_s64
@@ -1927,7 +1927,7 @@ body:             |
     ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %7(s32)
     ; CHECK: %r0 = COPY [[REXT]]
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_fcmp_ule_s64
@@ -1982,7 +1982,7 @@ body:             |
     ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %7(s32)
     ; CHECK: %r0 = COPY [[REXT]]
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_fcmp_une_s64
@@ -2037,7 +2037,7 @@ body:             |
     ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %7(s32)
     ; CHECK: %r0 = COPY [[REXT]]
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_fcmp_uno_s64
@@ -2097,7 +2097,7 @@ body:             |
     %7(s32) = G_ZEXT %6(s1)
     %r0 = COPY %7(s32)
     ; CHECK: %r0 = COPY [[REXT]]
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_fcmp_one_s64
@@ -2173,7 +2173,7 @@ body:             |
     %7(s32) = G_ZEXT %6(s1)
     %r0 = COPY %7(s32)
     ; CHECK: %r0 = COPY [[REXT]]
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_fcmp_ueq_s64
@@ -2249,5 +2249,5 @@ body:             |
     %7(s32) = G_ZEXT %6(s1)
     %r0 = COPY %7(s32)
     ; CHECK: %r0 = COPY [[REXT]]
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...

test/CodeGen/ARM/GlobalISel/arm-legalizer.mir

@@ -74,7 +74,7 @@ body:             |
     ; G_SEXT with s8 is legal, so we should find it unchanged in the output
     ; CHECK: {{%[0-9]+}}:_(s32) = G_SEXT {{%[0-9]+}}
     %r0 = COPY %2(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_zext_s16
@@ -98,7 +98,7 @@ body:             |
     ; G_ZEXT with s16 is legal, so we should find it unchanged in the output
     ; CHECK: {{%[0-9]+}}:_(s32) = G_ZEXT {{%[0-9]+}}
     %r0 = COPY %2(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_add_s8
@@ -130,7 +130,7 @@ body:             |
     ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_ADD {{%[0-9]+, %[0-9]+}}
     %5(s32) = G_SEXT %4(s8)
     %r0 = COPY %5(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_add_s16
@@ -162,7 +162,7 @@ body:             |
     ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_ADD {{%[0-9]+, %[0-9]+}}
     %5(s32) = G_SEXT %4(s16)
     %r0 = COPY %5(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_add_s32
@@ -186,7 +186,7 @@ body:             |
     ; G_ADD with s32 is legal, so we should find it unchanged in the output
     ; CHECK: {{%[0-9]+}}:_(s32) = G_ADD {{%[0-9]+, %[0-9]+}}
     %r0 = COPY %2(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 
 ...
 ---
@@ -219,7 +219,7 @@ body:             |
     ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_SUB {{%[0-9]+, %[0-9]+}}
     %5(s32) = G_SEXT %4(s8)
     %r0 = COPY %5(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_sub_s16
@@ -251,7 +251,7 @@ body:             |
     ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_SUB {{%[0-9]+, %[0-9]+}}
     %5(s32) = G_SEXT %4(s16)
     %r0 = COPY %5(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_sub_s32
@@ -275,7 +275,7 @@ body:             |
     ; G_SUB with s32 is legal, so we should find it unchanged in the output
     ; CHECK: {{%[0-9]+}}:_(s32) = G_SUB {{%[0-9]+, %[0-9]+}}
     %r0 = COPY %2(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 
 ...
 ---
@@ -308,7 +308,7 @@ body:             |
     ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_MUL {{%[0-9]+, %[0-9]+}}
     %5(s32) = G_SEXT %4(s8)
     %r0 = COPY %5(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_mul_s16
@@ -340,7 +340,7 @@ body:             |
     ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_MUL {{%[0-9]+, %[0-9]+}}
     %5(s32) = G_SEXT %4(s16)
     %r0 = COPY %5(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_mul_s32
@@ -364,7 +364,7 @@ body:             |
     ; G_MUL with s32 is legal, so we should find it unchanged in the output
     ; CHECK: {{%[0-9]+}}:_(s32) = G_MUL {{%[0-9]+, %[0-9]+}}
     %r0 = COPY %2(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 
 ...
 ---
@@ -397,7 +397,7 @@ body:             |
     ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_AND {{%[0-9]+, %[0-9]+}}
     %5(s32) = G_SEXT %4(s8)
     %r0 = COPY %5(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_and_s16
@@ -429,7 +429,7 @@ body:             |
     ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_AND {{%[0-9]+, %[0-9]+}}
     %5(s32) = G_SEXT %4(s16)
     %r0 = COPY %5(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_and_s32
@@ -453,7 +453,7 @@ body:             |
     ; G_AND with s32 is legal, so we should find it unchanged in the output
     ; CHECK: {{%[0-9]+}}:_(s32) = G_AND {{%[0-9]+, %[0-9]+}}
     %r0 = COPY %2(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 
 ...
 ---
@@ -486,7 +486,7 @@ body:             |
     ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_OR {{%[0-9]+, %[0-9]+}}
     %5(s32) = G_SEXT %4(s8)
     %r0 = COPY %5(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_or_s16
@@ -518,7 +518,7 @@ body:             |
     ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_OR {{%[0-9]+, %[0-9]+}}
     %5(s32) = G_SEXT %4(s16)
     %r0 = COPY %5(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_or_s32
@@ -542,7 +542,7 @@ body:             |
     ; G_OR with s32 is legal, so we should find it unchanged in the output
     ; CHECK: {{%[0-9]+}}:_(s32) = G_OR {{%[0-9]+, %[0-9]+}}
     %r0 = COPY %2(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 
 ...
 ---
@@ -575,7 +575,7 @@ body:             |
     ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_XOR {{%[0-9]+, %[0-9]+}}
     %5(s32) = G_SEXT %4(s8)
     %r0 = COPY %5(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_xor_s16
@@ -607,7 +607,7 @@ body:             |
     ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_XOR {{%[0-9]+, %[0-9]+}}
     %5(s32) = G_SEXT %4(s16)
     %r0 = COPY %5(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_xor_s32
@@ -631,7 +631,7 @@ body:             |
     ; G_XOR with s32 is legal, so we should find it unchanged in the output
     ; CHECK: {{%[0-9]+}}:_(s32) = G_XOR {{%[0-9]+, %[0-9]+}}
     %r0 = COPY %2(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 
 ...
 ---
@@ -656,7 +656,7 @@ body:             |
     ; G_LSHR with s32 is legal, so we should find it unchanged in the output
     ; CHECK: {{%[0-9]+}}:_(s32) = G_LSHR {{%[0-9]+, %[0-9]+}}
     %r0 = COPY %2(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 
 ...
 ---
@@ -681,7 +681,7 @@ body:             |
     ; G_ASHR with s32 is legal, so we should find it unchanged in the output
     ; CHECK: {{%[0-9]+}}:_(s32) = G_ASHR {{%[0-9]+, %[0-9]+}}
     %r0 = COPY %2(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 
 ...
 ---
@@ -706,7 +706,7 @@ body:             |
     ; G_SHL with s32 is legal, so we should find it unchanged in the output
     ; CHECK: {{%[0-9]+}}:_(s32) = G_SHL {{%[0-9]+, %[0-9]+}}
     %r0 = COPY %2(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 
 ...
 ---
@@ -737,7 +737,7 @@ body:             |
     %0(p0) = G_FRAME_INDEX %fixed-stack.2
     %1(s32) = G_LOAD %0(p0) :: (load 4)
     %r0 = COPY %1(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_legal_loads_stores
@@ -785,7 +785,7 @@ body:             |
     G_STORE %5(s1), %0(p0) :: (store 1)
     %6(p0) = G_LOAD %0(p0) :: (load 4)
     G_STORE %6(p0), %0(p0) :: (store 4)
-    BX_RET 14, _
+    BX_RET 14, %noreg
 ...
 ---
 name:            test_gep
@@ -810,7 +810,7 @@ body:             |
     %2(p0) = G_GEP %0, %1(s32)
 
     %r0 = COPY %2(p0)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_constants
@@ -857,7 +857,7 @@ body:             |
     ; CHECK-NOT: G_CONSTANT i1
 
     %r0 = COPY %0(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_icmp_s8
@@ -888,7 +888,7 @@ body:             |
     ; CHECK-NOT: {{%[0-9]+}}:_(s1) = G_ICMP intpred(ne), {{%[0-9]+}}(s8), {{%[0-9]+}}
     %5(s32) = G_ZEXT %4(s1)
     %r0 = COPY %5(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_icmp_s16
@@ -919,7 +919,7 @@ body:             |
     ; CHECK-NOT: {{%[0-9]+}}:_(s1) = G_ICMP intpred(slt), {{%[0-9]+}}(s16), {{%[0-9]+}}
     %5(s32) = G_ZEXT %4(s1)
     %r0 = COPY %5(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_icmp_s32
@@ -945,7 +945,7 @@ body:             |
     ; CHECK: {{%[0-9]+}}:_(s1) = G_ICMP intpred(eq), {{%[0-9]+}}(s32), {{%[0-9]+}}
     %3(s32) = G_ZEXT %2(s1)
     %r0 = COPY %3(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_select_s32
@@ -971,7 +971,7 @@ body:             |
     ; G_SELECT with s32 is legal, so we should find it unchanged in the output
     ; CHECK: {{%[0-9]+}}:_(s32) = G_SELECT {{%[0-9]+}}(s1), {{%[0-9]+}}, {{%[0-9]+}}
     %r0 = COPY %3(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_select_ptr
@@ -997,7 +997,7 @@ body:             |
     ; G_SELECT with p0 is legal, so we should find it unchanged in the output
     ; CHECK: {{%[0-9]+}}:_(p0) = G_SELECT {{%[0-9]+}}(s1), {{%[0-9]+}}, {{%[0-9]+}}
     %r0 = COPY %3(p0)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_brcond
@@ -1026,11 +1026,11 @@ body:             |
 
   bb.1:
     %r0 = COPY %1(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 
   bb.2:
     %r0 = COPY %0(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 
 ...
 ---
@@ -1053,6 +1053,6 @@ body:             |
     ; G_GLOBAL_VALUE is legal, so we should find it unchanged in the output
     ; CHECK: {{%[0-9]+}}:_(p0) = G_GLOBAL_VALUE @a_global
     %r0 = COPY %1(p0)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 
 ...

test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll

@@ -7,14 +7,14 @@ define arm_aapcscc i32* @test_call_simple_reg_params(i32 *%a, i32 %b) {
 ; CHECK-LABEL: name: test_call_simple_reg_params
 ; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY %r0
 ; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY %r1
-; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
 ; CHECK-DAG: %r0 = COPY [[BVREG]]
 ; CHECK-DAG: %r1 = COPY [[AVREG]]
 ; CHECK: BL @simple_reg_params_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit-def %r0
 ; CHECK: [[RVREG:%[0-9]+]]:_(p0) = COPY %r0
-; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
 ; CHECK: %r0 = COPY [[RVREG]]
-; CHECK: BX_RET 14, _, implicit %r0
+; CHECK: BX_RET 14, %noreg, implicit %r0
 entry:
   %r = notail call arm_aapcscc i32 *@simple_reg_params_target(i32 %b, i32 *%a)
   ret i32 *%r
@@ -26,7 +26,7 @@ define arm_aapcscc i32* @test_call_simple_stack_params(i32 *%a, i32 %b) {
 ; CHECK-LABEL: name: test_call_simple_stack_params
 ; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY %r0
 ; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY %r1
-; CHECK: ADJCALLSTACKDOWN 8, 0, 14, _, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKDOWN 8, 0, 14, %noreg, implicit-def %sp, implicit %sp
 ; CHECK-DAG: %r0 = COPY [[BVREG]]
 ; CHECK-DAG: %r1 = COPY [[AVREG]]
 ; CHECK-DAG: %r2 = COPY [[BVREG]]
@@ -41,9 +41,9 @@ define arm_aapcscc i32* @test_call_simple_stack_params(i32 *%a, i32 %b) {
 ; CHECK: G_STORE [[AVREG]](p0), [[FI2]](p0){{.*}}store 4
 ; CHECK: BL @simple_stack_params_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
 ; CHECK: [[RVREG:%[0-9]+]]:_(p0) = COPY %r0
-; CHECK: ADJCALLSTACKUP 8, 0, 14, _, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKUP 8, 0, 14, %noreg, implicit-def %sp, implicit %sp
 ; CHECK: %r0 = COPY [[RVREG]]
-; CHECK: BX_RET 14, _, implicit %r0
+; CHECK: BX_RET 14, %noreg, implicit %r0
 entry:
   %r = notail call arm_aapcscc i32 *@simple_stack_params_target(i32 %b, i32 *%a, i32 %b, i32 *%a, i32 %b, i32 *%a)
   ret i32 *%r
@@ -59,7 +59,7 @@ define arm_aapcscc signext i16 @test_call_ext_params(i8 %a, i16 %b, i1 %c) {
 ; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s16) = G_TRUNC [[R1VREG]]
 ; CHECK-DAG: [[R2VREG:%[0-9]+]]:_(s32) = COPY %r2
 ; CHECK-DAG: [[CVREG:%[0-9]+]]:_(s1) = G_TRUNC [[R2VREG]]
-; CHECK: ADJCALLSTACKDOWN 20, 0, 14, _, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKDOWN 20, 0, 14, %noreg, implicit-def %sp, implicit %sp
 ; CHECK: [[SEXTA:%[0-9]+]]:_(s32) = G_SEXT [[AVREG]](s8)
 ; CHECK: %r0 = COPY [[SEXTA]]
 ; CHECK: [[ZEXTA:%[0-9]+]]:_(s32) = G_ZEXT [[AVREG]](s8)
@@ -96,10 +96,10 @@ define arm_aapcscc signext i16 @test_call_ext_params(i8 %a, i16 %b, i1 %c) {
 ; CHECK: BL @ext_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
 ; CHECK: [[R0VREG:%[0-9]+]]:_(s32) = COPY %r0
 ; CHECK: [[RVREG:%[0-9]+]]:_(s16) = G_TRUNC [[R0VREG]]
-; CHECK: ADJCALLSTACKUP 20, 0, 14, _, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKUP 20, 0, 14, %noreg, implicit-def %sp, implicit %sp
 ; CHECK: [[RExtVREG:%[0-9]+]]:_(s32) = G_SEXT [[RVREG]]
 ; CHECK: %r0 = COPY [[RExtVREG]]
-; CHECK: BX_RET 14, _, implicit %r0
+; CHECK: BX_RET 14, %noreg, implicit %r0
 entry:
   %r = notail call arm_aapcscc signext i16 @ext_target(i8 signext %a, i8 zeroext %a, i16 signext %b, i16 zeroext %b, i8 signext %a, i8 zeroext %a, i16 signext %b, i16 zeroext %b, i1 zeroext %c)
   ret i16 %r
@@ -111,14 +111,14 @@ define arm_aapcs_vfpcc double @test_call_vfpcc_fp_params(double %a, float %b) {
 ; CHECK-LABEL: name: test_call_vfpcc_fp_params
 ; CHECK-DAG: [[AVREG:%[0-9]+]]:_(s64) = COPY %d0
 ; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY %s2
-; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
 ; CHECK-DAG: %s0 = COPY [[BVREG]]
 ; CHECK-DAG: %d1 = COPY [[AVREG]]
 ; CHECK: BL @vfpcc_fp_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %s0, implicit %d1, implicit-def %d0
 ; CHECK: [[RVREG:%[0-9]+]]:_(s64) = COPY %d0
-; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
 ; CHECK: %d0 = COPY [[RVREG]]
-; CHECK: BX_RET 14, _, implicit %d0
+; CHECK: BX_RET 14, %noreg, implicit %d0
 entry:
   %r = notail call arm_aapcs_vfpcc double @vfpcc_fp_target(float %b, double %a)
   ret double %r
@@ -133,7 +133,7 @@ define arm_aapcscc double @test_call_aapcs_fp_params(double %a, float %b) {
 ; LITTLE-DAG: [[AVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[A1]](s32), [[A2]](s32)
 ; BIG-DAG: [[AVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[A2]](s32), [[A1]](s32)
 ; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY %r2
-; CHECK: ADJCALLSTACKDOWN 16, 0, 14, _, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKDOWN 16, 0, 14, %noreg, implicit-def %sp, implicit %sp
 ; CHECK-DAG: %r0 = COPY [[BVREG]]
 ; CHECK-DAG: [[A1:%[0-9]+]]:_(s32), [[A2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AVREG]](s64)
 ; LITTLE-DAG: %r2 = COPY [[A1]]
@@ -153,13 +153,13 @@ define arm_aapcscc double @test_call_aapcs_fp_params(double %a, float %b) {
 ; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY %r1
 ; LITTLE: [[RVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R1]](s32), [[R2]](s32)
 ; BIG: [[RVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R2]](s32), [[R1]](s32)
-; CHECK: ADJCALLSTACKUP 16, 0, 14, _, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKUP 16, 0, 14, %noreg, implicit-def %sp, implicit %sp
 ; CHECK: [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[RVREG]](s64)
 ; LITTLE-DAG: %r0 = COPY [[R1]]
 ; LITTLE-DAG: %r1 = COPY [[R2]]
 ; BIG-DAG: %r0 = COPY [[R2]]
 ; BIG-DAG: %r1 = COPY [[R1]]
-; CHECK: BX_RET 14, _, implicit %r0, implicit %r1
+; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
 entry:
   %r = notail call arm_aapcscc double @aapcscc_fp_target(float %b, double %a, float %b, double %a)
   ret double %r
@@ -170,13 +170,13 @@ declare arm_aapcscc float @different_call_conv_target(float)
 define arm_aapcs_vfpcc float @test_call_different_call_conv(float %x) {
 ; CHECK-LABEL: name: test_call_different_call_conv
 ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY %s0
-; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
 ; CHECK: %r0 = COPY [[X]]
 ; CHECK: BL @different_call_conv_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit-def %r0
 ; CHECK: [[R:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
 ; CHECK: %s0 = COPY [[R]]
-; CHECK: BX_RET 14, _, implicit %s0
+; CHECK: BX_RET 14, %noreg, implicit %s0
 entry:
   %r = notail call arm_aapcscc float @different_call_conv_target(float %x)
   ret float %r
@@ -190,7 +190,7 @@ define arm_aapcscc [3 x i32] @test_tiny_int_arrays([2 x i32] %arr) {
 ; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0
 ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
 ; CHECK: [[ARG_ARR:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
-; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
 ; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR]](s64)
 ; CHECK: %r0 = COPY [[R0]]
 ; CHECK: %r1 = COPY [[R1]]
@@ -199,7 +199,7 @@ define arm_aapcscc [3 x i32] @test_tiny_int_arrays([2 x i32] %arr) {
 ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
 ; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY %r2
 ; CHECK: [[RES_ARR:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32)
-; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
 ; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[RES_ARR]](s96)
 ; FIXME: This doesn't seem correct with regard to the AAPCS docs (which say
 ; that composite types larger than 4 bytes should be passed through memory),
@@ -207,7 +207,7 @@ define arm_aapcscc [3 x i32] @test_tiny_int_arrays([2 x i32] %arr) {
 ; CHECK: %r0 = COPY [[R0]]
 ; CHECK: %r1 = COPY [[R1]]
 ; CHECK: %r2 = COPY [[R2]]
-; CHECK: BX_RET 14, _, implicit %r0, implicit %r1, implicit %r2
+; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1, implicit %r2
 entry:
   %r = notail call arm_aapcscc [3 x i32] @tiny_int_arrays_target([2 x i32] %arr)
   ret [3 x i32] %r
@@ -224,7 +224,7 @@ define arm_aapcscc void @test_multiple_int_arrays([2 x i32] %arr0, [2 x i32] %ar
 ; CHECK: [[R3:%[0-9]+]]:_(s32) = COPY %r3
 ; CHECK: [[ARG_ARR0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
 ; CHECK: [[ARG_ARR1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R2]](s32), [[R3]](s32)
-; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
 ; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR0]](s64)
 ; CHECK: [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR1]](s64)
 ; CHECK: %r0 = COPY [[R0]]
@@ -232,8 +232,8 @@ define arm_aapcscc void @test_multiple_int_arrays([2 x i32] %arr0, [2 x i32] %ar
 ; CHECK: %r2 = COPY [[R2]]
 ; CHECK: %r3 = COPY [[R3]]
 ; CHECK: BL @multiple_int_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3
-; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp
-; CHECK: BX_RET 14, _
+; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
+; CHECK: BX_RET 14, %noreg
 entry:
   notail call arm_aapcscc void @multiple_int_arrays_target([2 x i32] %arr0, [2 x i32] %arr1)
   ret void
@@ -258,7 +258,7 @@ define arm_aapcscc void @test_large_int_arrays([20 x i32] %arr) {
 ; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]]
 ; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[LAST_STACK_ID]]
 ; CHECK: [[ARG_ARR:%[0-9]+]]:_(s640) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32), [[R3]](s32), [[FIRST_STACK_ELEMENT]](s32), {{.*}}, [[LAST_STACK_ELEMENT]](s32)
-; CHECK: ADJCALLSTACKDOWN 64, 0, 14, _, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKDOWN 64, 0, 14, %noreg, implicit-def %sp, implicit %sp
 ; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32), [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32), {{.*}}, [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR]](s640)
 ; CHECK: %r0 = COPY [[R0]]
 ; CHECK: %r1 = COPY [[R1]]
@@ -275,8 +275,8 @@ define arm_aapcscc void @test_large_int_arrays([20 x i32] %arr) {
 ; CHECK: [[LAST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF_LAST_ELEMENT]](s32)
 ; CHECK: G_STORE [[LAST_STACK_ELEMENT]](s32), [[LAST_STACK_ARG_ADDR]]{{.*}}store 4
 ; CHECK: BL @large_int_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3
-; CHECK: ADJCALLSTACKUP 64, 0, 14, _, implicit-def %sp, implicit %sp
-; CHECK: BX_RET 14, _
+; CHECK: ADJCALLSTACKUP 64, 0, 14, %noreg, implicit-def %sp, implicit %sp
+; CHECK: BX_RET 14, %noreg
 entry:
   notail call arm_aapcscc void @large_int_arrays_target([20 x i32] %arr)
   ret void
@@ -300,7 +300,7 @@ define arm_aapcscc [2 x float] @test_fp_arrays_aapcs([3 x double] %arr) {
 ; CHECK: [[ARR2_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[ARR2_ID]]
 ; CHECK: [[ARR2:%[0-9]+]]:_(s64) = G_LOAD [[ARR2_FI]]{{.*}}load 8 from %fixed-stack.[[ARR2_ID]]
 ; CHECK: [[ARR_MERGED:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[ARR0]](s64), [[ARR1]](s64), [[ARR2]](s64)
-; CHECK: ADJCALLSTACKDOWN 8, 0, 14, _, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKDOWN 8, 0, 14, %noreg, implicit-def %sp, implicit %sp
 ; CHECK: [[ARR0:%[0-9]+]]:_(s64), [[ARR1:%[0-9]+]]:_(s64), [[ARR2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ARR_MERGED]](s192)
 ; CHECK: [[ARR0_0:%[0-9]+]]:_(s32), [[ARR0_1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARR0]](s64)
 ; LITTLE: %r0 = COPY [[ARR0_0]](s32)
@@ -320,11 +320,11 @@ define arm_aapcscc [2 x float] @test_fp_arrays_aapcs([3 x double] %arr) {
 ; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0
 ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
 ; CHECK: [[R_MERGED:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
-; CHECK: ADJCALLSTACKUP 8, 0, 14, _, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKUP 8, 0, 14, %noreg, implicit-def %sp, implicit %sp
 ; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[R_MERGED]](s64)
 ; CHECK: %r0 = COPY [[R0]]
 ; CHECK: %r1 = COPY [[R1]]
-; CHECK: BX_RET 14, _, implicit %r0, implicit %r1
+; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
 entry:
   %r = notail call arm_aapcscc [2 x float] @fp_arrays_aapcs_target([3 x double] %arr)
   ret [2 x float] %r
@@ -357,7 +357,7 @@ define arm_aapcs_vfpcc [4 x float] @test_fp_arrays_aapcs_vfp([3 x double] %x, [3
 ; CHECK: [[X_ARR:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[X0]](s64), [[X1]](s64), [[X2]](s64)
 ; CHECK: [[Y_ARR:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32), [[Y2]](s32)
 ; CHECK: [[Z_ARR:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[Z0]](s64), [[Z1]](s64), [[Z2]](s64), [[Z3]](s64)
-; CHECK: ADJCALLSTACKDOWN 32, 0, 14, _, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKDOWN 32, 0, 14, %noreg, implicit-def %sp, implicit %sp
 ; CHECK: [[X0:%[0-9]+]]:_(s64), [[X1:%[0-9]+]]:_(s64), [[X2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[X_ARR]](s192)
 ; CHECK: [[Y0:%[0-9]+]]:_(s32), [[Y1:%[0-9]+]]:_(s32), [[Y2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[Y_ARR]](s96)
 ; CHECK: [[Z0:%[0-9]+]]:_(s64), [[Z1:%[0-9]+]]:_(s64), [[Z2:%[0-9]+]]:_(s64), [[Z3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[Z_ARR]](s256)
@@ -389,13 +389,13 @@ define arm_aapcs_vfpcc [4 x float] @test_fp_arrays_aapcs_vfp([3 x double] %x, [3
 ; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY %s2
 ; CHECK: [[R3:%[0-9]+]]:_(s32) = COPY %s3
 ; CHECK: [[R_MERGED:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32), [[R3]](s32)
-; CHECK: ADJCALLSTACKUP 32, 0, 14, _, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKUP 32, 0, 14, %noreg, implicit-def %sp, implicit %sp
 ; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[R_MERGED]](s128)
 ; CHECK: %s0 = COPY [[R0]]
 ; CHECK: %s1 = COPY [[R1]]
 ; CHECK: %s2 = COPY [[R2]]
 ; CHECK: %s3 = COPY [[R3]]
-; CHECK: BX_RET 14, _, implicit %s0, implicit %s1, implicit %s2, implicit %s3
+; CHECK: BX_RET 14, %noreg, implicit %s0, implicit %s1, implicit %s2, implicit %s3
 entry:
   %r = notail call arm_aapcs_vfpcc [4 x float] @fp_arrays_aapcs_vfp_target([3 x double] %x, [3 x float] %y, [4 x double] %z)
   ret [4 x float] %r
@@ -420,7 +420,7 @@ define arm_aapcscc [2 x i32*] @test_tough_arrays([6 x [4 x i32]] %arr) {
 ; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]]
 ; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[LAST_STACK_ID]]
 ; CHECK: [[ARG_ARR:%[0-9]+]]:_(s768) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32), [[R3]](s32), [[FIRST_STACK_ELEMENT]](s32), {{.*}}, [[LAST_STACK_ELEMENT]](s32)
-; CHECK: ADJCALLSTACKDOWN 80, 0, 14, _, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKDOWN 80, 0, 14, %noreg, implicit-def %sp, implicit %sp
 ; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32), [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32), {{.*}}, [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR]](s768)
 ; CHECK: %r0 = COPY [[R0]]
 ; CHECK: %r1 = COPY [[R1]]
@@ -440,11 +440,11 @@ define arm_aapcscc [2 x i32*] @test_tough_arrays([6 x [4 x i32]] %arr) {
 ; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0
 ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
 ; CHECK: [[RES_ARR:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
-; CHECK: ADJCALLSTACKUP 80, 0, 14, _, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKUP 80, 0, 14, %noreg, implicit-def %sp, implicit %sp
 ; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[RES_ARR]](s64)
 ; CHECK: %r0 = COPY [[R0]]
 ; CHECK: %r1 = COPY [[R1]]
-; CHECK: BX_RET 14, _, implicit %r0, implicit %r1
+; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
 entry:
   %r = notail call arm_aapcscc [2 x i32*] @tough_arrays_target([6 x [4 x i32]] %arr)
   ret [2 x i32*] %r
@@ -458,7 +458,7 @@ define arm_aapcscc {i32, i32} @test_structs({i32, i32} %x) {
 ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
 ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
 ; CHECK: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
-; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
 ; CHECK: [[X0:%[0-9]+]]:_(s32), [[X1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[X]](s64)
 ; CHECK-DAG: %r0 = COPY [[X0]](s32)
 ; CHECK-DAG: %r1 = COPY [[X1]](s32)
@@ -466,11 +466,11 @@ define arm_aapcscc {i32, i32} @test_structs({i32, i32} %x) {
 ; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0
 ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
 ; CHECK: [[R:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
-; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
 ; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[R]](s64)
 ; CHECK: %r0 = COPY [[R0]](s32)
 ; CHECK: %r1 = COPY [[R1]](s32)
-; CHECK: BX_RET 14, _, implicit %r0, implicit %r1
+; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
   %r = notail call arm_aapcscc {i32, i32} @structs_target({i32, i32} %x)
   ret {i32, i32} %r
 }

test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir

@@ -80,7 +80,7 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = G_ADD %0, %1
     %r0 = COPY %2(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 
 ...
 ---
@@ -106,7 +106,7 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = G_SUB %0, %1
     %r0 = COPY %2(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 
 ...
 ---
@@ -132,7 +132,7 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = G_MUL %0, %1
     %r0 = COPY %2(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 
 ...
 ---
@@ -158,7 +158,7 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = G_SDIV %0, %1
     %r0 = COPY %2(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 
 ...
 ---
@@ -184,7 +184,7 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = G_UDIV %0, %1
     %r0 = COPY %2(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 
 ...
 ---
@@ -210,7 +210,7 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = G_AND %0, %1
     %r0 = COPY %2(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 
 ...
 ---
@@ -236,7 +236,7 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = G_OR %0, %1
     %r0 = COPY %2(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 
 ...
 ---
@@ -262,7 +262,7 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = G_XOR %0, %1
     %r0 = COPY %2(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 
 ...
 ---
@@ -288,7 +288,7 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = G_LSHR %0, %1
     %r0 = COPY %2(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 
 ...
 ---
@@ -314,7 +314,7 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = G_ASHR %0, %1
     %r0 = COPY %2(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 
 ...
 ---
@@ -340,7 +340,7 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = G_SHL %0, %1
     %r0 = COPY %2(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 
 ...
 ---
@@ -376,7 +376,7 @@ body:             |
     %3(s8)  = G_LOAD %0 :: (load 1)
     %4(s1)  = G_LOAD %0 :: (load 1)
     %5(p0)  = G_LOAD %0 :: (load 4)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 
 ...
 ---
@@ -418,7 +418,7 @@ body:             |
     G_STORE %5(p0), %0 :: (store 4)
     %6(s64) = COPY %d6
     G_STORE %6(s64), %0 :: (store 8)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 
 ...
 ---
@@ -451,7 +451,7 @@ body:             |
     %4(p0) = G_GEP %2, %3(s32)
     G_STORE %1(s32), %4(p0) :: (store 4)
 
-    BX_RET 14, _
+    BX_RET 14, %noreg
 
 ...
 ---
@@ -477,7 +477,7 @@ body:             |
     %1(s32) = COPY %r1
     %2(p0) = G_GEP %0, %1(s32)
     %r0 = COPY %2(p0)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_constants
@@ -493,7 +493,7 @@ body:             |
   bb.0:
     %0(s32) = G_CONSTANT 42
     %r0 = COPY %0(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_globals
@@ -509,7 +509,7 @@ body:             |
   bb.0:
     %0(p0) = G_GLOBAL_VALUE @a_global
     %r0 = COPY %0(p0)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_anyext_s8_32
@@ -533,7 +533,7 @@ body:             |
     %1(s8) = G_TRUNC %0(s32)
     %2(s32) = G_ANYEXT %1(s8)
     %r0 = COPY %2(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_anyext_s16_32
@@ -557,7 +557,7 @@ body:             |
     %1(s16) = G_TRUNC %0(s32)
     %2(s32) = G_ANYEXT %1(s16)
     %r0 = COPY %2(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_trunc_s32_16
@@ -581,7 +581,7 @@ body:             |
     %2(p0) = COPY %r1
     %1(s16) = G_TRUNC %0(s32)
     G_STORE %1(s16), %2 :: (store 2)
-    BX_RET 14, _
+    BX_RET 14, %noreg
 ...
 ---
 name:            test_icmp_eq_s32
@@ -609,7 +609,7 @@ body:             |
     %2(s1) = G_ICMP intpred(eq), %0(s32), %1
     %3(s32) = G_ZEXT %2(s1)
     %r0 = COPY %3(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 
 ...
 ---
@@ -638,7 +638,7 @@ body:             |
     %2(s1) = G_FCMP floatpred(one), %0(s32), %1
     %3(s32) = G_ZEXT %2(s1)
     %r0 = COPY %3(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 
 ...
 ---
@@ -667,7 +667,7 @@ body:             |
     %2(s1) = G_FCMP floatpred(ugt), %0(s64), %1
     %3(s32) = G_ZEXT %2(s1)
     %r0 = COPY %3(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 
 ...
 ---
@@ -699,7 +699,7 @@ body:             |
     %3(s1) = G_TRUNC %2(s32)
     %4(s32) = G_SELECT %3(s1), %0, %1
     %r0 = COPY %4(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 
 ...
 ---
@@ -727,10 +727,10 @@ body:             |
     G_BR %bb.2
 
   bb.1:
-    BX_RET 14, _
+    BX_RET 14, %noreg
 
   bb.2:
-    BX_RET 14, _
+    BX_RET 14, %noreg
 
 ...
 ---
@@ -756,7 +756,7 @@ body:             |
     %1(s32) = COPY %s1
     %2(s32) = G_FADD %0, %1
     %s0 = COPY %2(s32)
-    BX_RET 14, _, implicit %s0
+    BX_RET 14, %noreg, implicit %s0
 
 ...
 ---
@@ -782,7 +782,7 @@ body:             |
     %1(s64) = COPY %d1
     %2(s64) = G_FADD %0, %1
     %d0 = COPY %2(s64)
-    BX_RET 14, _, implicit %d0
+    BX_RET 14, %noreg, implicit %d0
 
 ...
 ---
@@ -808,7 +808,7 @@ body:             |
     %1(s32) = COPY %s1
     %2(s32) = G_FSUB %0, %1
     %s0 = COPY %2(s32)
-    BX_RET 14, _, implicit %s0
+    BX_RET 14, %noreg, implicit %s0
 
 ...
 ---
@@ -834,7 +834,7 @@ body:             |
     %1(s64) = COPY %d1
     %2(s64) = G_FSUB %0, %1
     %d0 = COPY %2(s64)
-    BX_RET 14, _, implicit %d0
+    BX_RET 14, %noreg, implicit %d0
 
 ...
 ---
@@ -860,7 +860,7 @@ body:             |
     %1(s32) = COPY %s1
     %2(s32) = G_FMUL %0, %1
     %s0 = COPY %2(s32)
-    BX_RET 14, _, implicit %s0
+    BX_RET 14, %noreg, implicit %s0
 
 ...
 ---
@@ -886,7 +886,7 @@ body:             |
     %1(s64) = COPY %d1
     %2(s64) = G_FMUL %0, %1
     %d0 = COPY %2(s64)
-    BX_RET 14, _, implicit %d0
+    BX_RET 14, %noreg, implicit %d0
 
 ...
 ---
@@ -912,7 +912,7 @@ body:             |
     %1(s32) = COPY %s1
     %2(s32) = G_FDIV %0, %1
     %s0 = COPY %2(s32)
-    BX_RET 14, _, implicit %s0
+    BX_RET 14, %noreg, implicit %s0
 
 ...
 ---
@@ -938,7 +938,7 @@ body:             |
     %1(s64) = COPY %d1
     %2(s64) = G_FDIV %0, %1
     %d0 = COPY %2(s64)
-    BX_RET 14, _, implicit %d0
+    BX_RET 14, %noreg, implicit %d0
 
 ...
 ---
@@ -970,6 +970,6 @@ body:             |
     %3(s32), %4(s32) = G_UNMERGE_VALUES %2(s64)
     %r0 = COPY %3(s32)
     %r1 = COPY %4(s32)
-    BX_RET 14, _, implicit %r0, implicit %r1
+    BX_RET 14, %noreg, implicit %r0, implicit %r1
 
 ...

test/CodeGen/ARM/GlobalISel/arm-select-globals-pic.mir

@@ -33,13 +33,13 @@ body:             |
     ; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel {{.*}}@internal_global
 
     %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global)
-    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _ :: (load 4 from @internal_global)
+    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @internal_global)
 
     %r0 = COPY %1(s32)
     ; CHECK: %r0 = COPY [[V]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_external_global
@@ -59,13 +59,13 @@ body:             |
     ; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel_ldr target-flags(<unknown>) @external_global :: (load 4 from got)
 
     %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global)
-    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _ :: (load 4 from @external_global)
+    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @external_global)
 
     %r0 = COPY %1(s32)
     ; CHECK: %r0 = COPY [[V]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_internal_constant
@@ -85,13 +85,13 @@ body:             |
     ; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel {{.*}}@internal_constant
 
     %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_constant)
-    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _ :: (load 4 from @internal_constant)
+    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @internal_constant)
 
     %r0 = COPY %1(s32)
     ; CHECK: %r0 = COPY [[V]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_external_constant
@@ -111,11 +111,11 @@ body:             |
     ; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel_ldr target-flags(<unknown>) @external_constant :: (load 4 from got)
 
     %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_constant)
-    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _ :: (load 4 from @external_constant)
+    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @external_constant)
 
     %r0 = COPY %1(s32)
     ; CHECK: %r0 = COPY [[V]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...

test/CodeGen/ARM/GlobalISel/arm-select-globals-ropi-rwpi.mir

@@ -37,19 +37,19 @@ body:             |
   bb.0:
     %0(p0) = G_GLOBAL_VALUE @internal_global
     ; RW-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global
-    ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool)
+    ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
     ; RWPI-MOVT: [[OFF:%[0-9]+]]:gpr = MOVi32imm {{.*}} @internal_global
-    ; RWPI-NOMOVT: [[OFF:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool)
-    ; RWPI: [[G:%[0-9]+]]:gpr = ADDrr %r9, [[OFF]], 14, _, _
+    ; RWPI-NOMOVT: [[OFF:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
+    ; RWPI: [[G:%[0-9]+]]:gpr = ADDrr %r9, [[OFF]], 14, %noreg, %noreg
 
     %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global)
-    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _ :: (load 4 from @internal_global)
+    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @internal_global)
 
     %r0 = COPY %1(s32)
     ; CHECK: %r0 = COPY [[V]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_external_global
@@ -71,19 +71,19 @@ body:             |
   bb.0:
     %0(p0) = G_GLOBAL_VALUE @external_global
     ; RW-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global
-    ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool)
+    ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
     ; RWPI-MOVT: [[OFF:%[0-9]+]]:gpr = MOVi32imm {{.*}} @external_global
-    ; RWPI-NOMOVT: [[OFF:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool)
-    ; RWPI: [[G:%[0-9]+]]:gpr = ADDrr %r9, [[OFF]], 14, _, _
+    ; RWPI-NOMOVT: [[OFF:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
+    ; RWPI: [[G:%[0-9]+]]:gpr = ADDrr %r9, [[OFF]], 14, %noreg, %noreg
 
     %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global)
-    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _ :: (load 4 from @external_global)
+    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @external_global)
 
     %r0 = COPY %1(s32)
     ; CHECK: %r0 = COPY [[V]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_internal_constant
@@ -104,16 +104,16 @@ body:             |
     ; ROPI-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel @internal_constant
     ; ROPI-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel @internal_constant
     ; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_constant
-    ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool)
+    ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
 
     %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_constant)
-    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _ :: (load 4 from @internal_constant)
+    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @internal_constant)
 
     %r0 = COPY %1(s32)
     ; CHECK: %r0 = COPY [[V]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_external_constant
@@ -134,14 +134,14 @@ body:             |
     ; ROPI-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel @external_constant
     ; ROPI-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel @external_constant
     ; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_constant
-    ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool)
+    ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
 
     %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_constant)
-    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _ :: (load 4 from @external_constant)
+    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @external_constant)
 
     %r0 = COPY %1(s32)
     ; CHECK: %r0 = COPY [[V]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...

test/CodeGen/ARM/GlobalISel/arm-select-globals-static.mir

@@ -26,18 +26,18 @@ body:             |
   bb.0:
     %0(p0) = G_GLOBAL_VALUE @internal_global
     ; ELF-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global
-    ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool)
+    ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
     ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global
     ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_abs @internal_global
 
     %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global)
-    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _
+    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg
 
     %r0 = COPY %1(s32)
     ; CHECK: %r0 = COPY [[V]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_external_global
@@ -56,16 +56,16 @@ body:             |
   bb.0:
     %0(p0) = G_GLOBAL_VALUE @external_global
     ; ELF-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global
-    ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool)
+    ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
     ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global
     ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_abs @external_global
 
     %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global)
-    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _
+    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg
 
     %r0 = COPY %1(s32)
     ; CHECK: %r0 = COPY [[V]]
 
-    BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
+    ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...

test/CodeGen/ARM/a15-SD-dep.ll

@@ -114,4 +114,4 @@ sw.bb1:                                           ; preds = %entry, %sw.bb
 
 sw.epilog:                                        ; preds = %entry, %sw.bb1
   ret void
-}
+}

test/CodeGen/ARM/cmp1-peephole-thumb.mir

@@ -49,9 +49,9 @@ frameInfo:
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
 
-# CHECK:  tMOVi8 1, 14, _
-# CHECK:  tMOVi8 0, 14, _
-# CHECK:  tMUL %1, %0, 14, _
+# CHECK:  tMOVi8 1, 14, %noreg
+# CHECK:  tMOVi8 0, 14, %noreg
+# CHECK:  tMUL %1, %0, 14, %noreg
 # CHECK-NOT: tCMPi8
 body:             |
   bb.0.entry:
@@ -59,10 +59,10 @@ body:             |
 
     %1 = COPY %r1
     %0 = COPY %r0
-    %2, %cpsr = tMUL %1, %0, 14, _
-    %3, %cpsr = tMOVi8 1, 14, _
-    %4, %cpsr = tMOVi8 0, 14, _
-    tCMPi8 killed %2, 0, 14, _, implicit-def %cpsr
+    %2, %cpsr = tMUL %1, %0, 14, %noreg
+    %3, %cpsr = tMOVi8 1, 14, %noreg
+    %4, %cpsr = tMOVi8 0, 14, %noreg
+    tCMPi8 killed %2, 0, 14, %noreg, implicit-def %cpsr
     tBcc %bb.2.entry, 0, %cpsr
 
   bb.1.entry:
@@ -70,6 +70,6 @@ body:             |
   bb.2.entry:
     %5 = PHI %4, %bb.1.entry, %3, %bb.0.entry
     %r0 = COPY %5
-    tBX_RET 14, _, implicit %r0
+    tBX_RET 14, %noreg, implicit %r0
 
 ...

test/CodeGen/ARM/cmp2-peephole-thumb.mir

@@ -80,24 +80,24 @@ body:             |
 
     %1 = COPY %r1
     %0 = COPY %r0
-    %2, %cpsr = tMUL %0, %1, 14, _
-    tSTRspi %2, %stack.1.mul, 0, 14, _ :: (store 4 into %ir.mul)
-    tCMPi8 %2, 0, 14, _, implicit-def %cpsr
+    %2, %cpsr = tMUL %0, %1, 14, %noreg
+    tSTRspi %2, %stack.1.mul, 0, 14, %noreg :: (store 4 into %ir.mul)
+    tCMPi8 %2, 0, 14, %noreg, implicit-def %cpsr
     tBcc %bb.2.if.end, 12, %cpsr
-    tB %bb.1.if.then, 14, _
+    tB %bb.1.if.then, 14, %noreg
 
   bb.1.if.then:
-    %4, %cpsr = tMOVi8 42, 14, _
-    tSTRspi killed %4, %stack.0.retval, 0, 14, _ :: (store 4 into %ir.retval)
-    tB %bb.3.return, 14, _
+    %4, %cpsr = tMOVi8 42, 14, %noreg
+    tSTRspi killed %4, %stack.0.retval, 0, 14, %noreg :: (store 4 into %ir.retval)
+    tB %bb.3.return, 14, %noreg
 
   bb.2.if.end:
-    %3, %cpsr = tMOVi8 1, 14, _
-    tSTRspi killed %3, %stack.0.retval, 0, 14, _ :: (store 4 into %ir.retval)
+    %3, %cpsr = tMOVi8 1, 14, %noreg
+    tSTRspi killed %3, %stack.0.retval, 0, 14, %noreg :: (store 4 into %ir.retval)
 
   bb.3.return:
-    %5 = tLDRspi %stack.0.retval, 0, 14, _ :: (dereferenceable load 4 from %ir.retval)
+    %5 = tLDRspi %stack.0.retval, 0, 14, %noreg :: (dereferenceable load 4 from %ir.retval)
     %r0 = COPY %5
-    tBX_RET 14, _, implicit %r0
+    tBX_RET 14, %noreg, implicit %r0
 
 ...

test/CodeGen/ARM/constant-islands-cfg.mir

@@ -48,17 +48,17 @@ fixedStack:
 body:             |
   bb.0:
     liveins: %r0
-    tCMPi8 killed %r0, 0, 14, _, implicit-def %cpsr
+    tCMPi8 killed %r0, 0, 14, %noreg, implicit-def %cpsr
     tBcc %bb.2, 1, killed %cpsr
-    tB %bb.3, 14, _
+    tB %bb.3, 14, %noreg
 
   bb.1:
     dead %r0 = SPACE 256, undef %r0
 
   bb.2:
-    tPOP_RET 14, _, def %pc
+    tPOP_RET 14, %noreg, def %pc
 
   bb.3:
-    tPOP_RET 14, _, def %pc
+    tPOP_RET 14, %noreg, def %pc
 
 ...

test/CodeGen/ARM/dbg-range-extension.mir

@@ -23,37 +23,37 @@
 # CHECK: [[VAR_I:![0-9]+]] = !DILocalVariable(name: "i",
 
 # CHECK: bb.0.entry
-# CHECK: DBG_VALUE debug-use %r0, debug-use _, [[VAR_A]]
-# CHECK: DBG_VALUE debug-use [[REG_A:%r[0-9]+]], debug-use _, [[VAR_A]]
-# CHECK: DBG_VALUE debug-use [[REG_B:%r[0-9]+]], debug-use _, [[VAR_B]]
+# CHECK: DBG_VALUE debug-use %r0, debug-use %noreg, [[VAR_A]]
+# CHECK: DBG_VALUE debug-use [[REG_A:%r[0-9]+]], debug-use %noreg, [[VAR_A]]
+# CHECK: DBG_VALUE debug-use [[REG_B:%r[0-9]+]], debug-use %noreg, [[VAR_B]]
 
 # CHECK: bb.1.if.then
-# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use _, [[VAR_B]]
-# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use _, [[VAR_A]]
-# CHECK: DBG_VALUE debug-use [[REG_C:%r[0-9]+]], debug-use _, [[VAR_C]]
+# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use %noreg, [[VAR_B]]
+# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use %noreg, [[VAR_A]]
+# CHECK: DBG_VALUE debug-use [[REG_C:%r[0-9]+]], debug-use %noreg, [[VAR_C]]
 # CHECK: DBG_VALUE 1, 0, [[VAR_I]]
 
 # CHECK: bb.2.for.body
-# CHECK: DBG_VALUE debug-use [[REG_I:%r[0-9]+]], debug-use _, [[VAR_I]]
-# CHECK: DBG_VALUE debug-use [[REG_C]], debug-use _, [[VAR_C]]
-# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use _, [[VAR_B]]
-# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use _, [[VAR_A]]
-# CHECK: DBG_VALUE debug-use [[REG_I]], debug-use _, [[VAR_I]]
+# CHECK: DBG_VALUE debug-use [[REG_I:%r[0-9]+]], debug-use %noreg, [[VAR_I]]
+# CHECK: DBG_VALUE debug-use [[REG_C]], debug-use %noreg, [[VAR_C]]
+# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use %noreg, [[VAR_B]]
+# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use %noreg, [[VAR_A]]
+# CHECK: DBG_VALUE debug-use [[REG_I]], debug-use %noreg, [[VAR_I]]
 
 # CHECK: bb.3.for.cond
-# CHECK: DBG_VALUE debug-use [[REG_C]], debug-use _, [[VAR_C]]
-# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use _, [[VAR_B]]
-# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use _, [[VAR_A]]
-# CHECK: DBG_VALUE debug-use [[REG_I]], debug-use _, [[VAR_I]]
+# CHECK: DBG_VALUE debug-use [[REG_C]], debug-use %noreg, [[VAR_C]]
+# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use %noreg, [[VAR_B]]
+# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use %noreg, [[VAR_A]]
+# CHECK: DBG_VALUE debug-use [[REG_I]], debug-use %noreg, [[VAR_I]]
 
 # CHECK: bb.4.for.cond.cleanup
-# CHECK: DBG_VALUE debug-use [[REG_C]], debug-use _, [[VAR_C]]
-# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use _, [[VAR_B]]
-# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use _, [[VAR_A]]
+# CHECK: DBG_VALUE debug-use [[REG_C]], debug-use %noreg, [[VAR_C]]
+# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use %noreg, [[VAR_B]]
+# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use %noreg, [[VAR_A]]
 
 # CHECK: bb.5.if.end
-# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use _, [[VAR_B]]
-# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use _, [[VAR_A]]
+# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use %noreg, [[VAR_B]]
+# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use %noreg, [[VAR_A]]
 --- |
   ; ModuleID = '/data/kwalker/work/OpenSource-llvm/llvm/test/CodeGen/ARM/dbg-range-extension.ll'
   source_filename = "/data/kwalker/work/OpenSource-llvm/llvm/test/CodeGen/ARM/dbg-range-extension.ll"
@@ -211,7 +211,7 @@ body:             |
   bb.0.entry:
     liveins: %r0, %r4, %r5, %r6, %r7, %r11, %lr
   
-    %sp = frame-setup STMDB_UPD %sp, 14, _, killed %r4, killed %r5, killed %r6, killed %r7, killed %r11, killed %lr
+    %sp = frame-setup STMDB_UPD %sp, 14, %noreg, killed %r4, killed %r5, killed %r6, killed %r7, killed %r11, killed %lr
     frame-setup CFI_INSTRUCTION def_cfa_offset 24
     frame-setup CFI_INSTRUCTION offset %lr, -4
     frame-setup CFI_INSTRUCTION offset %r11, -8
@@ -219,58 +219,58 @@ body:             |
     frame-setup CFI_INSTRUCTION offset %r6, -16
     frame-setup CFI_INSTRUCTION offset %r5, -20
     frame-setup CFI_INSTRUCTION offset %r4, -24
-    DBG_VALUE debug-use %r0, debug-use _, !13, !20, debug-location !21
-    %r4 = MOVr killed %r0, 14, _, _
-    DBG_VALUE debug-use %r4, debug-use _, !13, !20, debug-location !21
-    %r0 = MOVi 10, 14, _, _, debug-location !22
-    %r1 = MOVi 11, 14, _, _, debug-location !22
+    DBG_VALUE debug-use %r0, debug-use %noreg, !13, !20, debug-location !21
+    %r4 = MOVr killed %r0, 14, %noreg, %noreg
+    DBG_VALUE debug-use %r4, debug-use %noreg, !13, !20, debug-location !21
+    %r0 = MOVi 10, 14, %noreg, _, debug-location !22
+    %r1 = MOVi 11, 14, %noreg, _, debug-location !22
     BL @func2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit killed %r0, implicit killed %r1, implicit-def %sp, implicit-def %r0, debug-location !22
-    %r5 = MOVr killed %r0, 14, _, _, debug-location !22
-    DBG_VALUE debug-use %r5, debug-use _, !14, !20, debug-location !23
-    CMPri %r4, 0, 14, _, implicit-def %cpsr, debug-location !25
+    %r5 = MOVr killed %r0, 14, %noreg, _, debug-location !22
+    DBG_VALUE debug-use %r5, debug-use %noreg, !14, !20, debug-location !23
+    CMPri %r4, 0, 14, %noreg, implicit-def %cpsr, debug-location !25
     Bcc %bb.5.if.end, 0, killed %cpsr
   
   bb.1.if.then:
     liveins: %r4, %r5
   
-    %r0 = MOVi 12, 14, _, _, debug-location !26
-    %r1 = MOVi 13, 14, _, _, debug-location !26
+    %r0 = MOVi 12, 14, %noreg, _, debug-location !26
+    %r1 = MOVi 13, 14, %noreg, _, debug-location !26
     BL @func2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit killed %r0, implicit killed %r1, implicit-def %sp, implicit-def %r0, debug-location !26
-    %r6 = MOVr killed %r0, 14, _, _, debug-location !26
-    DBG_VALUE debug-use %r6, debug-use _, !15, !20, debug-location !27
-    %r7 = MOVi 1, 14, _, _
+    %r6 = MOVr killed %r0, 14, %noreg, _, debug-location !26
+    DBG_VALUE debug-use %r6, debug-use %noreg, !15, !20, debug-location !27
+    %r7 = MOVi 1, 14, %noreg, %noreg
     DBG_VALUE 1, 0, !18, !20, debug-location !28
     B %bb.3.for.cond
   
   bb.2.for.body:
     liveins: %r4, %r5, %r6, %r7
   
-    %r1 = ADDrr %r5, %r7, 14, _, _, debug-location !36
-    %r0 = MOVr %r7, 14, _, _, debug-location !36
+    %r1 = ADDrr %r5, %r7, 14, %noreg, _, debug-location !36
+    %r0 = MOVr %r7, 14, %noreg, _, debug-location !36
     BL @func2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit killed %r0, implicit killed %r1, implicit-def %sp, implicit-def dead %r0, debug-location !36
-    %r7 = ADDri killed %r7, 1, 14, _, _, debug-location !38
-    DBG_VALUE debug-use %r7, debug-use _, !18, !20, debug-location !28
+    %r7 = ADDri killed %r7, 1, 14, %noreg, _, debug-location !38
+    DBG_VALUE debug-use %r7, debug-use %noreg, !18, !20, debug-location !28
   
   bb.3.for.cond:
     liveins: %r4, %r5, %r6, %r7
   
-    DBG_VALUE debug-use %r7, debug-use _, !18, !20, debug-location !28
-    CMPrr %r7, %r4, 14, _, implicit-def %cpsr, debug-location !33
+    DBG_VALUE debug-use %r7, debug-use %noreg, !18, !20, debug-location !28
+    CMPrr %r7, %r4, 14, %noreg, implicit-def %cpsr, debug-location !33
     Bcc %bb.2.for.body, 11, killed %cpsr, debug-location !33
   
   bb.4.for.cond.cleanup:
     liveins: %r4, %r5, %r6
   
-    %r0 = MOVr %r5, 14, _, _, debug-location !34
-    %r1 = MOVr killed %r6, 14, _, _, debug-location !34
+    %r0 = MOVr %r5, 14, %noreg, _, debug-location !34
+    %r1 = MOVr killed %r6, 14, %noreg, _, debug-location !34
     BL @func2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit killed %r0, implicit killed %r1, implicit-def %sp, implicit-def dead %r0, debug-location !34
   
   bb.5.if.end:
     liveins: %r4, %r5
   
-    %r0 = MOVr killed %r5, 14, _, _, debug-location !43
-    %r1 = MOVr killed %r4, 14, _, _, debug-location !43
-    %sp = LDMIA_UPD %sp, 14, _, def %r4, def %r5, def %r6, def %r7, def %r11, def %lr, debug-location !43
+    %r0 = MOVr killed %r5, 14, %noreg, _, debug-location !43
+    %r1 = MOVr killed %r4, 14, %noreg, _, debug-location !43
+    %sp = LDMIA_UPD %sp, 14, %noreg, def %r4, def %r5, def %r6, def %r7, def %r11, def %lr, debug-location !43
     TAILJMPd @func2, implicit %sp, implicit %sp, implicit killed %r0, implicit killed %r1, debug-location !43
 
 ...

test/CodeGen/ARM/expand-pseudos.mir

@@ -25,11 +25,11 @@ body:             |
   bb.0.entry:
     liveins: %r0
 
-    %r1 = MOVi 2, 14, _, _
-    CMPri killed %r0, 0, 14, _, implicit-def %cpsr
+    %r1 = MOVi 2, 14, %noreg, %noreg
+    CMPri killed %r0, 0, 14, %noreg, implicit-def %cpsr
     %r1 = MOVCCi16 killed %r1, 500, 0, killed %cpsr
-    %r0 = MOVr killed %r1, 14, _, _
-    BX_RET 14, _, implicit %r0
+    %r0 = MOVr killed %r1, 14, %noreg, %noreg
+    BX_RET 14, %noreg, implicit %r0
 
 ...
 ---
@@ -42,11 +42,11 @@ body:             |
   bb.0.entry:
     liveins: %r0
 
-    %r1 = MOVi 2, 14, _, _
-    CMPri killed %r0, 0, 14, _, implicit-def %cpsr
+    %r1 = MOVi 2, 14, %noreg, %noreg
+    CMPri killed %r0, 0, 14, %noreg, implicit-def %cpsr
     %r1 = MOVCCi32imm killed %r1, 500500500, 0, killed %cpsr
-    %r0 = MOVr killed %r1, 14, _, _
-    BX_RET 14, _, implicit %r0
+    %r0 = MOVr killed %r1, 14, %noreg, %noreg
+    BX_RET 14, %noreg, implicit %r0
 
 ...
 ---
@@ -60,9 +60,9 @@ body:             |
   bb.0.entry:
     liveins: %r0, %r1
 
-    CMPri %r1, 500, 14, _, implicit-def %cpsr
+    CMPri %r1, 500, 14, %noreg, implicit-def %cpsr
     %r0 = MOVCCr killed %r0, killed %r1, 12, killed %cpsr
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 
 ...
 
@@ -72,4 +72,4 @@ body:             |
 # CHECK:    %r1 = MOVi16 2068, 0, %cpsr, implicit killed %r1
 # CHECK:    %r1 = MOVTi16 %r1, 7637, 0, %cpsr
 # CHECK-LABEL: name: test3
-# CHECK: %r0 = MOVr killed %r1, 12, killed %cpsr, _, implicit killed %r0
+# CHECK: %r0 = MOVr killed %r1, 12, killed %cpsr, %noreg, implicit killed %r0

test/CodeGen/ARM/fpoffset_overflow.mir

@@ -3,10 +3,10 @@
 # This should trigger an emergency spill in the register scavenger because the
 # frame offset into the large argument is too large.
 # CHECK-LABEL: name: func0
-# CHECK: t2STRi12 killed [[SPILLED:%r[0-9]+]], %sp, 0, 14, _ :: (store 4 into %stack.0)
-# CHECK: [[SPILLED]] = t2ADDri killed %sp, 4096, 14, _, _
-# CHECK: %sp = t2LDRi12 killed [[SPILLED]], 40, 14, _ :: (load 4)
-# CHECK: [[SPILLED]] = t2LDRi12 %sp, 0, 14, _ :: (load 4 from %stack.0)
+# CHECK: t2STRi12 killed [[SPILLED:%r[0-9]+]], %sp, 0, 14, %noreg :: (store 4 into %stack.0)
+# CHECK: [[SPILLED]] = t2ADDri killed %sp, 4096, 14, %noreg, %noreg
+# CHECK: %sp = t2LDRi12 killed [[SPILLED]], 40, 14, %noreg :: (load 4)
+# CHECK: [[SPILLED]] = t2LDRi12 %sp, 0, 14, %noreg :: (load 4 from %stack.0)
 name: func0
 tracksRegLiveness: true
 fixedStack:
@@ -31,7 +31,7 @@ body: |
     %r12 = IMPLICIT_DEF
     %lr = IMPLICIT_DEF
 
-    %sp = t2LDRi12 %fixed-stack.0, 0, 14, _ :: (load 4)
+    %sp = t2LDRi12 %fixed-stack.0, 0, 14, %noreg :: (load 4)
 
     KILL %r0
     KILL %r1
@@ -53,7 +53,7 @@ body: |
 # CHECK-LABEL: name: func1
 # CHECK-NOT: t2STRi12
 # CHECK-NOT: t2ADDri
-# CHECK: %r11 = t2LDRi12 %sp, 4092, 14, _ :: (load 4)
+# CHECK: %r11 = t2LDRi12 %sp, 4092, 14, %noreg :: (load 4)
 # CHECK-NOT: t2LDRi12
 name: func1
 tracksRegLiveness: true
@@ -78,7 +78,7 @@ body: |
     %r12 = IMPLICIT_DEF
     %lr = IMPLICIT_DEF
 
-    %r11 = t2LDRi12 %fixed-stack.0, 0, 14, _ :: (load 4)
+    %r11 = t2LDRi12 %fixed-stack.0, 0, 14, %noreg :: (load 4)
 
     KILL %r0
     KILL %r1

test/CodeGen/ARM/imm-peephole-arm.mir

@@ -42,18 +42,18 @@ body:             |
 
     %0 = COPY %r0
     %1 = MOVi32imm -25733
-    %2 = SUBrr %0, killed %1, 14, _, _
+    %2 = SUBrr %0, killed %1, 14, %noreg, %noreg
 
     %3 = MOVi32imm 25733
-    %4 = SUBrr %0, killed %3, 14, _, _
+    %4 = SUBrr %0, killed %3, 14, %noreg, %noreg
 
     %5 = MOVi32imm -25733
-    %6 = ADDrr %0, killed %5, 14, _, _
+    %6 = ADDrr %0, killed %5, 14, %noreg, %noreg
 
     %7 = MOVi32imm 25733
-    %8 = ADDrr killed %0, killed %7, 14, _, _
+    %8 = ADDrr killed %0, killed %7, 14, %noreg, %noreg
 
     %r0 = COPY killed %8
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, %noreg, implicit %r0
 
 ...

test/CodeGen/ARM/imm-peephole-thumb.mir

@@ -41,18 +41,18 @@ body:             |
     liveins: %r0
     %0 = COPY %r0
     %1 = t2MOVi32imm -25733
-    %2 = t2SUBrr %0, killed %1, 14, _, _
+    %2 = t2SUBrr %0, killed %1, 14, %noreg, %noreg
 
     %3 = t2MOVi32imm 25733
-    %4 = t2SUBrr %0, killed %3, 14, _, _
+    %4 = t2SUBrr %0, killed %3, 14, %noreg, %noreg
 
     %5 = t2MOVi32imm -25733
-    %6= t2ADDrr %0, killed %5, 14, _, _
+    %6= t2ADDrr %0, killed %5, 14, %noreg, %noreg
 
     %7 = t2MOVi32imm 25733
-    %8 = t2ADDrr killed %0, killed %7, 14, _, _
+    %8 = t2ADDrr killed %0, killed %7, 14, %noreg, %noreg
 
     %r0 = COPY killed %8
-    tBX_RET 14, _, implicit %r0
+    tBX_RET 14, %noreg, implicit %r0
 
 ...

test/CodeGen/ARM/indirect-hidden.ll

@@ -19,4 +19,4 @@ define i32* @get_var_hidden() {
 ; CHECK-NOT: __DATA,__data
 
 ; CHECK: .indirect_symbol _var_hidden
-; CHECK-NEXT: .long 0
+; CHECK-NEXT: .long 0

test/CodeGen/ARM/litpool-licm.ll

@@ -43,4 +43,4 @@ done:
   ret void
 }
 
-declare void @foo(i32*)
+declare void @foo(i32*)

test/CodeGen/ARM/load_store_opt_kill.mir

@@ -3,8 +3,8 @@
 # CHECK-LABEL: name: f
 name:            f
 # Make sure the load into %r0 doesn't clobber the base register before the second load uses it.
-# CHECK: %r3 = LDRi12 %r0, 12, 14, _
-# CHECK-NEXT: %r0 = LDRi12 %r0, 8, 14, _
+# CHECK: %r3 = LDRi12 %r0, 12, 14, %noreg
+# CHECK-NEXT: %r0 = LDRi12 %r0, 8, 14, %noreg
 body:             |
   bb.0:
     liveins: %r0, %r3

test/CodeGen/ARM/local-call.ll

@@ -17,4 +17,4 @@ define i64 @test_local_call(i64 %a, i64 %b) {
 
 %res = udiv i64 %a, %b
   ret i64 %res
-}
+}

test/CodeGen/ARM/machine-copyprop.mir

@@ -3,20 +3,20 @@
 # Test that machine copy prop recognizes the implicit-def operands on a COPY
 # as clobbering the register.
 # CHECK-LABEL: name: func
-# CHECK: %d2 = VMOVv2i32 2, 14, _
+# CHECK: %d2 = VMOVv2i32 2, 14, %noreg
 # CHECK: %s5 = COPY %s0, implicit %q1, implicit-def %q1
-# CHECK: VST1q32 %r0, 0, %q1, 14, _
+# CHECK: VST1q32 %r0, 0, %q1, 14, %noreg
 # The following two COPYs must not be removed
 # CHECK: %s4 = COPY %s20, implicit-def %q1
 # CHECK: %s5 = COPY %s0, implicit killed %d0, implicit %q1, implicit-def %q1
-# CHECK: VST1q32 %r2, 0, %q1, 14, _
+# CHECK: VST1q32 %r2, 0, %q1, 14, %noreg
 name: func
 body: |
   bb.0:
-    %d2 = VMOVv2i32 2, 14, _
+    %d2 = VMOVv2i32 2, 14, %noreg
     %s5 = COPY %s0, implicit %q1, implicit-def %q1
-    VST1q32 %r0, 0, %q1, 14, _
+    VST1q32 %r0, 0, %q1, 14, %noreg
     %s4 = COPY %s20, implicit-def %q1
     %s5 = COPY %s0, implicit killed %d0, implicit %q1, implicit-def %q1
-    VST1q32 %r2, 0, %q1, 14, _
+    VST1q32 %r2, 0, %q1, 14, %noreg
 ...

test/CodeGen/ARM/misched-int-basic-thumb2.mir

@@ -152,24 +152,24 @@ body:             |
     %1 = COPY %r1
     %0 = COPY %r0
     %2 = t2MOVi32imm @g1
-    %3 = t2LDRi12 %2, 0, 14, _ :: (dereferenceable load 4 from @g1)
+    %3 = t2LDRi12 %2, 0, 14, %noreg :: (dereferenceable load 4 from @g1)
     %4 = t2MOVi32imm @g2
-    %5 = t2LDRi12 %4, 0, 14, _ :: (dereferenceable load 4 from @g2)
-    %6 = t2ADDrr %3, %3, 14, _, _
-    %7 = t2SDIV %6, %5, 14, _
-    t2STRi12 %7, %2, 0, 14, _ :: (store 4 into @g1)
-    %8 = t2SMULBB %1, %1, 14, _
-    %9 = t2SMLABB %0, %0, %8, 14, _
-    %10 = t2UXTH %9, 0, 14, _
-    %11 = t2MUL %10, %7, 14, _
-    %12 = t2MLA %11, %11, %11, 14, _
-    %13, %14 = t2UMULL %12, %12, 14, _
-    %19, %16 = t2UMULL %13, %13, 14, _
-    %17 = t2MLA %13, %14, %16, 14, _
-    %20 = t2MLA %13, %14, %17, 14, _
-    %19, %20 = t2UMLAL %12, %12, %19, %20, 14, _
+    %5 = t2LDRi12 %4, 0, 14, %noreg :: (dereferenceable load 4 from @g2)
+    %6 = t2ADDrr %3, %3, 14, %noreg, %noreg
+    %7 = t2SDIV %6, %5, 14, %noreg
+    t2STRi12 %7, %2, 0, 14, %noreg :: (store 4 into @g1)
+    %8 = t2SMULBB %1, %1, 14, %noreg
+    %9 = t2SMLABB %0, %0, %8, 14, %noreg
+    %10 = t2UXTH %9, 0, 14, %noreg
+    %11 = t2MUL %10, %7, 14, %noreg
+    %12 = t2MLA %11, %11, %11, 14, %noreg
+    %13, %14 = t2UMULL %12, %12, 14, %noreg
+    %19, %16 = t2UMULL %13, %13, 14, %noreg
+    %17 = t2MLA %13, %14, %16, 14, %noreg
+    %20 = t2MLA %13, %14, %17, 14, %noreg
+    %19, %20 = t2UMLAL %12, %12, %19, %20, 14, %noreg
     %r0 = COPY %19
     %r1 = COPY %20
-    tBX_RET 14, _, implicit %r0, implicit %r1
+    tBX_RET 14, %noreg, implicit %r0, implicit %r1
 
 ...

test/CodeGen/ARM/misched-int-basic.mir

@@ -111,18 +111,18 @@ body:             |
 
     %1 = COPY %r1
     %0 = COPY %r0
-    %2 = SMULBB %1, %1, 14, _
-    %3 = SMLABB %0, %0, %2, 14, _
-    %4 = UXTH %3, 0, 14, _
-    %5 = MUL %4, %4, 14, _, _
-    %6 = MLA %5, %5, %5, 14, _, _
-    %7, %8 = UMULL %6, %6, 14, _, _
-    %13, %10 = UMULL %7, %7, 14, _, _
-    %11 = MLA %7, %8, %10, 14, _, _
-    %14 = MLA %7, %8, %11, 14, _, _
-    %13, %14 = UMLAL %6, %6, %13, %14, 14, _, _
+    %2 = SMULBB %1, %1, 14, %noreg
+    %3 = SMLABB %0, %0, %2, 14, %noreg
+    %4 = UXTH %3, 0, 14, %noreg
+    %5 = MUL %4, %4, 14, %noreg, %noreg
+    %6 = MLA %5, %5, %5, 14, %noreg, %noreg
+    %7, %8 = UMULL %6, %6, 14, %noreg, %noreg
+    %13, %10 = UMULL %7, %7, 14, %noreg, %noreg
+    %11 = MLA %7, %8, %10, 14, %noreg, %noreg
+    %14 = MLA %7, %8, %11, 14, %noreg, %noreg
+    %13, %14 = UMLAL %6, %6, %13, %14, 14, %noreg, %noreg
     %r0 = COPY %13
     %r1 = COPY %14
-    BX_RET 14, _, implicit %r0, implicit %r1
+    BX_RET 14, %noreg, implicit %r0, implicit %r1
 
 ...

test/CodeGen/ARM/pei-swiftself.mir

@@ -39,7 +39,7 @@ body: |
     ; not just use %r10 for that.
     ; CHECK-NOT: STRi12 %1,{{.*}}%r10
 
-    STRi12 %r1, %stack.0, 0, 14, _ :: (store 4)
+    STRi12 %r1, %stack.0, 0, 14, %noreg :: (store 4)
 
     ; use the swiftself parameter value.
     KILL %r10

test/CodeGen/ARM/pr25317.ll

@@ -8,4 +8,4 @@ target triple = "armv7--linux-gnueabihf"
 define void @f(i32* %p) {
   call void asm sideeffect "str lr, $0", "=*o"(i32* %p)
   ret void
-}
+}

test/CodeGen/ARM/preferred-align.ll

@@ -18,4 +18,4 @@
 @var16 = global i16 zeroinitializer
 
 ; CHECK: .globl var16
-; CHECK-NEXT: .p2align 1
+; CHECK-NEXT: .p2align 1

test/CodeGen/ARM/prera-ldst-aliasing.mir

@@ -26,15 +26,15 @@ body:             |
 
     %1 : gpr = COPY %r1
     %0 : gpr = COPY %r0
-    %2 : gpr = t2LDRi12 %1, 0, 14, _ :: (load 4 from %ir.y)
-    t2STRi12 killed %2, %0, 0, 14, _ :: (store 4 into %ir.x)
-    %3 : gpr = t2LDRi12 %1, 4, 14, _ :: (load 4 from %ir.arrayidx2)
-    t2STRi12 killed %3, %0, 4, 14, _ :: (store 4 into %ir.arrayidx3)
+    %2 : gpr = t2LDRi12 %1, 0, 14, %noreg :: (load 4 from %ir.y)
+    t2STRi12 killed %2, %0, 0, 14, %noreg :: (store 4 into %ir.x)
+    %3 : gpr = t2LDRi12 %1, 4, 14, %noreg :: (load 4 from %ir.arrayidx2)
+    t2STRi12 killed %3, %0, 4, 14, %noreg :: (store 4 into %ir.arrayidx3)
     ; CHECK: t2LDRi12
     ; CHECK-NEXT: t2LDRi12
     ; CHECK-NEXT: t2STRi12
     ; CHECK-NEXT: t2STRi12
-    tBX_RET 14, _
+    tBX_RET 14, %noreg
 
 ...
 

test/CodeGen/ARM/prera-ldst-insertpt.mir

@@ -28,14 +28,14 @@ body:             |
     %2 : rgpr = COPY %r2
     %1 : rgpr = COPY %r1
     %0 : gpr = COPY %r0
-    %3 : rgpr = t2MUL %2, %2, 14, _
-    %4 : rgpr = t2MUL %1, %1, 14, _
+    %3 : rgpr = t2MUL %2, %2, 14, %noreg
+    %4 : rgpr = t2MUL %1, %1, 14, %noreg
     %5 : rgpr = t2MOVi32imm -858993459
-    %6 : rgpr, %7 : rgpr  = t2UMULL killed %3, %5, 14, _
-    %8 : rgpr, %9 : rgpr  = t2UMULL killed %4, %5, 14, _
-    t2STRi12 %1, %0, 0, 14, _ :: (store 4)
-    %10 : rgpr = t2LSLri %2, 1, 14, _, _
-    t2STRi12 killed %10, %0, 4, 14, _ :: (store 4)
+    %6 : rgpr, %7 : rgpr  = t2UMULL killed %3, %5, 14, %noreg
+    %8 : rgpr, %9 : rgpr  = t2UMULL killed %4, %5, 14, %noreg
+    t2STRi12 %1, %0, 0, 14, %noreg :: (store 4)
+    %10 : rgpr = t2LSLri %2, 1, 14, %noreg, %noreg
+    t2STRi12 killed %10, %0, 4, 14, %noreg :: (store 4)
 
     ; Make sure we move the paired stores next to each other, and
     ; insert them in an appropriate location.
@@ -44,17 +44,17 @@ body:             |
     ; CHECK-NEXT: t2MOVi
     ; CHECK-NEXT: t2ADDrs
 
-    %11 : rgpr = t2MOVi 55, 14, _, _
-    %12 : gprnopc = t2ADDrs %11, killed %7, 19, 14, _, _
-    t2STRi12 killed %12, %0, 16, 14, _ :: (store 4)
-    %13 : gprnopc = t2ADDrs %11, killed %9, 19, 14, _, _
-    t2STRi12 killed %13, %0, 20, 14, _ :: (store 4)
+    %11 : rgpr = t2MOVi 55, 14, %noreg, %noreg
+    %12 : gprnopc = t2ADDrs %11, killed %7, 19, 14, %noreg, %noreg
+    t2STRi12 killed %12, %0, 16, 14, %noreg :: (store 4)
+    %13 : gprnopc = t2ADDrs %11, killed %9, 19, 14, %noreg, %noreg
+    t2STRi12 killed %13, %0, 20, 14, %noreg :: (store 4)
 
     ; Make sure we move the paired stores next to each other.
     ; CHECK: t2STRi12 killed %12,
     ; CHECK-NEXT: t2STRi12 killed %13,
 
-    tBX_RET 14, _
+    tBX_RET 14, %noreg
 ---
 # CHECK-LABEL: name: b
 name:            b
@@ -71,11 +71,11 @@ body:             |
     %2 : rgpr = COPY %r2
     %1 : rgpr = COPY %r1
     %0 : gpr = COPY %r0
-    t2STRi12 %1, %0, 0, 14, _ :: (store 4)
-    %10 : rgpr = t2LSLri %2, 1, 14, _, _
-    t2STRi12 killed %10, %0, 4, 14, _ :: (store 4)
-    %3 : rgpr = t2MUL %2, %2, 14, _
-    t2STRi12 %3, %0, 8, 14, _ :: (store 4)
+    t2STRi12 %1, %0, 0, 14, %noreg :: (store 4)
+    %10 : rgpr = t2LSLri %2, 1, 14, %noreg, %noreg
+    t2STRi12 killed %10, %0, 4, 14, %noreg :: (store 4)
+    %3 : rgpr = t2MUL %2, %2, 14, %noreg
+    t2STRi12 %3, %0, 8, 14, %noreg :: (store 4)
 
     ; Make sure we move the paired stores next to each other, and
     ; insert them in an appropriate location.
@@ -85,21 +85,21 @@ body:             |
     ; CHECK-NEXT: t2MUL
     ; CHECK-NEXT: t2MOVi32imm
 
-    %4 : rgpr = t2MUL %1, %1, 14, _
+    %4 : rgpr = t2MUL %1, %1, 14, %noreg
     %5 : rgpr = t2MOVi32imm -858993459
-    %6 : rgpr, %7 : rgpr  = t2UMULL killed %3, %5, 14, _
-    %8 : rgpr, %9 : rgpr  = t2UMULL killed %4, %5, 14, _
-    %10 : rgpr = t2LSLri %2, 1, 14, _, _
-    %11 : rgpr = t2MOVi 55, 14, _, _
-    %12 : gprnopc = t2ADDrs %11, killed %7, 19, 14, _, _
-    t2STRi12 killed %12, %0, 16, 14, _ :: (store 4)
-    %13 : gprnopc = t2ADDrs %11, killed %9, 19, 14, _, _
-    t2STRi12 killed %13, %0, 20, 14, _ :: (store 4)
+    %6 : rgpr, %7 : rgpr  = t2UMULL killed %3, %5, 14, %noreg
+    %8 : rgpr, %9 : rgpr  = t2UMULL killed %4, %5, 14, %noreg
+    %10 : rgpr = t2LSLri %2, 1, 14, %noreg, %noreg
+    %11 : rgpr = t2MOVi 55, 14, %noreg, %noreg
+    %12 : gprnopc = t2ADDrs %11, killed %7, 19, 14, %noreg, %noreg
+    t2STRi12 killed %12, %0, 16, 14, %noreg :: (store 4)
+    %13 : gprnopc = t2ADDrs %11, killed %9, 19, 14, %noreg, %noreg
+    t2STRi12 killed %13, %0, 20, 14, %noreg :: (store 4)
 
     ; Make sure we move the paired stores next to each other.
     ; CHECK: t2STRi12 {{.*}}, 16
     ; CHECK-NEXT: t2STRi12 {{.*}}, 20
 
-    tBX_RET 14, _
+    tBX_RET 14, %noreg
 
 ...

test/CodeGen/ARM/scavenging.mir

@@ -25,36 +25,36 @@ body: |
     %r7 = IMPLICIT_DEF
 
     %0 : tgpr = IMPLICIT_DEF
-    %0 = tADDhirr %0, %sp, 14, _
-    tSTRi %r0, %0, 0, 14, _
+    %0 = tADDhirr %0, %sp, 14, %noreg
+    tSTRi %r0, %0, 0, 14, %noreg
 
     %1 : tgpr = IMPLICIT_DEF
-    %1 = tADDhirr %1, %sp, 14, _
-    tSTRi %r1, %1, 0, 14, _
+    %1 = tADDhirr %1, %sp, 14, %noreg
+    tSTRi %r1, %1, 0, 14, %noreg
 
     %2 : tgpr = IMPLICIT_DEF
-    %2 = tADDhirr %2, %sp, 14, _
-    tSTRi %r2, %2, 0, 14, _
+    %2 = tADDhirr %2, %sp, 14, %noreg
+    tSTRi %r2, %2, 0, 14, %noreg
 
     %3 : tgpr = IMPLICIT_DEF
-    %3 = tADDhirr %3, %sp, 14, _
-    tSTRi %r3, %3, 0, 14, _
+    %3 = tADDhirr %3, %sp, 14, %noreg
+    tSTRi %r3, %3, 0, 14, %noreg
 
     %4 : tgpr = IMPLICIT_DEF
-    %4 = tADDhirr %4, %sp, 14, _
-    tSTRi %r4, %4, 0, 14, _
+    %4 = tADDhirr %4, %sp, 14, %noreg
+    tSTRi %r4, %4, 0, 14, %noreg
 
     %5 : tgpr = IMPLICIT_DEF
-    %5 = tADDhirr %5, %sp, 14, _
-    tSTRi %r5, %5, 0, 14, _
+    %5 = tADDhirr %5, %sp, 14, %noreg
+    tSTRi %r5, %5, 0, 14, %noreg
 
     %6 : tgpr = IMPLICIT_DEF
-    %6 = tADDhirr %6, %sp, 14, _
-    tSTRi %r6, %6, 0, 14, _
+    %6 = tADDhirr %6, %sp, 14, %noreg
+    tSTRi %r6, %6, 0, 14, %noreg
 
     %7 : tgpr = IMPLICIT_DEF
-    %7 = tADDhirr %7, %sp, 14, _
-    tSTRi %r7, %7, 0, 14, _
+    %7 = tADDhirr %7, %sp, 14, %noreg
+    tSTRi %r7, %7, 0, 14, %noreg
 
     KILL %r0
     KILL %r1

test/CodeGen/ARM/sched-it-debug-nodes.mir

@@ -131,27 +131,27 @@ body:             |
   bb.0.entry:
     liveins: %r0, %r1, %r2, %r3, %lr, %r7
 
-    DBG_VALUE debug-use %r0, debug-use _, !18, !27, debug-location !28
-    DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28
-    DBG_VALUE debug-use %r2, debug-use _, !20, !27, debug-location !28
-    DBG_VALUE debug-use %r3, debug-use _, !21, !27, debug-location !28
-    t2CMPri %r3, 4, 14, _, implicit-def %cpsr, debug-location !31
-    DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28
-    %r0 = t2MOVi -1, 3, %cpsr, _, implicit undef %r0
-    DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28
+    DBG_VALUE debug-use %r0, debug-use %noreg, !18, !27, debug-location !28
+    DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
+    DBG_VALUE debug-use %r2, debug-use %noreg, !20, !27, debug-location !28
+    DBG_VALUE debug-use %r3, debug-use %noreg, !21, !27, debug-location !28
+    t2CMPri %r3, 4, 14, %noreg, implicit-def %cpsr, debug-location !31
+    DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
+    %r0 = t2MOVi -1, 3, %cpsr, %noreg, implicit undef %r0
+    DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
     tBX_RET 3, %cpsr, implicit %r0, debug-location !34
-    %sp = frame-setup t2STMDB_UPD %sp, 14, _, killed %r7, killed %lr
+    %sp = frame-setup t2STMDB_UPD %sp, 14, %noreg, killed %r7, killed %lr
     frame-setup CFI_INSTRUCTION def_cfa_offset 8
     frame-setup CFI_INSTRUCTION offset %lr, -4
     frame-setup CFI_INSTRUCTION offset %r7, -8
-    DBG_VALUE debug-use %r0, debug-use _, !18, !27, debug-location !28
-    DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28
-    DBG_VALUE debug-use %r2, debug-use _, !20, !27, debug-location !28
-    DBG_VALUE debug-use %r3, debug-use _, !21, !27, debug-location !28
-    %r1 = tMOVr killed %r2, 14, _, debug-location !32
-    %r2 = tMOVr killed %r3, 14, _, debug-location !32
-    tBL 14, _, @g, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit-def %sp, debug-location !32
-    %r0 = t2MOVi 0, 14, _, _
-    %sp = t2LDMIA_RET %sp, 14, _, def %r7, def %pc, implicit %r0
+    DBG_VALUE debug-use %r0, debug-use %noreg, !18, !27, debug-location !28
+    DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
+    DBG_VALUE debug-use %r2, debug-use %noreg, !20, !27, debug-location !28
+    DBG_VALUE debug-use %r3, debug-use %noreg, !21, !27, debug-location !28
+    %r1 = tMOVr killed %r2, 14, %noreg, debug-location !32
+    %r2 = tMOVr killed %r3, 14, %noreg, debug-location !32
+    tBL 14, %noreg, @g, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit-def %sp, debug-location !32
+    %r0 = t2MOVi 0, 14, %noreg, %noreg
+    %sp = t2LDMIA_RET %sp, 14, %noreg, def %r7, def %pc, implicit %r0
 
 ...

test/CodeGen/ARM/single-issue-r52.mir

@@ -76,11 +76,11 @@ body:             |
     liveins: %r0
 
     %0 = COPY %r0
-    %1 = VLD4d8Pseudo %0, 8, 14, _ :: (load 32 from %ir.A, align 8)
-    %4 = VADDv8i8 %1.dsub_0, %1.dsub_1, 14, _
-    %5, %6 = VMOVRRD %4, 14, _
+    %1 = VLD4d8Pseudo %0, 8, 14, %noreg :: (load 32 from %ir.A, align 8)
+    %4 = VADDv8i8 %1.dsub_0, %1.dsub_1, 14, %noreg
+    %5, %6 = VMOVRRD %4, 14, %noreg
     %r0 = COPY %5
     %r1 = COPY %6
-    BX_RET 14, _, implicit %r0, implicit killed %r1
+    BX_RET 14, %noreg, implicit %r0, implicit killed %r1
 
 ...

test/CodeGen/ARM/tail-dup-bundle.mir

@@ -19,7 +19,7 @@ body: |
   bb.1:
     liveins: %r0
 
-    t2CMPri %r0, 32, 14, _, implicit-def %cpsr
+    t2CMPri %r0, 32, 14, %noreg, implicit-def %cpsr
     BUNDLE implicit-def dead %itstate, implicit-def %cpsr, implicit killed %r0, implicit killed %cpsr {
       t2IT 1, 24, implicit-def %itstate
       t2CMPri killed %r0, 9, 1, killed %cpsr, implicit-def %cpsr, implicit internal killed %itstate
@@ -28,9 +28,9 @@ body: |
 
   bb.2:
     %r0 = IMPLICIT_DEF
-    t2B %bb.1, 14, _
+    t2B %bb.1, 14, %noreg
 
   bb.3:
     %r0 = IMPLICIT_DEF
-    t2B %bb.1, 14, _
+    t2B %bb.1, 14, %noreg
 ...

test/CodeGen/ARM/thumb-litpool.ll

@@ -12,4 +12,4 @@ define void @foo() minsize {
   call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7}"()
   call void @callee(i8* @var)
   ret void
-}
+}

test/CodeGen/ARM/v6-jumptable-clobber.mir

@@ -231,21 +231,21 @@ body:             |
     successors: %bb.2.d1(0x03c3c3c4), %bb.1(0x7c3c3c3c)
     liveins: %r0, %r1
   
-    %r2 = tLDRpci %const.0, 14, _
-    tSTRi killed %r2, killed %r1, 0, 14, _ :: (store 4 into %ir.addr)
+    %r2 = tLDRpci %const.0, 14, %noreg
+    tSTRi killed %r2, killed %r1, 0, 14, %noreg :: (store 4 into %ir.addr)
     dead %r1 = SPACE 980, undef %r0
-    %r0 = tUXTB killed %r0, 14, _
-    %r1, dead %cpsr = tSUBi3 killed %r0, 1, 14, _
-    tCMPi8 %r1, 25, 14, _, implicit-def %cpsr
+    %r0 = tUXTB killed %r0, 14, %noreg
+    %r1, dead %cpsr = tSUBi3 killed %r0, 1, 14, %noreg
+    tCMPi8 %r1, 25, 14, %noreg, implicit-def %cpsr
     tBcc %bb.2.d1, 8, killed %cpsr
   
   bb.1 (%ir-block.0):
     successors: %bb.3.d2(0x07c549d2), %bb.9.d8(0x07c549d2), %bb.4.d3(0x07c549d2), %bb.5.d4(0x07c549d2), %bb.6.d5(0x07c549d2), %bb.7.d6(0x07c549d2), %bb.8.d7(0x07c549d2), %bb.10.d9(0x07c549d2), %bb.11.d10(0x07c549d2), %bb.2.d1(0x03ab62db), %bb.12.d11(0x07c549d2), %bb.13.d12(0x07c549d2), %bb.14.d13(0x07c549d2), %bb.15.d14(0x07c549d2), %bb.16.d15(0x07c549d2), %bb.17.d16(0x07c549d2), %bb.18.d17(0x07c549d2)
     liveins: %r1
   
-    %r0, dead %cpsr = tLSLri killed %r1, 2, 14, _
-    %r1 = tLEApcrelJT %jump-table.0, 14, _
-    %r0 = tLDRr killed %r1, killed %r0, 14, _ :: (load 4 from jump-table)
+    %r0, dead %cpsr = tLSLri killed %r1, 2, 14, %noreg
+    %r1 = tLEApcrelJT %jump-table.0, 14, %noreg
+    %r0 = tLDRr killed %r1, killed %r0, 14, %noreg :: (load 4 from jump-table)
     tBR_JTr killed %r0, %jump-table.0
   
   bb.3.d2:
@@ -329,20 +329,20 @@ body:             |
     successors: %bb.2.d1(0x03c3c3c4), %bb.1(0x7c3c3c3c)
     liveins: %r0, %r1
   
-    %r2 = tLDRpci %const.0, 14, _
-    tSTRi killed %r2, killed %r1, 0, 14, _ :: (store 4 into %ir.addr)
-    %r0 = tUXTB killed %r0, 14, _
-    %r1, dead %cpsr = tSUBi3 killed %r0, 1, 14, _
-    tCMPi8 %r1, 25, 14, _, implicit-def %cpsr
+    %r2 = tLDRpci %const.0, 14, %noreg
+    tSTRi killed %r2, killed %r1, 0, 14, %noreg :: (store 4 into %ir.addr)
+    %r0 = tUXTB killed %r0, 14, %noreg
+    %r1, dead %cpsr = tSUBi3 killed %r0, 1, 14, %noreg
+    tCMPi8 %r1, 25, 14, %noreg, implicit-def %cpsr
     tBcc %bb.2.d1, 8, killed %cpsr
   
   bb.1 (%ir-block.0):
     successors: %bb.3.d2(0x07c549d2), %bb.9.d8(0x07c549d2), %bb.4.d3(0x07c549d2), %bb.5.d4(0x07c549d2), %bb.6.d5(0x07c549d2), %bb.7.d6(0x07c549d2), %bb.8.d7(0x07c549d2), %bb.10.d9(0x07c549d2), %bb.11.d10(0x07c549d2), %bb.2.d1(0x03ab62db), %bb.12.d11(0x07c549d2), %bb.13.d12(0x07c549d2), %bb.14.d13(0x07c549d2), %bb.15.d14(0x07c549d2), %bb.16.d15(0x07c549d2), %bb.17.d16(0x07c549d2), %bb.18.d17(0x07c549d2)
     liveins: %r1
   
-    %r0, dead %cpsr = tLSLri killed %r1, 2, 14, _
-    %r1 = tLEApcrelJT %jump-table.0, 14, _
-    %r0 = tLDRr killed %r1, killed %r0, 14, _ :: (load 4 from jump-table)
+    %r0, dead %cpsr = tLSLri killed %r1, 2, 14, %noreg
+    %r1 = tLEApcrelJT %jump-table.0, 14, %noreg
+    %r0 = tLDRr killed %r1, killed %r0, 14, %noreg :: (load 4 from jump-table)
     tBR_JTr killed %r0, %jump-table.0
   
   bb.3.d2:

test/CodeGen/ARM/vcvt_combine.ll

@@ -69,4 +69,4 @@ define <3 x i32> @test_illegal_fp_to_int(<3 x float> %in) {
   %scale = fmul <3 x float> %in, <float 4.0, float 4.0, float 4.0>
   %val = fptosi <3 x float> %scale to <3 x i32>
   ret <3 x i32> %val
-}
+}

test/CodeGen/ARM/vdiv_combine.ll

@@ -160,4 +160,4 @@ define <3 x float> @test_illegal_int_to_fp(<3 x i32> %in) {
   %conv = sitofp <3 x i32> %in to <3 x float>
   %res = fdiv <3 x float> %conv, <float 4.0, float 4.0, float 4.0>
   ret <3 x float> %res
-}
+}

test/CodeGen/ARM/virtregrewriter-subregliveness.mir

@@ -33,7 +33,7 @@ body:             |
     ; CHECK-NEXT: %r1 = KILL %r1, implicit killed %r0_r1
     undef %0.gsub_0 = COPY %r0
     %0.gsub_1 = COPY %r1
-    tBX_RET 14, _, implicit %0
+    tBX_RET 14, %noreg, implicit %0
   
 
 ...
@@ -55,7 +55,7 @@ body:             |
     ; CHECK: %r0 = KILL %r0, implicit-def %r0_r1
     ; CHECK-NEXT: tBX_RET
     undef %0.gsub_0 = COPY %r0
-    tBX_RET 14, _, implicit %0
+    tBX_RET 14, %noreg, implicit %0
   
 
 ...
@@ -78,7 +78,7 @@ body:             |
     ; CHECK: %r0 = KILL %r0, implicit-def %r1, implicit-def %r0_r1
     ; CHECK-NEXT: tBX_RET
     undef %0.gsub_0 = COPY %r0, implicit-def %r1
-    tBX_RET 14, _, implicit %0
+    tBX_RET 14, %noreg, implicit %0
   
 
 ...

test/CodeGen/ARM/vldm-liveness.mir

@@ -26,15 +26,15 @@ body:             |
   bb.0 (%ir-block.0):
     liveins: %r0
 
-    %s1 = VLDRS %r0, 1, 14, _, implicit-def %q0 :: (load 4)
-    %s3 = VLDRS %r0, 2, 14, _, implicit killed %q0, implicit-def %q0 :: (load 4)
-    ; CHECK: %s3 = VLDRS %r0, 2, 14, _, implicit killed undef %q0, implicit-def %q0 :: (load 4)
+    %s1 = VLDRS %r0, 1, 14, %noreg, implicit-def %q0 :: (load 4)
+    %s3 = VLDRS %r0, 2, 14, %noreg, implicit killed %q0, implicit-def %q0 :: (load 4)
+    ; CHECK: %s3 = VLDRS %r0, 2, 14, %noreg, implicit killed undef %q0, implicit-def %q0 :: (load 4)
 
-    %s0 = VLDRS %r0, 0, 14, _, implicit killed %q0, implicit-def %q0 :: (load 4)
-    ; CHECK: VLDMSIA %r0, 14, _, def %s0, def %s1, implicit-def _
+    %s0 = VLDRS %r0, 0, 14, %noreg, implicit killed %q0, implicit-def %q0 :: (load 4)
+    ; CHECK: VLDMSIA %r0, 14, %noreg, def %s0, def %s1, implicit-def %noreg
 
-    %s2 = VLDRS killed %r0, 4, 14, _, implicit killed %q0, implicit-def %q0 :: (load 4)
-    ; CHECK: %s2 = VLDRS killed %r0, 4, 14, _, implicit killed %q0, implicit-def %q0 :: (load 4)
+    %s2 = VLDRS killed %r0, 4, 14, %noreg, implicit killed %q0, implicit-def %q0 :: (load 4)
+    ; CHECK: %s2 = VLDRS killed %r0, 4, 14, %noreg, implicit killed %q0, implicit-def %q0 :: (load 4)
 
-    tBX_RET 14, _, implicit %q0
+    tBX_RET 14, %noreg, implicit %q0
 ...

test/CodeGen/Hexagon/duplex.ll

@@ -4,4 +4,4 @@
 
 define i32 @foo() {
 ret i32 0
-}
+}

test/CodeGen/Hexagon/early-if-debug.mir

@@ -6,11 +6,11 @@
 # CHECK: %0:intregs = COPY %r0
 # CHECK: %1:predregs = C2_cmpeqi %0, 0
 # CHECK: %2:intregs = A2_tfrsi 123
-# CHECK: DBG_VALUE debug-use %0, debug-use _
-# CHECK: DBG_VALUE debug-use %0, debug-use _
-# CHECK: DBG_VALUE debug-use %0, debug-use _
-# CHECK: DBG_VALUE debug-use %0, debug-use _
-# CHECK: DBG_VALUE debug-use %0, debug-use _
+# CHECK: DBG_VALUE debug-use %0, debug-use %noreg
+# CHECK: DBG_VALUE debug-use %0, debug-use %noreg
+# CHECK: DBG_VALUE debug-use %0, debug-use %noreg
+# CHECK: DBG_VALUE debug-use %0, debug-use %noreg
+# CHECK: DBG_VALUE debug-use %0, debug-use %noreg
 # CHECK: %3:intregs = A2_tfrsi 321
 # CHECK: %5:intregs = C2_mux %1, %2, %3
 
@@ -40,11 +40,11 @@ body:             |
     J2_jump %bb.1, implicit-def dead %pc
 
   bb.1:
-    DBG_VALUE debug-use %0, debug-use _, !1, !1
-    DBG_VALUE debug-use %0, debug-use _, !1, !1
-    DBG_VALUE debug-use %0, debug-use _, !1, !1
-    DBG_VALUE debug-use %0, debug-use _, !1, !1
-    DBG_VALUE debug-use %0, debug-use _, !1, !1
+    DBG_VALUE debug-use %0, debug-use %noreg, !1, !1
+    DBG_VALUE debug-use %0, debug-use %noreg, !1, !1
+    DBG_VALUE debug-use %0, debug-use %noreg, !1, !1
+    DBG_VALUE debug-use %0, debug-use %noreg, !1, !1
+    DBG_VALUE debug-use %0, debug-use %noreg, !1, !1
     %3 = A2_tfrsi 321
 
   bb.2:

test/CodeGen/MIR/ARM/bundled-instructions.mir

@@ -28,14 +28,14 @@ body: |
   bb.0.entry:
     liveins: %r0
     ; CHECK-LABEL: name: test1
-    ; CHECK:      %r1 = t2MOVi 0, 14, _, _
-    ; CHECK-NEXT: t2CMNri killed %r0, 78, 14, _, implicit-def %cpsr
+    ; CHECK:      %r1 = t2MOVi 0, 14, %noreg, %noreg
+    ; CHECK-NEXT: t2CMNri killed %r0, 78, 14, %noreg, implicit-def %cpsr
     ; CHECK-NEXT: BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr {
     ; CHECK-NEXT:   t2IT 12, 8, implicit-def %itstate
-    ; CHECK-NEXT:   %r1 = t2MOVi 1, 12, killed %cpsr, _, implicit internal killed %itstate
+    ; CHECK-NEXT:   %r1 = t2MOVi 1, 12, killed %cpsr, %noreg, implicit internal killed %itstate
     ; CHECK-NEXT: }
-    ; CHECK-NEXT: %r0 = tMOVr killed %r1, 14, _
-    ; CHECK-NEXT: tBX_RET 14, _, implicit killed %r0
+    ; CHECK-NEXT: %r0 = tMOVr killed %r1, 14, %noreg
+    ; CHECK-NEXT: tBX_RET 14, %noreg, implicit killed %r0
     %r1 = t2MOVi 0, 14, _, _
     t2CMNri killed %r0, 78, 14, _, implicit-def %cpsr
     BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr {
@@ -58,14 +58,14 @@ body: |
     ; '{' or '}'.
 
     ; CHECK-LABEL: name: test2
-    ; CHECK:      %r1 = t2MOVi 0, 14, _, _
-    ; CHECK-NEXT: t2CMNri killed %r0, 78, 14, _, implicit-def %cpsr
+    ; CHECK:      %r1 = t2MOVi 0, 14, %noreg, %noreg
+    ; CHECK-NEXT: t2CMNri killed %r0, 78, 14, %noreg, implicit-def %cpsr
     ; CHECK-NEXT: BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr {
     ; CHECK-NEXT:   t2IT 12, 8, implicit-def %itstate
-    ; CHECK-NEXT:   %r1 = t2MOVi 1, 12, killed %cpsr, _, implicit internal killed %itstate
+    ; CHECK-NEXT:   %r1 = t2MOVi 1, 12, killed %cpsr, %noreg, implicit internal killed %itstate
     ; CHECK-NEXT: }
-    ; CHECK-NEXT: %r0 = tMOVr killed %r1, 14, _
-    ; CHECK-NEXT: tBX_RET 14, _, implicit killed %r0
+    ; CHECK-NEXT: %r0 = tMOVr killed %r1, 14, %noreg
+    ; CHECK-NEXT: tBX_RET 14, %noreg, implicit killed %r0
     %r1 = t2MOVi 0, 14, _, _
     t2CMNri killed %r0, 78, 14, _, implicit-def %cpsr
     BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr { t2IT 12, 8, implicit-def %itstate

test/CodeGen/MIR/ARM/ifcvt_diamond_unanalyzable.mir

@@ -26,5 +26,5 @@ body:             |
 # CHECK:   bb.0:
 # CHECK:     %sp = tADDspi %sp, 2, 1, %cpsr
 # CHECK:     %sp = tADDspi %sp, 1, 0, %cpsr, implicit %sp
-# CHECK:     %sp = tADDspi %sp, 3, 14, _
-# CHECK:     BX_RET 14, _
+# CHECK:     %sp = tADDspi %sp, 3, 14, %noreg
+# CHECK:     BX_RET 14, %noreg

test/CodeGen/MIR/ARM/ifcvt_forked_diamond_unanalyzable.mir

@@ -40,9 +40,9 @@ body:             |
 # CHECK:     Bcc %bb.2, 1, %cpsr
 
 # CHECK:   bb.1:
-# CHECK:     %sp = tADDspi %sp, 4, 14, _
-# CHECK:     BX_RET 14, _
+# CHECK:     %sp = tADDspi %sp, 4, 14, %noreg
+# CHECK:     BX_RET 14, %noreg
 
 # CHECK:   bb.2:
-# CHECK:     %sp = tADDspi %sp, 3, 14, _
-# CHECK:     BX_RET 14, _
+# CHECK:     %sp = tADDspi %sp, 3, 14, %noreg
+# CHECK:     BX_RET 14, %noreg

test/CodeGen/MIR/ARM/ifcvt_simple_unanalyzable.mir

@@ -21,5 +21,5 @@ body:             |
 # CHECK:   bb.0:
 # CHECK:     %sp = tADDspi %sp, 2, 0, %cpsr
 # CHECK:     BX_RET 0, %cpsr
-# CHECK:     BX_RET 14, _
+# CHECK:     BX_RET 14, %noreg
 

test/CodeGen/MIR/ARM/ifcvt_triangleWoCvtToNextEdge.mir

@@ -47,6 +47,6 @@ body:             |
 # CHECK:     bb.2:
 # CHECK-NOT:   successors: %bb
 # CHECK:       tBL 1, %cpsr, @__stack_chk_fail
-# CHECK:       %sp = tADDspi %sp, 2, 14, _
-# CHECK:       %sp = tADDspi %sp, 2, 14, _
+# CHECK:       %sp = tADDspi %sp, 2, 14, %noreg
+# CHECK:       %sp = tADDspi %sp, 2, 14, %noreg
 # CHECK:       tTAILJMPdND @bar, 14, %cpsr

test/CodeGen/MIR/X86/block-address-operands.mir

@@ -57,7 +57,7 @@ name:            test
 body: |
   bb.0.entry:
     successors: %bb.1.block
-  ; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block), _
+  ; CHECK: %rax = LEA64r %rip, 1, %noreg, blockaddress(@test, %ir-block.block), %noreg
     %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block), _
     MOV64mr %rip, 1, _, @addr, _, killed %rax
     JMP64m %rip, 1, _, @addr, _
@@ -71,7 +71,7 @@ tracksRegLiveness: true
 body: |
   bb.0.entry:
     successors: %bb.1
-  ; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test2, %ir-block."quoted block"), _
+  ; CHECK: %rax = LEA64r %rip, 1, %noreg, blockaddress(@test2, %ir-block."quoted block"), %noreg
     %rax = LEA64r %rip, 1, _, blockaddress(@test2, %ir-block."quoted block"), _
     MOV64mr %rip, 1, _, @addr, _, killed %rax
     JMP64m %rip, 1, _, @addr, _
@@ -86,7 +86,7 @@ body: |
   bb.0.entry:
     liveins: %rdi
   ; CHECK-LABEL: name: slot_in_other_function
-  ; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _
+  ; CHECK: %rax = LEA64r %rip, 1, %noreg, blockaddress(@test3, %ir-block.0), %noreg
     %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _
     MOV64mr killed %rdi, 1, _, 0, _, killed %rax
     RETQ
@@ -98,7 +98,7 @@ body: |
   bb.0.entry:
     successors: %bb.1
   ; CHECK-LABEL: name: test3
-  ; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _
+  ; CHECK: %rax = LEA64r %rip, 1, %noreg, blockaddress(@test3, %ir-block.0), %noreg
     %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _
     MOV64mr %rip, 1, _, @addr, _, killed %rax
     JMP64m %rip, 1, _, @addr, _
@@ -111,7 +111,7 @@ name:            test4
 body: |
   bb.0.entry:
     successors: %bb.1.block
-  ; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block) + 2, _
+  ; CHECK: %rax = LEA64r %rip, 1, %noreg, blockaddress(@test, %ir-block.block) + 2, %noreg
     %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block) + 2, _
     MOV64mr %rip, 1, _, @addr, _, killed %rax
     JMP64m %rip, 1, _, @addr, _

test/CodeGen/MIR/X86/constant-pool.mir

@@ -61,8 +61,8 @@ constants:
     alignment:   4
 body: |
   bb.0.entry:
-    ; CHECK:      %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
-    ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
+    ; CHECK:      %xmm0 = ADDSDrm killed %xmm0, %rip, 1, %noreg, %const.0, %noreg
+    ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, %noreg, %const.1, %noreg
     %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
     %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
     %xmm1 = CVTSS2SDrr killed %xmm1
@@ -117,8 +117,8 @@ constants:
     alignment:   1
 body: |
   bb.0.entry:
-    ; CHECK:      %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
-    ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
+    ; CHECK:      %xmm0 = ADDSDrm killed %xmm0, %rip, 1, %noreg, %const.0, %noreg
+    ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, %noreg, %const.1, %noreg
     %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
     %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
     %xmm1 = CVTSS2SDrr killed %xmm1
@@ -135,8 +135,8 @@ constants:
     value:       'float 6.250000e+00'
 body: |
   bb.0.entry:
-    ; CHECK:      %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.1 - 12, _
-    ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.0 + 8, _
+    ; CHECK:      %xmm0 = ADDSDrm killed %xmm0, %rip, 1, %noreg, %const.1 - 12, %noreg
+    ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, %noreg, %const.0 + 8, %noreg
     %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.1 - 12, _
     %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.0 + 8, _
     %xmm1 = CVTSS2SDrr killed %xmm1

test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir

@@ -31,7 +31,7 @@ body: |
     frame-setup PUSH32r undef %eax, implicit-def %esp, implicit %esp
     CFI_INSTRUCTION def_cfa_offset 8
   ; CHECK: name: test
-  ; CHECK: %eax = MOV32rm %esp, 1, _, 8, _ :: (load 4 from %fixed-stack.0, align 16)
+  ; CHECK: %eax = MOV32rm %esp, 1, %noreg, 8, %noreg :: (load 4 from %fixed-stack.0, align 16)
     %eax = MOV32rm %esp, 1, _, 8, _ :: (load 4 from %fixed-stack.0, align 16)
     MOV32mr %esp, 1, _, 0, _, %eax :: (store 4 into %ir.b)
     %edx = POP32r implicit-def %esp, implicit %esp

test/CodeGen/MIR/X86/global-value-operands.mir

@@ -64,7 +64,7 @@
 name: inc
 body: |
   bb.0.entry:
-    ; CHECK: %rax = MOV64rm %rip, 1, _, @G, _
+    ; CHECK: %rax = MOV64rm %rip, 1, %noreg, @G, %noreg
     %rax = MOV64rm %rip, 1, _, @G, _
     %eax = MOV32rm %rax, 1, _, 0, _
     %eax = INC32r %eax, implicit-def %eflags
@@ -75,7 +75,7 @@ body: |
 name: inc2
 body: |
   bb.0.entry:
-    ; CHECK: %rax = MOV64rm %rip, 1, _, @0, _
+    ; CHECK: %rax = MOV64rm %rip, 1, %noreg, @0, %noreg
     %rax = MOV64rm %rip, 1, _, @0, _
     %eax = MOV32rm %rax, 1, _, 0, _
     %eax = INC32r %eax, implicit-def %eflags
@@ -132,7 +132,7 @@ body: |
 name: tf
 body: |
   bb.0.entry:
-  ; CHECK: %rax = MOV64rm %rip, 1, _, target-flags(x86-gotpcrel) @G, _
+  ; CHECK: %rax = MOV64rm %rip, 1, %noreg, target-flags(x86-gotpcrel) @G, %noreg
     %rax = MOV64rm %rip, 1, _, target-flags(x86-gotpcrel) @G, _
     %eax = MOV32rm %rax, 1, _, 0, _
     %eax = INC32r %eax, implicit-def %eflags

test/CodeGen/MIR/X86/instructions-debug-location.mir

@@ -59,7 +59,7 @@ stack:
 body: |
   bb.0.entry:
     liveins: %edi
-    ; CHECK: DBG_VALUE debug-use _, 0, !11, !DIExpression(), debug-location !12
+    ; CHECK: DBG_VALUE debug-use %noreg, 0, !11, !DIExpression(), debug-location !12
     ; CHECK: %eax = COPY %0, debug-location !13
     ; CHECK: RETQ %eax, debug-location !13
     %0 = COPY %edi
@@ -82,9 +82,9 @@ body: |
     liveins: %edi
 
     %0 = COPY %edi
-  ; CHECK:      DBG_VALUE _, i32 0, !DIExpression(), !12
-  ; CHECK-NEXT: DBG_VALUE _, i64 -22, !DIExpression(), !12
-  ; CHECK-NEXT: DBG_VALUE _, i128 123492148938512984928424384934328985928, !DIExpression(), !12
+  ; CHECK:      DBG_VALUE %noreg, i32 0, !DIExpression(), !12
+  ; CHECK-NEXT: DBG_VALUE %noreg, i64 -22, !DIExpression(), !12
+  ; CHECK-NEXT: DBG_VALUE %noreg, i128 123492148938512984928424384934328985928, !DIExpression(), !12
     DBG_VALUE _, i32 0, !DIExpression(), !13
     DBG_VALUE _, i64 -22, !DIExpression(), !13
     DBG_VALUE _, i128 123492148938512984928424384934328985928, !DIExpression(), !13

test/CodeGen/MIR/X86/jump-table-info.mir

@@ -78,7 +78,7 @@ body: |
 
   bb.1.entry:
     successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4
-    ; CHECK: %rcx = LEA64r %rip, 1, _, %jump-table.0, _
+    ; CHECK: %rcx = LEA64r %rip, 1, %noreg, %jump-table.0, %noreg
     %rcx = LEA64r %rip, 1, _, %jump-table.0, _
     %rax = MOVSX64rm32 %rcx, 4, %rax, 0, _
     %rax = ADD64rr %rax, %rcx, implicit-def %eflags
@@ -122,7 +122,7 @@ body: |
   bb.1.entry:
     successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4
     ; Verify that the printer will use an id of 0 for this jump table:
-    ; CHECK: %rcx = LEA64r %rip, 1, _, %jump-table.0, _
+    ; CHECK: %rcx = LEA64r %rip, 1, %noreg, %jump-table.0, %noreg
     %rcx = LEA64r %rip, 1, _, %jump-table.1, _
     %rax = MOVSX64rm32 %rcx, 4, %rax, 0, _
     %rax = ADD64rr %rax, %rcx, implicit-def %eflags

test/CodeGen/MIR/X86/memory-operands.mir

@@ -198,8 +198,8 @@ liveins:
 body: |
   bb.0.entry:
     liveins: %rdi
-  ; CHECK:      %eax = MOV32rm %rdi, 1, _, 0, _ :: (load 4 from %ir.a)
-  ; CHECK-NEXT: MOV32mi killed %rdi, 1, _, 0, _, 42 :: (store 4 into %ir.a)
+  ; CHECK:      %eax = MOV32rm %rdi, 1, %noreg, 0, %noreg :: (load 4 from %ir.a)
+  ; CHECK-NEXT: MOV32mi killed %rdi, 1, %noreg, 0, %noreg, 42 :: (store 4 into %ir.a)
     %eax = MOV32rm %rdi, 1, _, 0, _ :: (load 4 from %ir.a)
     MOV32mi killed %rdi, 1, _, 0, _, 42 :: (store 4 into %ir.a)
     RETQ %eax
@@ -212,7 +212,7 @@ liveins:
 body: |
   bb.0.entry2:
     liveins: %rdi
-  ; CHECK: INC32m killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (store 4 into %ir."a value"), (load 4 from %ir."a value")
+  ; CHECK: INC32m killed %rdi, 1, %noreg, 0, %noreg, implicit-def dead %eflags :: (store 4 into %ir."a value"), (load 4 from %ir."a value")
     INC32m killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (store 4 into %ir."a value"), (load 4 from %ir."a value")
     RETQ
 ...
@@ -230,8 +230,8 @@ body: |
     liveins: %rdi
   ; Verify that the unnamed local values can be serialized.
   ; CHECK-LABEL: name: test3
-  ; CHECK: %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from %ir.0)
-  ; CHECK: MOV32mr %rsp, 1, _, -4, _, killed %eax :: (store 4 into %ir.1)
+  ; CHECK: %eax = MOV32rm killed %rdi, 1, %noreg, 0, %noreg :: (load 4 from %ir.0)
+  ; CHECK: MOV32mr %rsp, 1, %noreg, -4, %noreg, killed %eax :: (store 4 into %ir.1)
     %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from %ir.0)
     %eax = INC32r killed %eax, implicit-def dead %eflags
     MOV32mr %rsp, 1, _, -4, _, killed %eax :: (store 4 into %ir.1)
@@ -246,8 +246,8 @@ body: |
   bb.0.entry:
     liveins: %rdi
     ; CHECK: name: volatile_inc
-    ; CHECK: %eax = MOV32rm %rdi, 1, _, 0, _ :: (volatile load 4 from %ir.x)
-    ; CHECK: MOV32mr killed %rdi, 1, _, 0, _, %eax :: (volatile store 4 into %ir.x)
+    ; CHECK: %eax = MOV32rm %rdi, 1, %noreg, 0, %noreg :: (volatile load 4 from %ir.x)
+    ; CHECK: MOV32mr killed %rdi, 1, %noreg, 0, %noreg, %eax :: (volatile store 4 into %ir.x)
     %eax = MOV32rm %rdi, 1, _, 0, _ :: (volatile load 4 from %ir.x)
     %eax = INC32r killed %eax, implicit-def dead %eflags
     MOV32mr killed %rdi, 1, _, 0, _, %eax :: (volatile store 4 into %ir.x)
@@ -263,7 +263,7 @@ body: |
   bb.0.entry:
     liveins: %esi, %rdi
   ; CHECK: name: non_temporal_store
-  ; CHECK: MOVNTImr killed %rdi, 1, _, 0, _, killed %esi :: (non-temporal store 4 into %ir.a)
+  ; CHECK: MOVNTImr killed %rdi, 1, %noreg, 0, %noreg, killed %esi :: (non-temporal store 4 into %ir.a)
     MOVNTImr killed %rdi, 1, _, 0, _, killed %esi :: (non-temporal store 4 into %ir.a)
     RETQ
 ...
@@ -276,7 +276,7 @@ body: |
   bb.0.entry:
     liveins: %rdi
   ; CHECK: name: invariant_load
-  ; CHECK: %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (invariant load 4 from %ir.x)
+  ; CHECK: %eax = MOV32rm killed %rdi, 1, %noreg, 0, %noreg :: (invariant load 4 from %ir.x)
     %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (invariant load 4 from %ir.x)
     RETQ %eax
 ...
@@ -289,10 +289,10 @@ body: |
   bb.0.entry:
     liveins: %rdi
   ; CHECK: name: memory_offset
-  ; CHECK:      %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec)
-  ; CHECK-NEXT: %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16)
-  ; CHECK:      MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec)
-  ; CHECK-NEXT: MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16)
+  ; CHECK:      %xmm0 = MOVAPSrm %rdi, 1, %noreg, 0, %noreg :: (load 16 from %ir.vec)
+  ; CHECK-NEXT: %xmm1 = MOVAPSrm %rdi, 1, %noreg, 16, %noreg :: (load 16 from %ir.vec + 16)
+  ; CHECK:      MOVAPSmr %rdi, 1, %noreg, 0, %noreg, killed %xmm0 :: (store 16 into %ir.vec)
+  ; CHECK-NEXT: MOVAPSmr killed %rdi, 1, %noreg, 16, %noreg, killed %xmm1 :: (store 16 into %ir.vec + 16)
     %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec)
     %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16)
     %xmm2 = FsFLD0SS
@@ -310,10 +310,10 @@ body: |
   bb.0.entry:
     liveins: %rdi
   ; CHECK: name: memory_alignment
-  ; CHECK:      %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align 32)
-  ; CHECK-NEXT: %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)
-  ; CHECK:      MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)
-  ; CHECK-NEXT: MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)
+  ; CHECK:      %xmm0 = MOVAPSrm %rdi, 1, %noreg, 0, %noreg :: (load 16 from %ir.vec, align 32)
+  ; CHECK-NEXT: %xmm1 = MOVAPSrm %rdi, 1, %noreg, 16, %noreg :: (load 16 from %ir.vec + 16, align 32)
+  ; CHECK:      MOVAPSmr %rdi, 1, %noreg, 0, %noreg, killed %xmm0 :: (store 16 into %ir.vec, align 32)
+  ; CHECK-NEXT: MOVAPSmr killed %rdi, 1, %noreg, 16, %noreg, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)
     %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align 32)
     %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)
     %xmm2 = FsFLD0SS
@@ -334,8 +334,8 @@ body: |
   bb.0.entry:
     liveins: %xmm0
   ; CHECK: name: constant_pool_psv
-  ; CHECK:      %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool)
-  ; CHECK-NEXT: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool + 8)
+  ; CHECK:      %xmm0 = ADDSDrm killed %xmm0, %rip, 1, %noreg, %const.0, %noreg :: (load 8 from constant-pool)
+  ; CHECK-NEXT: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, %noreg, %const.0, %noreg :: (load 8 from constant-pool + 8)
     %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool)
     %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool + 8)
     RETQ %xmm0
@@ -355,9 +355,9 @@ body: |
   bb.0.entry:
     %rsp = frame-setup SUB64ri8 %rsp, 24, implicit-def dead %eflags
     CFI_INSTRUCTION def_cfa_offset 32
-    LD_F80m %rsp, 1, _, 32, _, implicit-def dead %fpsw
+    LD_F80m %rsp, 1, %noreg, 32, %noreg, implicit-def dead %fpsw
   ; CHECK: name: stack_psv
-  ; CHECK: ST_FP80m %rsp, 1, _, 0, _, implicit-def dead %fpsw :: (store 10 into stack, align 16)
+  ; CHECK: ST_FP80m %rsp, 1, %noreg, 0, %noreg, implicit-def dead %fpsw :: (store 10 into stack, align 16)
     ST_FP80m %rsp, 1, _, 0, _, implicit-def dead %fpsw :: (store 10 into stack, align 16)
     CALL64pcrel32 $cosl, csr_64, implicit %rsp, implicit-def %rsp, implicit-def %fp0
     %rsp = ADD64ri8 %rsp, 24, implicit-def dead %eflags
@@ -369,7 +369,7 @@ tracksRegLiveness: true
 body: |
   bb.0.entry:
   ; CHECK: name: got_psv
-  ; CHECK: %rax = MOV64rm %rip, 1, _, @G, _ :: (load 8 from got)
+  ; CHECK: %rax = MOV64rm %rip, 1, %noreg, @G, %noreg :: (load 8 from got)
     %rax = MOV64rm %rip, 1, _, @G, _ :: (load 8 from got)
     %eax = MOV32rm killed %rax, 1, _, 0, _
     %eax = INC32r killed %eax, implicit-def dead %eflags
@@ -382,8 +382,8 @@ body: |
   bb.0.entry:
     %rax = MOV64rm %rip, 1, _, @G, _
   ; CHECK-LABEL: name: global_value
-  ; CHECK: %eax = MOV32rm killed %rax, 1, _, 0, _, implicit-def %rax :: (load 4 from @G)
-  ; CHECK: %ecx = MOV32rm killed %rcx, 1, _, 0, _, implicit-def %rcx :: (load 4 from @0)
+  ; CHECK: %eax = MOV32rm killed %rax, 1, %noreg, 0, %noreg, implicit-def %rax :: (load 4 from @G)
+  ; CHECK: %ecx = MOV32rm killed %rcx, 1, %noreg, 0, %noreg, implicit-def %rcx :: (load 4 from @0)
     %eax = MOV32rm killed %rax, 1, _, 0, _, implicit-def %rax :: (load 4 from @G)
     %rcx = MOV64rm %rip, 1, _, @0, _
     %ecx = MOV32rm killed %rcx, 1, _, 0, _, implicit-def %rcx :: (load 4 from @0)
@@ -415,7 +415,7 @@ body: |
 
     %rcx = LEA64r %rip, 1, _, %jump-table.0, _
   ; CHECK: name: jumptable_psv
-  ; CHECK: %rax = MOVSX64rm32 %rcx, 4, killed %rax, 0, _ :: (load 4 from jump-table, align 8)
+  ; CHECK: %rax = MOVSX64rm32 %rcx, 4, killed %rax, 0, %noreg :: (load 4 from jump-table, align 8)
     %rax = MOVSX64rm32 %rcx, 4, killed %rax, 0, _ :: (load 4 from jump-table, align 8)
     %rax = ADD64rr killed %rax, killed %rcx, implicit-def dead %eflags
     JMP64r killed %rax
@@ -447,8 +447,8 @@ body: |
   bb.0.entry:
     %rax = MOV64rm %rip, 1, _, @a, _ :: (load 8 from got)
   ; CHECK-LABEL: name: tbaa_metadata
-  ; CHECK:      %eax = MOV32rm killed %rax, 1, _, 0, _, implicit-def %rax :: (load 4 from @a, !tbaa !2)
-  ; CHECK-NEXT: %eax = MOV32rm killed %rax, 1, _, 0, _ :: (load 4 from %ir.total_len2, !tbaa !6)
+  ; CHECK:      %eax = MOV32rm killed %rax, 1, %noreg, 0, %noreg, implicit-def %rax :: (load 4 from @a, !tbaa !2)
+  ; CHECK-NEXT: %eax = MOV32rm killed %rax, 1, %noreg, 0, %noreg :: (load 4 from %ir.total_len2, !tbaa !6)
     %eax = MOV32rm killed %rax, 1, _, 0, _, implicit-def %rax :: (load 4 from @a, !tbaa !2)
     %eax = MOV32rm killed %rax, 1, _, 0, _ :: (load 4 from %ir.total_len2, !tbaa !6)
     RETQ %eax
@@ -463,9 +463,9 @@ body: |
   bb.0.entry:
     liveins: %rdi, %rsi
   ; CHECK-LABEL: name: aa_scope
-  ; CHECK: %xmm0 = MOVSSrm %rsi, 1, _, 0, _ :: (load 4 from %ir.c, !alias.scope !9)
+  ; CHECK: %xmm0 = MOVSSrm %rsi, 1, %noreg, 0, %noreg :: (load 4 from %ir.c, !alias.scope !9)
     %xmm0 = MOVSSrm %rsi, 1, _, 0, _ :: (load 4 from %ir.c, !alias.scope !9)
-  ; CHECK-NEXT: MOVSSmr %rdi, 1, _, 20, _, killed %xmm0 :: (store 4 into %ir.arrayidx.i, !noalias !9)
+  ; CHECK-NEXT: MOVSSmr %rdi, 1, %noreg, 20, %noreg, killed %xmm0 :: (store 4 into %ir.arrayidx.i, !noalias !9)
     MOVSSmr %rdi, 1, _, 20, _, killed %xmm0 :: (store 4 into %ir.arrayidx.i, !noalias !9)
     %xmm0 = MOVSSrm killed %rsi, 1, _, 0, _ :: (load 4 from %ir.c)
     MOVSSmr killed %rdi, 1, _, 28, _, killed %xmm0 :: (store 4 into %ir.arrayidx)
@@ -480,7 +480,7 @@ body: |
   bb.0.entry:
     liveins: %rdi
   ; CHECK-LABEL: name: range_metadata
-  ; CHECK: %al = MOV8rm killed %rdi, 1, _, 0, _ :: (load 1 from %ir.x, !range !11)
+  ; CHECK: %al = MOV8rm killed %rdi, 1, %noreg, 0, %noreg :: (load 1 from %ir.x, !range !11)
     %al = MOV8rm killed %rdi, 1, _, 0, _ :: (load 1 from %ir.x, !range !11)
     RETQ %al
 ...
@@ -495,7 +495,7 @@ body: |
 
     %rax = MOV64rm %rip, 1, _, @values, _ :: (load 8 from got)
   ; CHECK-LABEL: gep_value
-  ; CHECK: MOV32mr killed %rax, 1, _, 0, _, %edi, implicit killed %rdi :: (store 4 into `i32* getelementptr inbounds ([50 x %st], [50 x %st]* @values, i64 0, i64 0, i32 0)`, align 16)
+  ; CHECK: MOV32mr killed %rax, 1, %noreg, 0, %noreg, %edi, implicit killed %rdi :: (store 4 into `i32* getelementptr inbounds ([50 x %st], [50 x %st]* @values, i64 0, i64 0, i32 0)`, align 16)
     MOV32mr killed %rax, 1, _, 0, _, %edi, implicit killed %rdi :: (store 4 into `i32* getelementptr inbounds ([50 x %st], [50 x %st]* @values, i64 0, i64 0, i32 0)`, align 16)
     RETQ
 ...
@@ -505,14 +505,14 @@ tracksRegLiveness: true
 body: |
   bb.0.entry:
   ; CHECK-LABEL: name: undef_value
-  ; CHECK: %rax = MOV64rm undef %rax, 1, _, 0, _ :: (load 8 from `i8** undef`)
+  ; CHECK: %rax = MOV64rm undef %rax, 1, %noreg, 0, %noreg :: (load 8 from `i8** undef`)
     %rax = MOV64rm undef %rax, 1, _, 0, _ :: (load 8 from `i8** undef`)
     RETQ %rax
 ...
 ---
 # Test memory operand without associated value.
 # CHECK-LABEL: name: dummy0
-# CHECK: %rax = MOV64rm undef %rax, 1, _, 0, _ :: (load 8)
+# CHECK: %rax = MOV64rm undef %rax, 1, %noreg, 0, %noreg :: (load 8)
 name: dummy0
 tracksRegLiveness: true
 body: |
@@ -523,7 +523,7 @@ body: |
 ---
 # Test parsing of stack references in machine memory operands.
 # CHECK-LABEL: name: dummy1
-# CHECK: %rax = MOV64rm %rsp, 1, _, 0, _ :: (load 8 from %stack.0)
+# CHECK: %rax = MOV64rm %rsp, 1, %noreg, 0, %noreg :: (load 8 from %stack.0)
 name: dummy1
 tracksRegLiveness: true
 stack:

test/CodeGen/MIR/X86/metadata-operands.mir

@@ -51,7 +51,7 @@ body: |
   bb.0.entry:
     liveins: %edi
     ; CHECK:      %0:gr32 = COPY %edi
-    ; CHECK-NEXT: DBG_VALUE _, 0, !11, !DIExpression()
+    ; CHECK-NEXT: DBG_VALUE %noreg, 0, !11, !DIExpression()
     %0 = COPY %edi
     DBG_VALUE _, 0, !12, !DIExpression()
     MOV32mr %stack.0.x.addr, 1, _, 0, _, %0

test/CodeGen/MIR/X86/null-register-operands.mir

@@ -15,7 +15,7 @@
 name:            deref
 body: |
   bb.0.entry:
-    ; CHECK:      %eax = MOV32rm %rdi, 1, _, 0, _
+    ; CHECK:      %eax = MOV32rm %rdi, 1, %noreg, 0, %noreg
     ; CHECK-NEXT: RETQ %eax
     %eax = MOV32rm %rdi, 1, _, 0, %noreg
     RETQ %eax

test/CodeGen/MIR/X86/roundtrip.mir

@@ -8,7 +8,7 @@
 # CHECK:   bb.0:
 # CHECK:     %0:gr32 = MOV32r0 implicit-def %eflags
 # CHECK:     dead %1:gr32 = COPY %0
-# CHECK:     MOV32mr undef %rcx, 1, _, 0, _, killed %0 :: (volatile store 4)
+# CHECK:     MOV32mr undef %rcx, 1, %noreg, 0, %noreg, killed %0 :: (volatile store 4)
 # CHECK:     RETQ undef %eax
 name: func0
 body: |

test/CodeGen/MIR/X86/stack-object-operands.mir

@@ -32,10 +32,10 @@ stack:
 body: |
   bb.0.entry:
     ; CHECK-LABEL: name: test
-    ; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, _, 0, _
-    ; CHECK: MOV32mr %stack.0.b, 1, _, 0, _, [[MOV32rm]]
-    ; CHECK: MOV32mi %stack.1, 1, _, 0, _, 2
-    ; CHECK: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm %stack.0.b, 1, _, 0, _
+    ; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, %noreg, 0, %noreg
+    ; CHECK: MOV32mr %stack.0.b, 1, %noreg, 0, %noreg, [[MOV32rm]]
+    ; CHECK: MOV32mi %stack.1, 1, %noreg, 0, %noreg, 2
+    ; CHECK: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm %stack.0.b, 1, %noreg, 0, %noreg
     ; CHECK: %eax = COPY [[MOV32rm1]]
     ; CHECK: RETL %eax
     %0 = MOV32rm %fixed-stack.0, 1, _, 0, _

test/CodeGen/Mips/const-mult.ll

@@ -90,4 +90,4 @@ define i128 @mul170141183460469231731687303715884105723_128(i128 signext %a) {
 entry:
   %mul = mul nsw i128 %a, 170141183460469231731687303715884105723
   ret i128 %mul
-}
+}

test/CodeGen/Mips/mips64signextendsesf.ll

@@ -211,4 +211,4 @@ declare float @fminf(float, float) #1
 
 
 attributes #0 = { nounwind "use-soft-float"="true" }
-attributes #1 = { nounwind readnone "use-soft-float"="true" }
+attributes #1 = { nounwind readnone "use-soft-float"="true" }

test/CodeGen/PowerPC/cxx_tlscc64.ll

@@ -40,4 +40,4 @@ define cxx_fast_tlscc i32* @_ZTW4sum2() #0 {
   ret i32* @sum1
 }
 
-attributes #0 = { nounwind "no-frame-pointer-elim"="true" }
+attributes #0 = { nounwind "no-frame-pointer-elim"="true" }

test/CodeGen/PowerPC/debuginfo-split-int.ll

@@ -27,9 +27,9 @@ target triple = "ppc32"
 ;
 ; High 32 bits in R3, low 32 bits in R4
 ; CHECK: %0:gprc = COPY %r3
-; CHECK: DBG_VALUE debug-use %0, debug-use _, [[DL]], !DIExpression(DW_OP_LLVM_fragment, 0, 32)
+; CHECK: DBG_VALUE debug-use %0, debug-use %noreg, [[DL]], !DIExpression(DW_OP_LLVM_fragment, 0, 32)
 ; CHECK: %1:gprc = COPY %r4
-; CHECK: DBG_VALUE debug-use %1, debug-use _, [[DL]], !DIExpression(DW_OP_LLVM_fragment, 32, 32)
+; CHECK: DBG_VALUE debug-use %1, debug-use %noreg, [[DL]], !DIExpression(DW_OP_LLVM_fragment, 32, 32)
 define void @bar() local_unnamed_addr #0 !dbg !6 {
   %1 = alloca i64, align 8
   %2 = tail call i64 @foo()

test/CodeGen/PowerPC/ppc32-align-long-double-sf.ll

@@ -18,4 +18,4 @@ declare i32 @printf(i8* nocapture readonly, ...) #0
 
 attributes #0 = { "use-soft-float"="true" }
 
-                        
+                        

test/CodeGen/SPARC/LeonItinerariesUT.ll

@@ -47,4 +47,4 @@ entry:
   %6 = fmul float %5, %3
   %7 = fdiv float %6, %4
   ret float %7
-}
+}

test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir

@@ -149,7 +149,7 @@ body:             |
     %11 = VGBM 0
     %43 = LHIMux 0
     %44 = LARL %const.0
-    %45 = VL64 %44, 0, _ :: (load 8 from constant-pool)
+    %45 = VL64 %44, 0, %noreg :: (load 8 from constant-pool)
   
   bb.1:
     ADJCALLSTACKDOWN 0, 0
@@ -160,19 +160,19 @@ body:             |
     KILL killed %f0d
   
   bb.2:
-    %17 = VLGVH %11, _, 0
+    %17 = VLGVH %11, %noreg, 0
     %19 = LHR %17.subreg_l32
     undef %20.subreg_l64 = LGHI 0
     %20 = DSGFR %20, %19
-    %22 = VLGVH %11, _, 3
+    %22 = VLGVH %11, %noreg, 3
     %24 = LHR %22.subreg_l32
     undef %25.subreg_l64 = LGHI 0
     %25 = DSGFR %25, %24
-    %31 = VLGVH %11, _, 1
+    %31 = VLGVH %11, %noreg, 1
     %33 = LHR %31.subreg_l32
     undef %34.subreg_l64 = LGHI 0
     %34 = DSGFR %34, %33
-    %37 = VLGVH %11, _, 2
+    %37 = VLGVH %11, %noreg, 2
     %39 = LHR %37.subreg_l32
     undef %40.subreg_l64 = LGHI 0
     %40 = DSGFR %40, %39
@@ -191,10 +191,10 @@ body:             |
   
   bb.4:
     %36 = VLVGP %25.subreg_l64, %25.subreg_l64
-    %36 = VLVGH %36, %20.subreg_l32, _, 0
-    %36 = VLVGH %36, %34.subreg_l32, _, 1
-    dead %36 = VLVGH %36, %40.subreg_l32, _, 2
-    %4 = LG undef %42, 0, _ :: (load 8 from `i64* undef`)
+    %36 = VLVGH %36, %20.subreg_l32, %noreg, 0
+    %36 = VLVGH %36, %34.subreg_l32, %noreg, 1
+    dead %36 = VLVGH %36, %40.subreg_l32, %noreg, 2
+    %4 = LG undef %42, 0, %noreg :: (load 8 from `i64* undef`)
     undef %57.subreg_h64 = LLILL 0
     undef %66.subreg_h64 = LLILL 0
     undef %79.subreg_h64 = LLILL 0
@@ -204,27 +204,27 @@ body:             |
   bb.5:
   
   bb.6:
-    %51 = VLGVH undef %7, _, 0
+    %51 = VLGVH undef %7, %noreg, 0
     %53 = LLHRMux %51.subreg_l32
-    %54 = VLGVH undef %1, _, 0
+    %54 = VLGVH undef %1, %noreg, 0
     %57.subreg_l32 = LLHRMux %54.subreg_l32
     %58 = COPY %57
     %58 = DLR %58, %53
-    %60 = VLGVH undef %7, _, 3
+    %60 = VLGVH undef %7, %noreg, 3
     %62 = LLHRMux %60.subreg_l32
-    %63 = VLGVH undef %1, _, 3
+    %63 = VLGVH undef %1, %noreg, 3
     %66.subreg_l32 = LLHRMux %63.subreg_l32
     %67 = COPY %66
     %67 = DLR %67, %62
-    %73 = VLGVH undef %7, _, 1
+    %73 = VLGVH undef %7, %noreg, 1
     %75 = LLHRMux %73.subreg_l32
-    %76 = VLGVH undef %1, _, 1
+    %76 = VLGVH undef %1, %noreg, 1
     %79.subreg_l32 = LLHRMux %76.subreg_l32
     %80 = COPY %79
     %80 = DLR %80, %75
-    %83 = VLGVH undef %7, _, 2
+    %83 = VLGVH undef %7, %noreg, 2
     %85 = LLHRMux %83.subreg_l32
-    %86 = VLGVH undef %1, _, 2
+    %86 = VLGVH undef %1, %noreg, 2
     %89.subreg_l32 = LLHRMux %86.subreg_l32
     %90 = COPY %89
     %90 = DLR %90, %85
@@ -248,12 +248,12 @@ body:             |
   
   bb.9:
     %82 = VLVGP %67.subreg_h64, %67.subreg_h64
-    %82 = VLVGH %82, %58.subreg_hl32, _, 0
-    %82 = VLVGH %82, %80.subreg_hl32, _, 1
-    dead %82 = VLVGH %82, %90.subreg_hl32, _, 2
+    %82 = VLVGH %82, %58.subreg_hl32, %noreg, 0
+    %82 = VLVGH %82, %80.subreg_hl32, %noreg, 1
+    dead %82 = VLVGH %82, %90.subreg_hl32, %noreg, 2
     %96 = AFIMux %96, 1879048192, implicit-def dead %cc
-    %96 = SRL %96, _, 31
-    dead %11 = VLVGF %11, %96, _, 1
+    %96 = SRL %96, %noreg, 31
+    dead %11 = VLVGF %11, %96, %noreg, 1
     %100 = LHIMux 0
   
   bb.10:

test/CodeGen/SystemZ/clear-liverange-spillreg.mir

@@ -223,14 +223,14 @@ body:             |
   
   bb.11:
     %4 = COPY %60
-    %6 = SLLG %120, _, 1
+    %6 = SLLG %120, %noreg, 1
     %7 = LA %6, 64, %41
     %6 = AGR %6, %42, implicit-def dead %cc
-    %45 = SRLK %120.subreg_l32, _, 31
+    %45 = SRLK %120.subreg_l32, %noreg, 31
     %45 = AR %45, %120.subreg_l32, implicit-def dead %cc
     %45 = NIFMux %45, 536870910, implicit-def dead %cc
     %47 = SRK %120.subreg_l32, %45, implicit-def dead %cc
-    %47 = SLL %47, _, 3
+    %47 = SLL %47, %noreg, 3
     %81 = LGFR %47
   
   bb.12:
@@ -284,43 +284,43 @@ body:             |
     MVHI %0, 332, 2 :: (store 4)
     %60 = COPY %126
     %60 = AR %60, %4, implicit-def dead %cc
-    %18 = LHMux %6, 0, _ :: (load 2)
+    %18 = LHMux %6, 0, %noreg :: (load 2)
     CHIMux %38, 0, implicit-def %cc
     BRC 14, 6, %bb.19, implicit killed %cc
     J %bb.18
   
   bb.18:
-    %62 = SLLG %81, _, 1
+    %62 = SLLG %81, %noreg, 1
     %64 = LA %62, 0, %63
-    %65 = LG undef %66, 0, _ :: (load 8)
-    %67 = LGF undef %68, 0, _ :: (load 4)
+    %65 = LG undef %66, 0, %noreg :: (load 8)
+    %67 = LGF undef %68, 0, %noreg :: (load 4)
     MVC undef %69, 0, 2, %64, 0 :: (store 2), (load 2)
     %70 = COPY %81
     %70 = OILL64 %70, 3, implicit-def dead %cc
-    %71 = LA %70, 2, _
-    %72 = SLLG %71, _, 1
+    %71 = LA %70, 2, %noreg
+    %72 = SLLG %71, %noreg, 1
     %73 = LHMux %72, 0, %63 :: (load 2)
     %74 = LA %70, 2, %67
-    %75 = SLLG %74, _, 1
-    %76 = LG %65, 0, _ :: (load 8)
+    %75 = SLLG %74, %noreg, 1
+    %76 = LG %65, 0, %noreg :: (load 8)
     STHMux %73, %76, 0, %75 :: (store 2)
-    %77 = LG undef %78, 0, _ :: (load 8)
+    %77 = LG undef %78, 0, %noreg :: (load 8)
     %79 = LHRL @rec_mbY8x8 :: (load 2)
-    STHMux %79, %77, 0, _ :: (store 2)
+    STHMux %79, %77, 0, %noreg :: (store 2)
     %80 = LHMux %72, 0, %63 :: (load 2)
     STHMux %80, %77, 0, %75 :: (store 2)
     %81 = OILL64 %81, 7, implicit-def dead %cc
-    %82 = SLLG %81, _, 1
+    %82 = SLLG %81, %noreg, 1
     %83 = LHMux %82, 0, %63 :: (load 2)
-    STHMux %83, %77, 0, _ :: (store 2)
+    STHMux %83, %77, 0, %noreg :: (store 2)
     %84 = LA %62, 64, %63
     MVC undef %85, 0, 2, %84, 0 :: (store 2), (load 2)
-    %86 = SLLG %70, _, 1
+    %86 = SLLG %70, %noreg, 1
     %87 = LHMux %86, 64, %63 :: (load 2)
-    %88 = SLLG %67, _, 3
+    %88 = SLLG %67, %noreg, 3
     %89 = LG %65, 16, %88 :: (load 8)
     %90 = LA %70, 0, %67
-    %91 = SLLG %90, _, 1
+    %91 = SLLG %90, %noreg, 1
     STHMux %87, %89, 0, %91 :: (store 2)
     %92 = LA %72, 64, %63
     MVC undef %93, 0, 2, %92, 0 :: (store 2), (load 2)
@@ -332,8 +332,8 @@ body:             |
   bb.19:
     successors: %bb.20(0x04000000), %bb.11(0x7c000000)
   
-    %98 = LGH %7, 0, _ :: (load 2)
-    %99 = LGH undef %100, 0, _ :: (load 2)
+    %98 = LGH %7, 0, %noreg :: (load 2)
+    %99 = LGH undef %100, 0, %noreg :: (load 2)
     ADJCALLSTACKDOWN 0, 0
     %101 = LGFR %120.subreg_l32
     %102 = LGFR %18
@@ -347,7 +347,7 @@ body:             |
     ADJCALLSTACKDOWN 0, 0
     CallBRASL @reset_coding_state, undef %r2d, csr_systemz, implicit-def dead %r14d, implicit-def dead %cc
     ADJCALLSTACKUP 0, 0
-    %120 = LA %120, 1, _
+    %120 = LA %120, 1, %noreg
     CGHI %120, 4, implicit-def %cc
     BRC 14, 6, %bb.11, implicit killed %cc
     J %bb.20
@@ -410,7 +410,7 @@ body:             |
   bb.30:
     successors: %bb.33(0x00000001), %bb.31(0x7fffffff)
   
-    VST64 %130, undef %117, 0, _ :: (store 8)
+    VST64 %130, undef %117, 0, %noreg :: (store 8)
     CHIMux undef %118, 2, implicit-def %cc
     BRC 14, 8, %bb.33, implicit killed %cc
     J %bb.31
@@ -470,7 +470,7 @@ body:             |
   bb.44:
   
   bb.45:
-    %0 = LG undef %22, 0, _ :: (load 8)
+    %0 = LG undef %22, 0, %noreg :: (load 8)
     %38 = LHIMux 0
     STRL %38, @bi_pred_me :: (store 4)
     %120 = LGHI 0

test/CodeGen/SystemZ/fp-cmp-07.mir

@@ -38,7 +38,7 @@ body:             |
   bb.1.store:
     liveins: %f0s, %r2d
 
-    STE %f0s, killed %r2d, 0, _ :: (store 4 into %ir.dest)
+    STE %f0s, killed %r2d, 0, %noreg :: (store 4 into %ir.dest)
     Return implicit %f0s
 
 ...

test/CodeGen/SystemZ/fp-conv-17.mir

@@ -129,74 +129,74 @@ body:             |
   
     %1 = COPY %r3d
     %0 = COPY %r2d
-    %2 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
-    %3 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
-    %4 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
-    %5 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
-    %6 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
-    %7 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
-    %8 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
-    %9 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
-    %10 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
-    %11 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
-    %12 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
-    %13 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
-    %14 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
-    %15 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
-    %16 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
-    %17 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
-    %18 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2)
-    STE %2, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
-    STE %3, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
-    STE %4, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
-    STE %5, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
-    STE %6, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
-    STE %7, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
-    STE %8, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
-    STE %9, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
-    STE %10, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
-    STE %11, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
-    STE %12, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
-    STE %13, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
-    STE %14, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
-    STE %15, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
-    STE %16, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
-    STE %17, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
-    STE %18, %1, 0, _ :: (volatile store 4 into %ir.ptr2)
+    %2 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
+    %3 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
+    %4 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
+    %5 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
+    %6 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
+    %7 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
+    %8 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
+    %9 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
+    %10 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
+    %11 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
+    %12 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
+    %13 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
+    %14 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
+    %15 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
+    %16 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
+    %17 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
+    %18 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
+    STE %2, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
+    STE %3, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
+    STE %4, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
+    STE %5, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
+    STE %6, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
+    STE %7, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
+    STE %8, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
+    STE %9, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
+    STE %10, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
+    STE %11, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
+    STE %12, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
+    STE %13, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
+    STE %14, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
+    STE %15, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
+    STE %16, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
+    STE %17, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
+    STE %18, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
     %19 = LDEBR %2
-    STD %19, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
+    STD %19, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
     %20 = LDEBR %3
-    STD %20, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
+    STD %20, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
     %21 = LDEBR %4
-    STD %21, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
+    STD %21, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
     %22 = LDEBR %5
-    STD %22, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
+    STD %22, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
     %23 = LDEBR %6
-    STD %23, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
+    STD %23, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
     %24 = LDEBR %7
-    STD %24, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
+    STD %24, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
     %25 = LDEBR %8
-    STD %25, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
+    STD %25, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
     %26 = LDEBR %9
-    STD %26, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
+    STD %26, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
     %27 = LDEBR %10
-    STD %27, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
+    STD %27, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
     %28 = LDEBR %11
-    STD %28, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
+    STD %28, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
     %29 = LDEBR %12
-    STD %29, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
+    STD %29, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
     %30 = LDEBR %13
-    STD %30, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
+    STD %30, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
     %31 = LDEBR %14
-    STD %31, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
+    STD %31, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
     %32 = LDEBR %15
-    STD %32, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
+    STD %32, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
     %33 = LDEBR %16
-    STD %33, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
+    STD %33, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
     %34 = LDEBR %17
-    STD %34, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
+    STD %34, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
     %35 = LDEBR %18
-    STD %35, %0, 0, _ :: (volatile store 8 into %ir.ptr1)
+    STD %35, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
     Return
 
 ...

test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir

@@ -29,6 +29,6 @@ body:             |
     %0.subreg_hl32 = COPY %0.subreg_l32
     %1 = COPY %0.subreg_l64
     %2 = LARL @g_167
-    STC %1.subreg_l32, %2, 8, _
+    STC %1.subreg_l32, %2, 8, %noreg
 
 ...

test/CodeGen/Thumb/machine-cse-physreg.mir

@@ -21,15 +21,15 @@ body:             |
   bb.0:
     liveins: %r0
     %0 = COPY %r0
-    %1, %cpsr = tLSLri %0, 2, 14, _
-    tCMPi8 %0, 5, 14, _, implicit-def %cpsr
+    %1, %cpsr = tLSLri %0, 2, 14, %noreg
+    tCMPi8 %0, 5, 14, %noreg, implicit-def %cpsr
     tBcc %bb.8, 8, %cpsr
 
   bb.1:
-    %2, %cpsr = tLSLri %0, 2, 14, _
+    %2, %cpsr = tLSLri %0, 2, 14, %noreg
 
   bb.8:
     liveins: %cpsr
     %3 = COPY %cpsr
-    tSTRi killed %3, %0, 0, 14, _
+    tSTRi killed %3, %0, 0, 14, %noreg
 ...

test/CodeGen/Thumb/tbb-reuse.mir

@@ -108,44 +108,44 @@ body:             |
     successors: %bb.2.default(0x19999998), %bb.1.entry(0x66666668)
     liveins: %r0, %r7, %lr
   
-    frame-setup tPUSH 14, _, killed %r7, killed %lr, implicit-def %sp, implicit %sp
+    frame-setup tPUSH 14, %noreg, killed %r7, killed %lr, implicit-def %sp, implicit %sp
     frame-setup CFI_INSTRUCTION def_cfa_offset 8
     frame-setup CFI_INSTRUCTION offset %lr, -4
     frame-setup CFI_INSTRUCTION offset %r7, -8
-    %r1, dead %cpsr = tSUBi3 %r0, 1, 14, _
-    tCMPi8 %r1, 3, 14, _, implicit-def %cpsr
+    %r1, dead %cpsr = tSUBi3 %r0, 1, 14, %noreg
+    tCMPi8 %r1, 3, 14, %noreg, implicit-def %cpsr
     tBcc %bb.2.default, 8, killed %cpsr
   
   bb.1.entry:
     successors: %bb.3.lab1(0x20000000), %bb.4.lab2(0x20000000), %bb.5.lab3(0x20000000), %bb.6.lab4(0x20000000)
     liveins: %r0, %r1
   
-    %r1, dead %cpsr = tLSLri killed %r1, 2, 14, _
-    %r2 = tLEApcrelJT %jump-table.0, 14, _
-    %r2 = tLDRr killed %r1, killed %r2, 14, _ :: (load 4 from jump-table)
-    %r1, dead %cpsr = tLSLri %r2, 2, 14, _
+    %r1, dead %cpsr = tLSLri killed %r1, 2, 14, %noreg
+    %r2 = tLEApcrelJT %jump-table.0, 14, %noreg
+    %r2 = tLDRr killed %r1, killed %r2, 14, %noreg :: (load 4 from jump-table)
+    %r1, dead %cpsr = tLSLri %r2, 2, 14, %noreg
     tBR_JTr killed %r2, %jump-table.0
   
   bb.2.default:
-    tBL 14, _, @exit0, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp
-    tPOP_RET 14, _, def %r7, def %pc, implicit-def %sp, implicit %sp
+    tBL 14, %noreg, @exit0, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp
+    tPOP_RET 14, %noreg, def %r7, def %pc, implicit-def %sp, implicit %sp
   
   bb.3.lab1:
     liveins: %r0,%r1
   
-    tBL 14, _, @exit1, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit-def %sp
-    tPOP_RET 14, _, def %r7, def %pc, implicit-def %sp, implicit %sp
+    tBL 14, %noreg, @exit1, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit-def %sp
+    tPOP_RET 14, %noreg, def %r7, def %pc, implicit-def %sp, implicit %sp
   
   bb.4.lab2:
-    tBL 14, _, @exit2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp
-    tPOP_RET 14, _, def %r7, def %pc, implicit-def %sp, implicit %sp
+    tBL 14, %noreg, @exit2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp
+    tPOP_RET 14, %noreg, def %r7, def %pc, implicit-def %sp, implicit %sp
   
   bb.5.lab3:
-    tBL 14, _, @exit3, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp
-    tPOP_RET 14, _, def %r7, def %pc, implicit-def %sp, implicit %sp
+    tBL 14, %noreg, @exit3, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp
+    tPOP_RET 14, %noreg, def %r7, def %pc, implicit-def %sp, implicit %sp
   
   bb.6.lab4:
-    tBL 14, _, @exit4, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp
-    tPOP_RET 14, _, def %r7, def %pc, implicit-def %sp, implicit %sp
+    tBL 14, %noreg, @exit4, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp
+    tPOP_RET 14, %noreg, def %r7, def %pc, implicit-def %sp, implicit %sp
 
 ...