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Assumption that "VectorizedValue" will always be an Instruction is not correct.
It can be a constant or a vector argument.

ex :

define i32 @hadd(<4 x i32> %a) #0 {
entry:
%vecext = extractelement <4 x i32> %a, i32 0
%vecext1 = extractelement <4 x i32> %a, i32 1
%add = add i32 %vecext, %vecext1
%vecext2 = extractelement <4 x i32> %a, i32 2
%add3 = add i32 %add, %vecext2
%vecext4 = extractelement <4 x i32> %a, i32 3
%add5 = add i32 %add3, %vecext4
ret i32 %add5
}



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225517 91177308-0d34-0410-b5e6-96231b3b80d8

Suyog Sarda il y a 10 ans
Parent
commit
df970d6297
1 fichiers modifiés avec 1 ajouts et 2 suppressions
  1. 1 2
      lib/Transforms/Vectorize/SLPVectorizer.cpp

+ 1 - 2
lib/Transforms/Vectorize/SLPVectorizer.cpp

@@ -3502,11 +3502,10 @@ private:
   /// \brief Emit a horizontal reduction of the vectorized value.
   Value *emitReduction(Value *VectorizedValue, IRBuilder<> &Builder) {
     assert(VectorizedValue && "Need to have a vectorized tree node");
-    Instruction *ValToReduce = dyn_cast<Instruction>(VectorizedValue);
     assert(isPowerOf2_32(ReduxWidth) &&
            "We only handle power-of-two reductions for now");
 
-    Value *TmpVec = ValToReduce;
+    Value *TmpVec = VectorizedValue;
     for (unsigned i = ReduxWidth / 2; i != 0; i >>= 1) {
       if (IsPairwiseReduction) {
         Value *LeftMask =