Patches to make the LLVM sources more -pedantic clean. Patch provided

by Anton Korobeynikov!  This is a step towards closing PR786.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28447 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/CodeGen/MachineInstr.h

@@ -42,7 +42,7 @@ private:
   // Bit fields of the flags variable used for different operand properties
   enum {
     DEFFLAG     = 0x01,       // this is a def of the operand
-    USEFLAG     = 0x02,       // this is a use of the operand
+    USEFLAG     = 0x02        // this is a use of the operand
   };
 
 public:

include/llvm/CodeGen/ScheduleDAG.h

@@ -41,7 +41,7 @@ namespace llvm {
     enum HazardType {
       NoHazard,      // This instruction can be emitted at this cycle.
       Hazard,        // This instruction can't be emitted at this cycle.
-      NoopHazard,    // This instruction can't be emitted, and needs noops.
+      NoopHazard     // This instruction can't be emitted, and needs noops.
     };
     
     /// getHazardType - Return the hazard type of emitting this node.  There are

lib/Analysis/DataStructure/DataStructure.cpp

@@ -43,7 +43,7 @@ namespace {
   DSAFieldLimit("dsa-field-limit", cl::Hidden,
                 cl::desc("Number of fields to track before collapsing a node"),
                 cl::init(256));
-};
+}
 
 #if 0
 #define TIME_REGION(VARNAME, DESC) \

lib/Analysis/IPA/Andersens.cpp

@@ -192,7 +192,7 @@ namespace {
     enum {
       UniversalSet = 0,
       NullPtr      = 1,
-      NullObject   = 2,
+      NullObject   = 2
     };
 
   public:

lib/CodeGen/LiveIntervalAnalysis.cpp

@@ -59,7 +59,7 @@ namespace {
   EnableJoining("join-liveintervals",
                 cl::desc("Join compatible live intervals"),
                 cl::init(true));
-};
+}
 
 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const
 {

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

@@ -65,7 +65,7 @@ class SelectionDAGLegalize {
   enum LegalizeAction {
     Legal,      // The target natively supports this operation.
     Promote,    // This operation should be executed in a larger type.
-    Expand,     // Try to expand this to other ops, otherwise use a libcall.
+    Expand      // Try to expand this to other ops, otherwise use a libcall.
   };
   
   /// ValueTypeActions - This is a bitvector that contains two bits for each

lib/CodeGen/TwoAddressInstructionPass.cpp

@@ -60,7 +60,7 @@ namespace {
 
   RegisterPass<TwoAddressInstructionPass>
   X("twoaddressinstruction", "Two-Address instruction pass");
-};
+}
 
 const PassInfo *llvm::TwoAddressInstructionPassID = X.getPassInfo();
 

lib/Support/Compressor.cpp

@@ -23,7 +23,7 @@ using namespace llvm;
 
 enum CompressionTypes {
   COMP_TYPE_NONE  = '0',
-  COMP_TYPE_BZIP2 = '2',
+  COMP_TYPE_BZIP2 = '2'
 };
 
 static int getdata(char*& buffer, size_t &size,

lib/Support/IsInf.cpp

@@ -42,4 +42,4 @@ namespace llvm {
 int IsInf (float f)  { return isinf (f); }
 int IsInf (double d) { return isinf (d); }
 
-}; // end namespace llvm;
+} // end namespace llvm;

lib/Support/IsNAN.cpp

@@ -31,4 +31,4 @@ namespace llvm {
 int IsNAN (float f)  { return isnan (f); }
 int IsNAN (double d) { return isnan (d); }
 
-}; // end namespace llvm;
+} // end namespace llvm;

lib/Target/ARM/ARMISelDAGToDAG.cpp

@@ -31,7 +31,7 @@ using namespace llvm;
 namespace ARMISD {
   enum {
     FIRST_NUMBER = ISD::BUILTIN_OP_END+ARM::INSTRUCTION_LIST_END,
-    RET_FLAG,
+    RET_FLAG
   };
 }
 

lib/Target/Alpha/AlphaISelLowering.h

@@ -42,7 +42,7 @@ namespace llvm {
       CALL,
 
       /// DIVCALL - used for special library calls for div and rem
-      DivCall,
+      DivCall
 
     };
   }

lib/Target/Alpha/AlphaRelocations.h

@@ -23,7 +23,7 @@ namespace llvm {
       reloc_gprellow,
       reloc_gprelhigh,
       reloc_gpdist,
-      reloc_bsr,
+      reloc_bsr
     };
   }
 }

lib/Target/PowerPC/PPCISelLowering.cpp

@@ -1748,7 +1748,7 @@ static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
     OP_VSPLTISW3,
     OP_VSLDOI4,
     OP_VSLDOI8,
-    OP_VSLDOI12,
+    OP_VSLDOI12
   };
   
   if (OpNum == OP_COPY) {

lib/Target/PowerPC/PPCInstrInfo.h

@@ -44,7 +44,7 @@ enum {
   /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
   /// an instruction is issued to.
   PPC970_Shift = 3,
-  PPC970_Mask = 0x07 << PPC970_Shift,
+  PPC970_Mask = 0x07 << PPC970_Shift
 };
 enum PPC970_Unit {
   /// These are the various PPC970 execution unit pipelines.  Each instruction
@@ -56,7 +56,7 @@ enum PPC970_Unit {
   PPC970_CRU    = 4 << PPC970_Shift,   // Control Register Unit
   PPC970_VALU   = 5 << PPC970_Shift,   // Vector ALU
   PPC970_VPERM  = 6 << PPC970_Shift,   // Vector Permute Unit
-  PPC970_BRU    = 7 << PPC970_Shift,   // Branch Unit
+  PPC970_BRU    = 7 << PPC970_Shift    // Branch Unit
 };
 }
   

lib/Target/PowerPC/PPCJITInfo.cpp

@@ -165,7 +165,7 @@ PPCJITInfo::getLazyResolverFunction(JITCompilerFn Fn) {
 void *PPCJITInfo::emitFunctionStub(void *Fn, MachineCodeEmitter &MCE) {
   // If this is just a call to an external function, emit a branch instead of a
   // call.  The code is the same except for one bit of the last instruction.
-  if (Fn != PPC32CompilationCallback) {
+  if (Fn != (void*)PPC32CompilationCallback) {
     MCE.startFunctionStub(4*4);
     void *Addr = (void*)(intptr_t)MCE.getCurrentPCValue();
     MCE.emitWordBE(0);

lib/Target/PowerPC/PPCRelocations.h

@@ -50,7 +50,7 @@ namespace llvm {
       // relocated to point to a POINTER to the indicated global.  The low-16
       // bits of the instruction are rewritten with the low 16-bits of the
       // address of the pointer.
-      reloc_absolute_ptr_low,
+      reloc_absolute_ptr_low
     };
   }
 }

lib/Target/Sparc/Sparc.h

@@ -75,7 +75,7 @@ namespace llvm {
       FCC_UGE = 12+16,  // Unordered or Greater or Equal
       FCC_LE  = 13+16,  // Less or Equal
       FCC_ULE = 14+16,  // Unordered or Less or Equal
-      FCC_O   = 15+16,  // Ordered
+      FCC_O   = 15+16   // Ordered
     };
   }
   

lib/Target/Sparc/SparcISelDAGToDAG.cpp

@@ -48,7 +48,7 @@ namespace SPISD {
     ITOF,        // Int to FP within a FP register.
 
     CALL,        // A call instruction.
-    RET_FLAG,    // Return with a flag operand.
+    RET_FLAG     // Return with a flag operand.
   };
 }
 

lib/Target/Sparc/SparcInstrInfo.h

@@ -29,7 +29,7 @@ namespace SPII {
     Store = (1<<2),
     DelaySlot = (1<<3)
   };
-};
+}
 
 class SparcInstrInfo : public TargetInstrInfo {
   const SparcRegisterInfo RI;

lib/Target/Sparc/SparcSubtarget.cpp

@@ -40,4 +40,4 @@ SparcSubtarget::SparcSubtarget(const Module &M, const std::string &FS) {
   // Unless explicitly enabled, disable the V9 instructions.
   if (!EnableV9)
     IsV9 = false;
-};
+}

lib/Target/TargetMachine.cpp

@@ -28,7 +28,7 @@ namespace llvm {
   bool UnsafeFPMath;
   bool FiniteOnlyFPMathOption;
   Reloc::Model RelocationModel;
-};
+}
 namespace {
   cl::opt<bool, true> PrintCode("print-machineinstrs",
     cl::desc("Print generated machine code"),
@@ -70,7 +70,7 @@ namespace {
       clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic",
                  "Relocatable external references, non-relocatable code"),
       clEnumValEnd));
-};
+}
 
 //---------------------------------------------------------------------------
 // TargetMachine Class

lib/Target/X86/X86ISelDAGToDAG.cpp

@@ -47,7 +47,7 @@ namespace {
   struct X86ISelAddressMode {
     enum {
       RegBase,
-      FrameIndexBase,
+      FrameIndexBase
     } BaseType;
 
     struct {            // This is really a union, discriminated by BaseType!

lib/Target/X86/X86ISelLowering.h

@@ -156,7 +156,7 @@ namespace llvm {
 
       /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
       /// corresponds to X86::PINSRW.
-      PINSRW,
+      PINSRW
     };
 
     // X86 specific condition code. These correspond to X86_*_COND in

lib/Target/X86/X86InstrBuilder.h

@@ -35,7 +35,7 @@ namespace llvm {
 struct X86AddressMode {
   enum {
     RegBase,
-    FrameIndexBase,
+    FrameIndexBase
   } BaseType;
 
   union {

lib/Target/X86/X86InstrInfo.h

@@ -162,7 +162,7 @@ namespace X86II {
     SpecialFP  = 7 << FPTypeShift,
 
     OpcodeShift   = 16,
-    OpcodeMask    = 0xFF << OpcodeShift,
+    OpcodeMask    = 0xFF << OpcodeShift
     // Bits 25 -> 31 are unused
   };
 }

lib/Target/X86/X86JITInfo.cpp

@@ -167,7 +167,7 @@ X86JITInfo::getLazyResolverFunction(JITCompilerFn F) {
 }
 
 void *X86JITInfo::emitFunctionStub(void *Fn, MachineCodeEmitter &MCE) {
-  if (Fn != X86CompilationCallback) {
+  if (Fn != (void*)X86CompilationCallback) {
     MCE.startFunctionStub(5);
     MCE.emitByte(0xE9);
     MCE.emitWordLE((intptr_t)Fn-MCE.getCurrentPCValue()-4);

lib/Target/X86/X86Relocations.h

@@ -25,7 +25,7 @@ namespace llvm {
 
       // reloc_absolute_word - Absolute relocation, just add the relocated value
       // to the value already in memory.
-      reloc_absolute_word = 1,
+      reloc_absolute_word = 1
     };
   }
 }

lib/Transforms/Instrumentation/RSProfiling.cpp

@@ -162,7 +162,7 @@ namespace {
 
   RegisterOpt<ProfilerRS> X("insert-rs-profiling-framework",
 			   "Insert random sampling instrumentation  framework");
-};
+}
 
 //Local utilities
 static void ReplacePhiPred(BasicBlock* btarget, 

lib/Transforms/Instrumentation/RSProfiling.h

@@ -26,4 +26,4 @@ namespace llvm {
     void IncrementCounterInBlock(BasicBlock *BB, unsigned CounterNum,
                                  GlobalValue *CounterArray);
   };
-};
+}

lib/VMCore/Constants.cpp

@@ -529,7 +529,7 @@ bool ConstantFP::isValueValidForType(const Type *Ty, double Val) {
   case Type::DoubleTyID:
     return true;          // This is the largest type...
   }
-};
+}
 
 //===----------------------------------------------------------------------===//
 //                      Factory Function Implementation

tools/analyze/GraphPrinters.cpp

@@ -74,4 +74,4 @@ namespace {
 
   RegisterAnalysis<CallGraphPrinter> P2("print-callgraph",
                                         "Print Call Graph to 'dot' file");
-};
+}

tools/bugpoint/ListReducer.h

@@ -27,7 +27,7 @@ struct ListReducer {
   enum TestResult {
     NoFailure,         // No failure of the predicate was detected
     KeepSuffix,        // The suffix alone satisfies the predicate
-    KeepPrefix,        // The prefix alone satisfies the predicate
+    KeepPrefix         // The prefix alone satisfies the predicate
   };
 
   virtual ~ListReducer() {}

tools/llvm-ar/llvm-ar.cpp

@@ -80,7 +80,7 @@ enum ArchiveOperation {
   QuickAppend,      ///< Quickly append to end of archive
   ReplaceOrInsert,  ///< Replace or Insert members
   DisplayTable,     ///< Display the table of contents
-  Extract,          ///< Extract files back to file system
+  Extract           ///< Extract files back to file system
 };
 
 // Modifiers to follow operation to vary behavior

tools/llvm-nm/llvm-nm.cpp

@@ -63,7 +63,7 @@ namespace {
   bool MultipleFiles = false;
 
   std::string ToolName;
-};
+}
 
 char TypeCharForSymbol (GlobalValue &GV) {
   if (GV.isExternal ())                                     return 'U';

tools/llvmc/CompilerDriver.h

@@ -65,7 +65,7 @@ namespace llvm {
         PREPROCESSES_FLAG    = 0x0002, ///< Does this action preprocess?
         TRANSLATES_FLAG      = 0x0004, ///< Does this action translate?
         OUTPUT_IS_ASM_FLAG   = 0x0008, ///< Action produces .ll files?
-        FLAGS_MASK           = 0x000F, ///< Union of all flags
+        FLAGS_MASK           = 0x000F  ///< Union of all flags
       };
 
       /// This type is the input list to the CompilerDriver. It provides
@@ -131,7 +131,7 @@ namespace llvm {
         EMIT_RAW_FLAG        = 0x0080, ///< Emit raw, unoptimized bytecode
         KEEP_TEMPS_FLAG      = 0x0100, ///< Don't delete temporary files
         STRIP_OUTPUT_FLAG    = 0x0200, ///< Strip symbols from linked output
-        DRIVER_FLAGS_MASK    = 0x03FF, ///< Union of the above flags
+        DRIVER_FLAGS_MASK    = 0x03FF  ///< Union of the above flags
       };
 
     /// @}

tools/llvmc/ConfigLexer.h

@@ -102,7 +102,7 @@ enum ConfigLexerTokens {
   TRUETOK,           ///< A boolean true value (true/yes/on)
   VERBOSE_SUBST,     ///< The substitution item %verbose%
   VERSION_TOK,       ///< The name "version" (and variants)
-  WOPTS_SUBST,       ///< The %WOpts% substitution
+  WOPTS_SUBST        ///< The %WOpts% substitution
 };
 
 extern ConfigLexerTokens Configlex();

tools/llvmc/ConfigLexer.l

@@ -64,7 +64,7 @@ handleSubstitution(llvm::ConfigLexerTokens token) {
   }
   YY_FATAL_ERROR("Substitition tokens not allowed in names" ); 
   return ERRORTOK;
-};
+}
 
 inline llvm::ConfigLexerTokens handleValueContext(llvm::ConfigLexerTokens token) {
   ConfigLexerState.StringVal = yytext;

tools/llvmc/ConfigLexer.l.cvs

@@ -64,7 +64,7 @@ handleSubstitution(llvm::ConfigLexerTokens token) {
   }
   YY_FATAL_ERROR("Substitition tokens not allowed in names" ); 
   return ERRORTOK;
-};
+}
 
 inline llvm::ConfigLexerTokens handleValueContext(llvm::ConfigLexerTokens token) {
   ConfigLexerState.StringVal = yytext;

tools/opt/GraphPrinters.cpp

@@ -74,4 +74,4 @@ namespace {
 
   RegisterAnalysis<CallGraphPrinter> P2("print-callgraph",
                                         "Print Call Graph to 'dot' file");
-};
+}

utils/PerfectShuffle/PerfectShuffle.cpp

@@ -460,7 +460,7 @@ enum {
   OP_VSPLTISW3,
   OP_VSLDOI4,
   OP_VSLDOI8,
-  OP_VSLDOI12,
+  OP_VSLDOI12
 };
 
 struct vmrghw : public Operator {

utils/TableGen/RegisterInfoEmitter.cpp

@@ -37,7 +37,7 @@ void RegisterInfoEmitter::runEnums(std::ostream &OS) {
   OS << "  enum {\n    NoRegister,\n";
 
   for (unsigned i = 0, e = Registers.size(); i != e; ++i)
-    OS << "    " << Registers[i].getName() << ", \t// " << i+1 << "\n";
+    OS << "    " << Registers[i].getName() << (i != (e-1) ? ", \t// " : "  \t// ") << i+1 << "\n";
 
   OS << "  };\n";
   if (!Namespace.empty())