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@@ -9,6 +9,34 @@
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//
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// An implementation of the Swing Modulo Scheduling (SMS) software pipeliner.
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//
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+// Software pipelining (SWP) is an instruction scheduling technique for loops
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+// that overlap loop iterations and exploits ILP via a compiler transformation.
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+//
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+// Swing Modulo Scheduling is an implementation of software pipelining
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+// that generates schedules that are near optimal in terms of initiation
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+// interval, register requirements, and stage count. See the papers:
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+//
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+// "Swing Modulo Scheduling: A Lifetime-Sensitive Approach", by J. Llosa,
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+// A. Gonzalez, E. Ayguade, and M. Valero. In PACT '96 Proceedings of the 1996
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+// Conference on Parallel Architectures and Compilation Techiniques.
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+//
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+// "Lifetime-Sensitive Modulo Scheduling in a Production Environment", by J.
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+// Llosa, E. Ayguade, A. Gonzalez, M. Valero, and J. Eckhardt. In IEEE
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+// Transactions on Computers, Vol. 50, No. 3, 2001.
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+//
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+// "An Implementation of Swing Modulo Scheduling With Extensions for
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+// Superblocks", by T. Lattner, Master's Thesis, University of Illinois at
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+// Urbana-Chambpain, 2005.
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+//
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+//
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+// The SMS algorithm consists of three main steps after computing the minimal
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+// initiation interval (MII).
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+// 1) Analyze the dependence graph and compute information about each
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+// instruction in the graph.
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+// 2) Order the nodes (instructions) by priority based upon the heuristics
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+// described in the algorithm.
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+// 3) Attempt to schedule the nodes in the specified order using the MII.
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+//
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// This SMS implementation is a target-independent back-end pass. When enabled,
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// the pass runs just prior to the register allocation pass, while the machine
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// IR is in SSA form. If software pipelining is successful, then the original
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@@ -55,11 +83,13 @@
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineOperand.h"
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-#include "llvm/CodeGen/MachinePipeliner.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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+#include "llvm/CodeGen/RegisterClassInfo.h"
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#include "llvm/CodeGen/RegisterPressure.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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+#include "llvm/CodeGen/ScheduleDAGInstrs.h"
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#include "llvm/CodeGen/ScheduleDAGMutation.h"
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+#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetOpcodes.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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@@ -142,14 +172,575 @@ static cl::opt<bool> SwpIgnoreRecMII("pipeliner-ignore-recmii",
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cl::ReallyHidden, cl::init(false),
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cl::ZeroOrMore, cl::desc("Ignore RecMII"));
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-namespace llvm {
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-
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// A command line option to enable the CopyToPhi DAG mutation.
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-cl::opt<bool> SwpEnableCopyToPhi("pipeliner-enable-copytophi", cl::ReallyHidden,
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- cl::init(true), cl::ZeroOrMore,
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- cl::desc("Enable CopyToPhi DAG Mutation"));
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+static cl::opt<bool>
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+ SwpEnableCopyToPhi("pipeliner-enable-copytophi", cl::ReallyHidden,
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+ cl::init(true), cl::ZeroOrMore,
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+ cl::desc("Enable CopyToPhi DAG Mutation"));
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+
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+namespace {
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+
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+class NodeSet;
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+class SMSchedule;
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+
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+/// The main class in the implementation of the target independent
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+/// software pipeliner pass.
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+class MachinePipeliner : public MachineFunctionPass {
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+public:
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+ MachineFunction *MF = nullptr;
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+ const MachineLoopInfo *MLI = nullptr;
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+ const MachineDominatorTree *MDT = nullptr;
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+ const InstrItineraryData *InstrItins;
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+ const TargetInstrInfo *TII = nullptr;
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+ RegisterClassInfo RegClassInfo;
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+
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+#ifndef NDEBUG
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+ static int NumTries;
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+#endif
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-} // end namespace llvm
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+ /// Cache the target analysis information about the loop.
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+ struct LoopInfo {
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+ MachineBasicBlock *TBB = nullptr;
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+ MachineBasicBlock *FBB = nullptr;
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+ SmallVector<MachineOperand, 4> BrCond;
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+ MachineInstr *LoopInductionVar = nullptr;
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+ MachineInstr *LoopCompare = nullptr;
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+ };
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+ LoopInfo LI;
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+
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+ static char ID;
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+
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+ MachinePipeliner() : MachineFunctionPass(ID) {
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+ initializeMachinePipelinerPass(*PassRegistry::getPassRegistry());
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+ }
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+
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+ bool runOnMachineFunction(MachineFunction &MF) override;
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+
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+ void getAnalysisUsage(AnalysisUsage &AU) const override {
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+ AU.addRequired<AAResultsWrapperPass>();
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+ AU.addPreserved<AAResultsWrapperPass>();
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+ AU.addRequired<MachineLoopInfo>();
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+ AU.addRequired<MachineDominatorTree>();
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+ AU.addRequired<LiveIntervals>();
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+ MachineFunctionPass::getAnalysisUsage(AU);
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+ }
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+
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+private:
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+ void preprocessPhiNodes(MachineBasicBlock &B);
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+ bool canPipelineLoop(MachineLoop &L);
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+ bool scheduleLoop(MachineLoop &L);
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+ bool swingModuloScheduler(MachineLoop &L);
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+};
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+
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+/// This class builds the dependence graph for the instructions in a loop,
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+/// and attempts to schedule the instructions using the SMS algorithm.
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+class SwingSchedulerDAG : public ScheduleDAGInstrs {
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+ MachinePipeliner &Pass;
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+ /// The minimum initiation interval between iterations for this schedule.
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+ unsigned MII = 0;
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+ /// Set to true if a valid pipelined schedule is found for the loop.
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+ bool Scheduled = false;
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+ MachineLoop &Loop;
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+ LiveIntervals &LIS;
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+ const RegisterClassInfo &RegClassInfo;
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+
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+ /// A toplogical ordering of the SUnits, which is needed for changing
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+ /// dependences and iterating over the SUnits.
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+ ScheduleDAGTopologicalSort Topo;
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+
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+ struct NodeInfo {
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+ int ASAP = 0;
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+ int ALAP = 0;
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+ int ZeroLatencyDepth = 0;
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+ int ZeroLatencyHeight = 0;
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+
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+ NodeInfo() = default;
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+ };
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+ /// Computed properties for each node in the graph.
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+ std::vector<NodeInfo> ScheduleInfo;
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+
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+ enum OrderKind { BottomUp = 0, TopDown = 1 };
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+ /// Computed node ordering for scheduling.
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+ SetVector<SUnit *> NodeOrder;
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+
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+ using NodeSetType = SmallVector<NodeSet, 8>;
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+ using ValueMapTy = DenseMap<unsigned, unsigned>;
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+ using MBBVectorTy = SmallVectorImpl<MachineBasicBlock *>;
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+ using InstrMapTy = DenseMap<MachineInstr *, MachineInstr *>;
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+
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+ /// Instructions to change when emitting the final schedule.
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+ DenseMap<SUnit *, std::pair<unsigned, int64_t>> InstrChanges;
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+
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+ /// We may create a new instruction, so remember it because it
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+ /// must be deleted when the pass is finished.
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+ SmallPtrSet<MachineInstr *, 4> NewMIs;
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+
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+ /// Ordered list of DAG postprocessing steps.
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+ std::vector<std::unique_ptr<ScheduleDAGMutation>> Mutations;
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+
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+ /// Helper class to implement Johnson's circuit finding algorithm.
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+ class Circuits {
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+ std::vector<SUnit> &SUnits;
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+ SetVector<SUnit *> Stack;
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+ BitVector Blocked;
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+ SmallVector<SmallPtrSet<SUnit *, 4>, 10> B;
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+ SmallVector<SmallVector<int, 4>, 16> AdjK;
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+ // Node to Index from ScheduleDAGTopologicalSort
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+ std::vector<int> *Node2Idx;
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+ unsigned NumPaths;
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+ static unsigned MaxPaths;
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+
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+ public:
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+ Circuits(std::vector<SUnit> &SUs, ScheduleDAGTopologicalSort &Topo)
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+ : SUnits(SUs), Blocked(SUs.size()), B(SUs.size()), AdjK(SUs.size()) {
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+ Node2Idx = new std::vector<int>(SUs.size());
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+ unsigned Idx = 0;
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+ for (const auto &NodeNum : Topo)
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+ Node2Idx->at(NodeNum) = Idx++;
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+ }
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+
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+ ~Circuits() { delete Node2Idx; }
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+
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+ /// Reset the data structures used in the circuit algorithm.
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+ void reset() {
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+ Stack.clear();
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+ Blocked.reset();
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+ B.assign(SUnits.size(), SmallPtrSet<SUnit *, 4>());
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+ NumPaths = 0;
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+ }
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+
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+ void createAdjacencyStructure(SwingSchedulerDAG *DAG);
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+ bool circuit(int V, int S, NodeSetType &NodeSets, bool HasBackedge = false);
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+ void unblock(int U);
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+ };
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+
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+ struct CopyToPhiMutation : public ScheduleDAGMutation {
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+ void apply(ScheduleDAGInstrs *DAG) override;
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+ };
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+
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+public:
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+ SwingSchedulerDAG(MachinePipeliner &P, MachineLoop &L, LiveIntervals &lis,
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+ const RegisterClassInfo &rci)
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+ : ScheduleDAGInstrs(*P.MF, P.MLI, false), Pass(P), Loop(L), LIS(lis),
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+ RegClassInfo(rci), Topo(SUnits, &ExitSU) {
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+ P.MF->getSubtarget().getSMSMutations(Mutations);
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+ if (SwpEnableCopyToPhi)
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+ Mutations.push_back(llvm::make_unique<CopyToPhiMutation>());
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+ }
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+
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+ void schedule() override;
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+ void finishBlock() override;
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+
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+ /// Return true if the loop kernel has been scheduled.
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+ bool hasNewSchedule() { return Scheduled; }
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+
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+ /// Return the earliest time an instruction may be scheduled.
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+ int getASAP(SUnit *Node) { return ScheduleInfo[Node->NodeNum].ASAP; }
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+
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+ /// Return the latest time an instruction my be scheduled.
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+ int getALAP(SUnit *Node) { return ScheduleInfo[Node->NodeNum].ALAP; }
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+
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+ /// The mobility function, which the number of slots in which
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+ /// an instruction may be scheduled.
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+ int getMOV(SUnit *Node) { return getALAP(Node) - getASAP(Node); }
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+
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+ /// The depth, in the dependence graph, for a node.
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+ unsigned getDepth(SUnit *Node) { return Node->getDepth(); }
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+
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+ /// The maximum unweighted length of a path from an arbitrary node to the
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+ /// given node in which each edge has latency 0
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+ int getZeroLatencyDepth(SUnit *Node) {
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+ return ScheduleInfo[Node->NodeNum].ZeroLatencyDepth;
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+ }
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+
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+ /// The height, in the dependence graph, for a node.
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+ unsigned getHeight(SUnit *Node) { return Node->getHeight(); }
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+
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+ /// The maximum unweighted length of a path from the given node to an
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+ /// arbitrary node in which each edge has latency 0
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+ int getZeroLatencyHeight(SUnit *Node) {
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+ return ScheduleInfo[Node->NodeNum].ZeroLatencyHeight;
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+ }
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+
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+ /// Return true if the dependence is a back-edge in the data dependence graph.
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+ /// Since the DAG doesn't contain cycles, we represent a cycle in the graph
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+ /// using an anti dependence from a Phi to an instruction.
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+ bool isBackedge(SUnit *Source, const SDep &Dep) {
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+ if (Dep.getKind() != SDep::Anti)
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+ return false;
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+ return Source->getInstr()->isPHI() || Dep.getSUnit()->getInstr()->isPHI();
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+ }
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+
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+ bool isLoopCarriedDep(SUnit *Source, const SDep &Dep, bool isSucc = true);
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+
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+ /// The distance function, which indicates that operation V of iteration I
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+ /// depends on operations U of iteration I-distance.
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+ unsigned getDistance(SUnit *U, SUnit *V, const SDep &Dep) {
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+ // Instructions that feed a Phi have a distance of 1. Computing larger
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+ // values for arrays requires data dependence information.
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+ if (V->getInstr()->isPHI() && Dep.getKind() == SDep::Anti)
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+ return 1;
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+ return 0;
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+ }
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+
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+ /// Set the Minimum Initiation Interval for this schedule attempt.
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+ void setMII(unsigned mii) { MII = mii; }
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+
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+ void applyInstrChange(MachineInstr *MI, SMSchedule &Schedule);
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+
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+ void fixupRegisterOverlaps(std::deque<SUnit *> &Instrs);
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+
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+ /// Return the new base register that was stored away for the changed
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+ /// instruction.
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+ unsigned getInstrBaseReg(SUnit *SU) {
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+ DenseMap<SUnit *, std::pair<unsigned, int64_t>>::iterator It =
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+ InstrChanges.find(SU);
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+ if (It != InstrChanges.end())
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+ return It->second.first;
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+ return 0;
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+ }
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+
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+ void addMutation(std::unique_ptr<ScheduleDAGMutation> Mutation) {
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+ Mutations.push_back(std::move(Mutation));
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+ }
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+
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+ static bool classof(const ScheduleDAGInstrs *DAG) { return true; }
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+
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+private:
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+ void addLoopCarriedDependences(AliasAnalysis *AA);
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+ void updatePhiDependences();
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+ void changeDependences();
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+ unsigned calculateResMII();
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+ unsigned calculateRecMII(NodeSetType &RecNodeSets);
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+ void findCircuits(NodeSetType &NodeSets);
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+ void fuseRecs(NodeSetType &NodeSets);
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+ void removeDuplicateNodes(NodeSetType &NodeSets);
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+ void computeNodeFunctions(NodeSetType &NodeSets);
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+ void registerPressureFilter(NodeSetType &NodeSets);
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+ void colocateNodeSets(NodeSetType &NodeSets);
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+ void checkNodeSets(NodeSetType &NodeSets);
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+ void groupRemainingNodes(NodeSetType &NodeSets);
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+ void addConnectedNodes(SUnit *SU, NodeSet &NewSet,
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+ SetVector<SUnit *> &NodesAdded);
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+ void computeNodeOrder(NodeSetType &NodeSets);
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+ void checkValidNodeOrder(const NodeSetType &Circuits) const;
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+ bool schedulePipeline(SMSchedule &Schedule);
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+ void generatePipelinedLoop(SMSchedule &Schedule);
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+ void generateProlog(SMSchedule &Schedule, unsigned LastStage,
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+ MachineBasicBlock *KernelBB, ValueMapTy *VRMap,
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+ MBBVectorTy &PrologBBs);
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+ void generateEpilog(SMSchedule &Schedule, unsigned LastStage,
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+ MachineBasicBlock *KernelBB, ValueMapTy *VRMap,
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+ MBBVectorTy &EpilogBBs, MBBVectorTy &PrologBBs);
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+ void generateExistingPhis(MachineBasicBlock *NewBB, MachineBasicBlock *BB1,
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+ MachineBasicBlock *BB2, MachineBasicBlock *KernelBB,
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+ SMSchedule &Schedule, ValueMapTy *VRMap,
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+ InstrMapTy &InstrMap, unsigned LastStageNum,
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+ unsigned CurStageNum, bool IsLast);
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+ void generatePhis(MachineBasicBlock *NewBB, MachineBasicBlock *BB1,
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+ MachineBasicBlock *BB2, MachineBasicBlock *KernelBB,
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+ SMSchedule &Schedule, ValueMapTy *VRMap,
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+ InstrMapTy &InstrMap, unsigned LastStageNum,
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+ unsigned CurStageNum, bool IsLast);
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+ void removeDeadInstructions(MachineBasicBlock *KernelBB,
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+ MBBVectorTy &EpilogBBs);
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+ void splitLifetimes(MachineBasicBlock *KernelBB, MBBVectorTy &EpilogBBs,
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+ SMSchedule &Schedule);
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+ void addBranches(MBBVectorTy &PrologBBs, MachineBasicBlock *KernelBB,
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+ MBBVectorTy &EpilogBBs, SMSchedule &Schedule,
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+ ValueMapTy *VRMap);
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+ bool computeDelta(MachineInstr &MI, unsigned &Delta);
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+ void updateMemOperands(MachineInstr &NewMI, MachineInstr &OldMI,
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+ unsigned Num);
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+ MachineInstr *cloneInstr(MachineInstr *OldMI, unsigned CurStageNum,
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+ unsigned InstStageNum);
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+ MachineInstr *cloneAndChangeInstr(MachineInstr *OldMI, unsigned CurStageNum,
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+ unsigned InstStageNum,
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+ SMSchedule &Schedule);
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+ void updateInstruction(MachineInstr *NewMI, bool LastDef,
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+ unsigned CurStageNum, unsigned InstrStageNum,
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+ SMSchedule &Schedule, ValueMapTy *VRMap);
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+ MachineInstr *findDefInLoop(unsigned Reg);
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+ unsigned getPrevMapVal(unsigned StageNum, unsigned PhiStage, unsigned LoopVal,
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+ unsigned LoopStage, ValueMapTy *VRMap,
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+ MachineBasicBlock *BB);
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+ void rewritePhiValues(MachineBasicBlock *NewBB, unsigned StageNum,
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+ SMSchedule &Schedule, ValueMapTy *VRMap,
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+ InstrMapTy &InstrMap);
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+ void rewriteScheduledInstr(MachineBasicBlock *BB, SMSchedule &Schedule,
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+ InstrMapTy &InstrMap, unsigned CurStageNum,
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+ unsigned PhiNum, MachineInstr *Phi,
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+ unsigned OldReg, unsigned NewReg,
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+ unsigned PrevReg = 0);
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+ bool canUseLastOffsetValue(MachineInstr *MI, unsigned &BasePos,
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+ unsigned &OffsetPos, unsigned &NewBase,
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+ int64_t &NewOffset);
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+ void postprocessDAG();
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+};
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+
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+/// A NodeSet contains a set of SUnit DAG nodes with additional information
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+/// that assigns a priority to the set.
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+class NodeSet {
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+ SetVector<SUnit *> Nodes;
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+ bool HasRecurrence = false;
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+ unsigned RecMII = 0;
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+ int MaxMOV = 0;
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+ unsigned MaxDepth = 0;
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+ unsigned Colocate = 0;
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|
|
+ SUnit *ExceedPressure = nullptr;
|
|
|
+ unsigned Latency = 0;
|
|
|
+
|
|
|
+public:
|
|
|
+ using iterator = SetVector<SUnit *>::const_iterator;
|
|
|
+
|
|
|
+ NodeSet() = default;
|
|
|
+ NodeSet(iterator S, iterator E) : Nodes(S, E), HasRecurrence(true) {
|
|
|
+ Latency = 0;
|
|
|
+ for (unsigned i = 0, e = Nodes.size(); i < e; ++i)
|
|
|
+ for (const SDep &Succ : Nodes[i]->Succs)
|
|
|
+ if (Nodes.count(Succ.getSUnit()))
|
|
|
+ Latency += Succ.getLatency();
|
|
|
+ }
|
|
|
+
|
|
|
+ bool insert(SUnit *SU) { return Nodes.insert(SU); }
|
|
|
+
|
|
|
+ void insert(iterator S, iterator E) { Nodes.insert(S, E); }
|
|
|
+
|
|
|
+ template <typename UnaryPredicate> bool remove_if(UnaryPredicate P) {
|
|
|
+ return Nodes.remove_if(P);
|
|
|
+ }
|
|
|
+
|
|
|
+ unsigned count(SUnit *SU) const { return Nodes.count(SU); }
|
|
|
+
|
|
|
+ bool hasRecurrence() { return HasRecurrence; };
|
|
|
+
|
|
|
+ unsigned size() const { return Nodes.size(); }
|
|
|
+
|
|
|
+ bool empty() const { return Nodes.empty(); }
|
|
|
+
|
|
|
+ SUnit *getNode(unsigned i) const { return Nodes[i]; };
|
|
|
+
|
|
|
+ void setRecMII(unsigned mii) { RecMII = mii; };
|
|
|
+
|
|
|
+ void setColocate(unsigned c) { Colocate = c; };
|
|
|
+
|
|
|
+ void setExceedPressure(SUnit *SU) { ExceedPressure = SU; }
|
|
|
+
|
|
|
+ bool isExceedSU(SUnit *SU) { return ExceedPressure == SU; }
|
|
|
+
|
|
|
+ int compareRecMII(NodeSet &RHS) { return RecMII - RHS.RecMII; }
|
|
|
+
|
|
|
+ int getRecMII() { return RecMII; }
|
|
|
+
|
|
|
+ /// Summarize node functions for the entire node set.
|
|
|
+ void computeNodeSetInfo(SwingSchedulerDAG *SSD) {
|
|
|
+ for (SUnit *SU : *this) {
|
|
|
+ MaxMOV = std::max(MaxMOV, SSD->getMOV(SU));
|
|
|
+ MaxDepth = std::max(MaxDepth, SSD->getDepth(SU));
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ unsigned getLatency() { return Latency; }
|
|
|
+
|
|
|
+ unsigned getMaxDepth() { return MaxDepth; }
|
|
|
+
|
|
|
+ void clear() {
|
|
|
+ Nodes.clear();
|
|
|
+ RecMII = 0;
|
|
|
+ HasRecurrence = false;
|
|
|
+ MaxMOV = 0;
|
|
|
+ MaxDepth = 0;
|
|
|
+ Colocate = 0;
|
|
|
+ ExceedPressure = nullptr;
|
|
|
+ }
|
|
|
+
|
|
|
+ operator SetVector<SUnit *> &() { return Nodes; }
|
|
|
+
|
|
|
+ /// Sort the node sets by importance. First, rank them by recurrence MII,
|
|
|
+ /// then by mobility (least mobile done first), and finally by depth.
|
|
|
+ /// Each node set may contain a colocate value which is used as the first
|
|
|
+ /// tie breaker, if it's set.
|
|
|
+ bool operator>(const NodeSet &RHS) const {
|
|
|
+ if (RecMII == RHS.RecMII) {
|
|
|
+ if (Colocate != 0 && RHS.Colocate != 0 && Colocate != RHS.Colocate)
|
|
|
+ return Colocate < RHS.Colocate;
|
|
|
+ if (MaxMOV == RHS.MaxMOV)
|
|
|
+ return MaxDepth > RHS.MaxDepth;
|
|
|
+ return MaxMOV < RHS.MaxMOV;
|
|
|
+ }
|
|
|
+ return RecMII > RHS.RecMII;
|
|
|
+ }
|
|
|
+
|
|
|
+ bool operator==(const NodeSet &RHS) const {
|
|
|
+ return RecMII == RHS.RecMII && MaxMOV == RHS.MaxMOV &&
|
|
|
+ MaxDepth == RHS.MaxDepth;
|
|
|
+ }
|
|
|
+
|
|
|
+ bool operator!=(const NodeSet &RHS) const { return !operator==(RHS); }
|
|
|
+
|
|
|
+ iterator begin() { return Nodes.begin(); }
|
|
|
+ iterator end() { return Nodes.end(); }
|
|
|
+
|
|
|
+ void print(raw_ostream &os) const {
|
|
|
+ os << "Num nodes " << size() << " rec " << RecMII << " mov " << MaxMOV
|
|
|
+ << " depth " << MaxDepth << " col " << Colocate << "\n";
|
|
|
+ for (const auto &I : Nodes)
|
|
|
+ os << " SU(" << I->NodeNum << ") " << *(I->getInstr());
|
|
|
+ os << "\n";
|
|
|
+ }
|
|
|
+
|
|
|
+#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
|
|
|
+ LLVM_DUMP_METHOD void dump() const { print(dbgs()); }
|
|
|
+#endif
|
|
|
+};
|
|
|
+
|
|
|
+/// This class represents the scheduled code. The main data structure is a
|
|
|
+/// map from scheduled cycle to instructions. During scheduling, the
|
|
|
+/// data structure explicitly represents all stages/iterations. When
|
|
|
+/// the algorithm finshes, the schedule is collapsed into a single stage,
|
|
|
+/// which represents instructions from different loop iterations.
|
|
|
+///
|
|
|
+/// The SMS algorithm allows negative values for cycles, so the first cycle
|
|
|
+/// in the schedule is the smallest cycle value.
|
|
|
+class SMSchedule {
|
|
|
+private:
|
|
|
+ /// Map from execution cycle to instructions.
|
|
|
+ DenseMap<int, std::deque<SUnit *>> ScheduledInstrs;
|
|
|
+
|
|
|
+ /// Map from instruction to execution cycle.
|
|
|
+ std::map<SUnit *, int> InstrToCycle;
|
|
|
+
|
|
|
+ /// Map for each register and the max difference between its uses and def.
|
|
|
+ /// The first element in the pair is the max difference in stages. The
|
|
|
+ /// second is true if the register defines a Phi value and loop value is
|
|
|
+ /// scheduled before the Phi.
|
|
|
+ std::map<unsigned, std::pair<unsigned, bool>> RegToStageDiff;
|
|
|
+
|
|
|
+ /// Keep track of the first cycle value in the schedule. It starts
|
|
|
+ /// as zero, but the algorithm allows negative values.
|
|
|
+ int FirstCycle = 0;
|
|
|
+
|
|
|
+ /// Keep track of the last cycle value in the schedule.
|
|
|
+ int LastCycle = 0;
|
|
|
+
|
|
|
+ /// The initiation interval (II) for the schedule.
|
|
|
+ int InitiationInterval = 0;
|
|
|
+
|
|
|
+ /// Target machine information.
|
|
|
+ const TargetSubtargetInfo &ST;
|
|
|
+
|
|
|
+ /// Virtual register information.
|
|
|
+ MachineRegisterInfo &MRI;
|
|
|
+
|
|
|
+ std::unique_ptr<DFAPacketizer> Resources;
|
|
|
+
|
|
|
+public:
|
|
|
+ SMSchedule(MachineFunction *mf)
|
|
|
+ : ST(mf->getSubtarget()), MRI(mf->getRegInfo()),
|
|
|
+ Resources(ST.getInstrInfo()->CreateTargetScheduleState(ST)) {}
|
|
|
+
|
|
|
+ void reset() {
|
|
|
+ ScheduledInstrs.clear();
|
|
|
+ InstrToCycle.clear();
|
|
|
+ RegToStageDiff.clear();
|
|
|
+ FirstCycle = 0;
|
|
|
+ LastCycle = 0;
|
|
|
+ InitiationInterval = 0;
|
|
|
+ }
|
|
|
+
|
|
|
+ /// Set the initiation interval for this schedule.
|
|
|
+ void setInitiationInterval(int ii) { InitiationInterval = ii; }
|
|
|
+
|
|
|
+ /// Return the first cycle in the completed schedule. This
|
|
|
+ /// can be a negative value.
|
|
|
+ int getFirstCycle() const { return FirstCycle; }
|
|
|
+
|
|
|
+ /// Return the last cycle in the finalized schedule.
|
|
|
+ int getFinalCycle() const { return FirstCycle + InitiationInterval - 1; }
|
|
|
+
|
|
|
+ /// Return the cycle of the earliest scheduled instruction in the dependence
|
|
|
+ /// chain.
|
|
|
+ int earliestCycleInChain(const SDep &Dep);
|
|
|
+
|
|
|
+ /// Return the cycle of the latest scheduled instruction in the dependence
|
|
|
+ /// chain.
|
|
|
+ int latestCycleInChain(const SDep &Dep);
|
|
|
+
|
|
|
+ void computeStart(SUnit *SU, int *MaxEarlyStart, int *MinLateStart,
|
|
|
+ int *MinEnd, int *MaxStart, int II, SwingSchedulerDAG *DAG);
|
|
|
+ bool insert(SUnit *SU, int StartCycle, int EndCycle, int II);
|
|
|
+
|
|
|
+ /// Iterators for the cycle to instruction map.
|
|
|
+ using sched_iterator = DenseMap<int, std::deque<SUnit *>>::iterator;
|
|
|
+ using const_sched_iterator =
|
|
|
+ DenseMap<int, std::deque<SUnit *>>::const_iterator;
|
|
|
+
|
|
|
+ /// Return true if the instruction is scheduled at the specified stage.
|
|
|
+ bool isScheduledAtStage(SUnit *SU, unsigned StageNum) {
|
|
|
+ return (stageScheduled(SU) == (int)StageNum);
|
|
|
+ }
|
|
|
+
|
|
|
+ /// Return the stage for a scheduled instruction. Return -1 if
|
|
|
+ /// the instruction has not been scheduled.
|
|
|
+ int stageScheduled(SUnit *SU) const {
|
|
|
+ std::map<SUnit *, int>::const_iterator it = InstrToCycle.find(SU);
|
|
|
+ if (it == InstrToCycle.end())
|
|
|
+ return -1;
|
|
|
+ return (it->second - FirstCycle) / InitiationInterval;
|
|
|
+ }
|
|
|
+
|
|
|
+ /// Return the cycle for a scheduled instruction. This function normalizes
|
|
|
+ /// the first cycle to be 0.
|
|
|
+ unsigned cycleScheduled(SUnit *SU) const {
|
|
|
+ std::map<SUnit *, int>::const_iterator it = InstrToCycle.find(SU);
|
|
|
+ assert(it != InstrToCycle.end() && "Instruction hasn't been scheduled.");
|
|
|
+ return (it->second - FirstCycle) % InitiationInterval;
|
|
|
+ }
|
|
|
+
|
|
|
+ /// Return the maximum stage count needed for this schedule.
|
|
|
+ unsigned getMaxStageCount() {
|
|
|
+ return (LastCycle - FirstCycle) / InitiationInterval;
|
|
|
+ }
|
|
|
+
|
|
|
+ /// Return the max. number of stages/iterations that can occur between a
|
|
|
+ /// register definition and its uses.
|
|
|
+ unsigned getStagesForReg(int Reg, unsigned CurStage) {
|
|
|
+ std::pair<unsigned, bool> Stages = RegToStageDiff[Reg];
|
|
|
+ if (CurStage > getMaxStageCount() && Stages.first == 0 && Stages.second)
|
|
|
+ return 1;
|
|
|
+ return Stages.first;
|
|
|
+ }
|
|
|
+
|
|
|
+ /// The number of stages for a Phi is a little different than other
|
|
|
+ /// instructions. The minimum value computed in RegToStageDiff is 1
|
|
|
+ /// because we assume the Phi is needed for at least 1 iteration.
|
|
|
+ /// This is not the case if the loop value is scheduled prior to the
|
|
|
+ /// Phi in the same stage. This function returns the number of stages
|
|
|
+ /// or iterations needed between the Phi definition and any uses.
|
|
|
+ unsigned getStagesForPhi(int Reg) {
|
|
|
+ std::pair<unsigned, bool> Stages = RegToStageDiff[Reg];
|
|
|
+ if (Stages.second)
|
|
|
+ return Stages.first;
|
|
|
+ return Stages.first - 1;
|
|
|
+ }
|
|
|
+
|
|
|
+ /// Return the instructions that are scheduled at the specified cycle.
|
|
|
+ std::deque<SUnit *> &getInstructions(int cycle) {
|
|
|
+ return ScheduledInstrs[cycle];
|
|
|
+ }
|
|
|
+
|
|
|
+ bool isValidSchedule(SwingSchedulerDAG *SSD);
|
|
|
+ void finalizeSchedule(SwingSchedulerDAG *SSD);
|
|
|
+ void orderDependence(SwingSchedulerDAG *SSD, SUnit *SU,
|
|
|
+ std::deque<SUnit *> &Insts);
|
|
|
+ bool isLoopCarried(SwingSchedulerDAG *SSD, MachineInstr &Phi);
|
|
|
+ bool isLoopCarriedDefOfUse(SwingSchedulerDAG *SSD, MachineInstr *Def,
|
|
|
+ MachineOperand &MO);
|
|
|
+ void print(raw_ostream &os) const;
|
|
|
+ void dump() const;
|
|
|
+};
|
|
|
+
|
|
|
+} // end anonymous namespace
|
|
|
|
|
|
unsigned SwingSchedulerDAG::Circuits::MaxPaths = 5;
|
|
|
char MachinePipeliner::ID = 0;
|
Aleksandr Urakov