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@@ -971,6 +971,80 @@ getWeightIterator(MachineBasicBlock::const_succ_iterator I) const {
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return Weights.begin() + index;
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return Weights.begin() + index;
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}
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}
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+/// Return whether (physical) register "Reg" has been <def>ined and not <kill>ed
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+/// as of just before "MI".
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+///
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+/// Search is localised to a neighborhood of
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+/// Neighborhood instructions before (searching for defs or kills) and N
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+/// instructions after (searching just for defs) MI.
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+MachineBasicBlock::LivenessQueryResult
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+MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI,
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+ unsigned Reg, MachineInstr *MI,
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+ unsigned Neighborhood) {
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+
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+ unsigned N = Neighborhood;
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+ MachineBasicBlock *MBB = MI->getParent();
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+
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+ // Start by searching backwards from MI, looking for kills, reads or defs.
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+
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+ MachineBasicBlock::iterator I(MI);
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+ // If this is the first insn in the block, don't search backwards.
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+ if (I != MBB->begin()) {
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+ do {
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+ --I;
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+
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+ MachineOperandIteratorBase::PhysRegInfo Analysis =
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+ MIOperands(I).analyzePhysReg(Reg, TRI);
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+
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+ if (Analysis.Kills)
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+ // Register killed, so isn't live.
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+ return LQR_Dead;
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+
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+ else if (Analysis.DefinesOverlap || Analysis.ReadsOverlap)
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+ // Defined or read without a previous kill - live.
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+ return (Analysis.Defines || Analysis.Reads) ?
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+ LQR_Live : LQR_OverlappingLive;
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+
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+ } while (I != MBB->begin() && --N > 0);
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+ }
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+
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+ // Did we get to the start of the block?
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+ if (I == MBB->begin()) {
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+ // If so, the register's state is definitely defined by the live-in state.
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+ for (MCRegAliasIterator RAI(Reg, TRI, /*IncludeSelf=*/true);
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+ RAI.isValid(); ++RAI) {
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+ if (MBB->isLiveIn(*RAI))
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+ return (*RAI == Reg) ? LQR_Live : LQR_OverlappingLive;
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+ }
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+
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+ return LQR_Dead;
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+ }
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+
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+ N = Neighborhood;
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+
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+ // Try searching forwards from MI, looking for reads or defs.
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+ I = MachineBasicBlock::iterator(MI);
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+ // If this is the last insn in the block, don't search forwards.
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+ if (I != MBB->end()) {
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+ for (++I; I != MBB->end() && N > 0; ++I, --N) {
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+ MachineOperandIteratorBase::PhysRegInfo Analysis =
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+ MIOperands(I).analyzePhysReg(Reg, TRI);
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+
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+ if (Analysis.ReadsOverlap)
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+ // Used, therefore must have been live.
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+ return (Analysis.Reads) ?
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+ LQR_Live : LQR_OverlappingLive;
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+
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+ else if (Analysis.DefinesOverlap)
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+ // Defined (but not read) therefore cannot have been live.
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+ return LQR_Dead;
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+ }
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+ }
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+
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+ // At this point we have no idea of the liveness of the register.
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+ return LQR_Unknown;
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+}
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+
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void llvm::WriteAsOperand(raw_ostream &OS, const MachineBasicBlock *MBB,
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void llvm::WriteAsOperand(raw_ostream &OS, const MachineBasicBlock *MBB,
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bool t) {
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bool t) {
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OS << "BB#" << MBB->getNumber();
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OS << "BB#" << MBB->getNumber();
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