[MIR] MIRNamer pass for improving MIR test authoring experience.

This patch reuses the MIR vreg renamer from the MIRCanonicalizerPass to cleanup
names of vregs in a MIR file for MIR test authors. I found it useful when
writing a regression test for a globalisel failure I encountered recently and
thought it might be useful for other folks as well.

Differential Revision: https://reviews.llvm.org/D67209


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371121 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/InitializePasses.h

@@ -252,6 +252,7 @@ void initializeLowerInvokeLegacyPassPass(PassRegistry&);
 void initializeLowerSwitchPass(PassRegistry&);
 void initializeLowerTypeTestsPass(PassRegistry&);
 void initializeMIRCanonicalizerPass(PassRegistry &);
+void initializeMIRNamerPass(PassRegistry &);
 void initializeMIRPrintingPassPass(PassRegistry&);
 void initializeMachineBlockFrequencyInfoPass(PassRegistry&);
 void initializeMachineBlockPlacementPass(PassRegistry&);

lib/CodeGen/CMakeLists.txt

@@ -122,6 +122,7 @@ add_llvm_library(LLVMCodeGen
   RegisterScavenging.cpp
   RenameIndependentSubregs.cpp
   MIRVRegNamerUtils.cpp
+  MIRNamerPass.cpp
   MIRCanonicalizerPass.cpp
   RegisterUsageInfo.cpp
   RegUsageInfoCollector.cpp

lib/CodeGen/CodeGen.cpp

@@ -54,6 +54,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
   initializeLocalStackSlotPassPass(Registry);
   initializeLowerIntrinsicsPass(Registry);
   initializeMIRCanonicalizerPass(Registry);
+  initializeMIRNamerPass(Registry);
   initializeMachineBlockFrequencyInfoPass(Registry);
   initializeMachineBlockPlacementPass(Registry);
   initializeMachineBlockPlacementStatsPass(Registry);

lib/CodeGen/MIRNamerPass.cpp

@@ -0,0 +1,77 @@
+//===----------------------- MIRNamer.cpp - MIR Namer ---------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// The purpose of this pass is to rename virtual register operands with the goal
+// of making it easier to author easier to read tests for MIR. This pass reuses
+// the vreg renamer used by MIRCanonicalizerPass.
+//
+// Basic Usage:
+//
+// llc -o - -run-pass mir-namer example.mir
+//
+//===----------------------------------------------------------------------===//
+
+#include "MIRVRegNamerUtils.h"
+#include "llvm/ADT/PostOrderIterator.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/Passes.h"
+
+using namespace llvm;
+
+namespace llvm {
+extern char &MIRNamerID;
+} // namespace llvm
+
+#define DEBUG_TYPE "mir-namer"
+
+namespace {
+
+class MIRNamer : public MachineFunctionPass {
+public:
+  static char ID;
+  MIRNamer() : MachineFunctionPass(ID) {}
+
+  StringRef getPassName() const override {
+    return "Rename virtual register operands";
+  }
+
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+    AU.setPreservesCFG();
+    MachineFunctionPass::getAnalysisUsage(AU);
+  }
+
+  bool runOnMachineFunction(MachineFunction &MF) override {
+    bool Changed = false;
+
+    if (MF.empty())
+      return Changed;
+
+    NamedVRegCursor NVC(MF.getRegInfo());
+
+    ReversePostOrderTraversal<MachineBasicBlock *> RPOT(&*MF.begin());
+    for (auto &MBB : RPOT)
+      Changed |= NVC.renameVRegs(MBB);
+
+    return Changed;
+  }
+};
+
+} // end anonymous namespace
+
+char MIRNamer::ID;
+
+char &llvm::MIRNamerID = MIRNamer::ID;
+
+INITIALIZE_PASS_BEGIN(MIRNamer, "mir-namer", "Rename Register Operands", false,
+                      false)
+
+INITIALIZE_PASS_END(MIRNamer, "mir-namer", "Rename Register Operands", false,
+                    false)

test/CodeGen/MIR/AArch64/mirnamer.mir

@@ -0,0 +1,90 @@
+# RUN: llc -mtriple aarch64-apple-ios -run-pass mir-namer -verify-machineinstrs -o - %s | FileCheck %s
+
+---
+name: foo
+body:             |
+  bb.0:
+
+    ;CHECK: bb
+    ;CHECK-NEXT: %namedVReg1353:_(p0) = COPY $d0
+    ;CHECK-NEXT: %namedVReg1352:_(<4 x s32>) = COPY $q0
+    ;CHECK-NEXT: G_STORE %namedVReg1352(<4 x s32>), %namedVReg1353
+
+    liveins: $q0, $d0
+    %1:fpr(p0) = COPY $d0
+    %0:fpr(<4 x s32>) = COPY $q0
+    G_STORE %0(<4 x s32>), %1(p0) :: (store 16)
+...
+---
+name: bar
+stack:
+  - { id: 0, type: default, offset: 0, size: 4, alignment: 4,
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+      local-offset: -4, debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
+body:             |
+  bb.0:
+
+    ;CHECK: bb
+    ;CHECK-NEXT: %namedVReg1370:gpr32 = LDRWui
+    ;CHECK-NEXT: %namedVReg1371:gpr32 = MOVi32imm 1
+    ;CHECK-NEXT: %namedVReg1372:gpr32 = LDRWui
+    ;CHECK-NEXT: %namedVReg1373:gpr32 = MOVi32imm 2
+    ;CHECK-NEXT: %namedVReg1359:gpr32 = LDRWui
+    ;CHECK-NEXT: %namedVReg1360:gpr32 = MOVi32imm 3
+    ;CHECK-NEXT: %namedVReg1365:gpr32 = nsw ADDWrr
+    ;CHECK-NEXT: %namedVReg1361:gpr32 = LDRWui
+    ;CHECK-NEXT: %namedVReg1366:gpr32 = nsw ADDWrr
+    ;CHECK-NEXT: %namedVReg1362:gpr32 = MOVi32imm 4
+    ;CHECK-NEXT: %namedVReg1355:gpr32 = nsw ADDWrr
+    ;CHECK-NEXT: %namedVReg1363:gpr32 = LDRWui
+    ;CHECK-NEXT: %namedVReg1364:gpr32 = MOVi32imm 5
+
+    %0:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load 8)
+    %1:gpr32 = MOVi32imm 1
+    %2:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load 8)
+    %3:gpr32 = MOVi32imm 2
+    %4:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load 8)
+    %5:gpr32 = MOVi32imm 3
+    %10:gpr32 = nsw ADDWrr %0:gpr32, %1:gpr32
+    %6:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load 8)
+    %11:gpr32 = nsw ADDWrr %2:gpr32, %3:gpr32
+    %7:gpr32 = MOVi32imm 4
+    %12:gpr32 = nsw ADDWrr %4:gpr32, %5:gpr32
+    %8:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load 8)
+    %9:gpr32 = MOVi32imm 5
+    %13:gpr32 = nsw ADDWrr %6:gpr32, %7:gpr32
+    %14:gpr32 = nsw ADDWrr %8:gpr32, %9:gpr32
+    %15:gpr32 = nsw ADDWrr %10:gpr32, %11:gpr32
+    %16:gpr32 = nsw ADDWrr %12:gpr32, %13:gpr32
+    %17:gpr32 = nsw ADDWrr %14:gpr32, %15:gpr32
+    %18:gpr32 = nsw ADDWrr %16:gpr32, %17:gpr32
+    $w0 = COPY %18
+    RET_ReallyLR implicit $w0
+...
+---
+name: baz
+stack:
+  - { id: 0, type: default, offset: 0, size: 4, alignment: 4,
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+      local-offset: -4, debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
+body:             |
+  bb.0:
+    liveins: $x0, $x1, $d0, $d1
+
+    ;CHECK: bb
+    ;CHECK-NEXT: %namedVReg1355:gpr32 = LDRWui
+    ;CHECK-NEXT: %namedVReg1354:gpr32 = COPY %namedVReg1355
+    ;CHECK-NEXT: %namedVReg1353:gpr32 = COPY %namedVReg1354
+    ;CHECK-NEXT: %namedVReg1352:gpr32 = COPY %namedVReg1353
+    ;CHECK-NEXT: $w0 = COPY %namedVReg1352
+
+    %0:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load 8)
+    %1:gpr32 = COPY %0
+    %2:gpr32 = COPY %1
+    %3:gpr32 = COPY %2
+    $w0 = COPY %3
+    RET_ReallyLR implicit $w0
+...
+