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@@ -619,13 +619,29 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
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case AMDGPU::WQM:
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case AMDGPU::WQM:
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case AMDGPU::SOFT_WQM:
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case AMDGPU::SOFT_WQM:
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case AMDGPU::WWM: {
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case AMDGPU::WWM: {
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- // If the destination register is a physical register there isn't really
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- // much we can do to fix this.
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- if (!TargetRegisterInfo::isVirtualRegister(MI.getOperand(0).getReg()))
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- continue;
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+ Register DstReg = MI.getOperand(0).getReg();
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const TargetRegisterClass *SrcRC, *DstRC;
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const TargetRegisterClass *SrcRC, *DstRC;
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std::tie(SrcRC, DstRC) = getCopyRegClasses(MI, *TRI, MRI);
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std::tie(SrcRC, DstRC) = getCopyRegClasses(MI, *TRI, MRI);
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+
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+ if (!TargetRegisterInfo::isVirtualRegister(DstReg)) {
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+ // If the destination register is a physical register there isn't
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+ // really much we can do to fix this.
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+ // Some special instructions use M0 as an input. Some even only use
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+ // the first lane. Insert a readfirstlane and hope for the best.
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+ if (DstReg == AMDGPU::M0 && TRI->hasVectorRegisters(SrcRC)) {
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+ Register TmpReg
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+ = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
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+
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+ BuildMI(MBB, MI, MI.getDebugLoc(),
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+ TII->get(AMDGPU::V_READFIRSTLANE_B32), TmpReg)
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+ .add(MI.getOperand(1));
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+ MI.getOperand(1).setReg(TmpReg);
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+ }
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+
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+ continue;
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+ }
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+
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if (isVGPRToSGPRCopy(SrcRC, DstRC, *TRI)) {
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if (isVGPRToSGPRCopy(SrcRC, DstRC, *TRI)) {
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unsigned SrcReg = MI.getOperand(1).getReg();
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unsigned SrcReg = MI.getOperand(1).getReg();
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if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
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if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
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