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@@ -114,8 +114,8 @@ option specifies "``-``", then the output will also be sent to standard output.
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.. option:: -register-file-size=<size>
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.. option:: -register-file-size=<size>
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Specify the size of the register file. When specified, this flag limits how
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Specify the size of the register file. When specified, this flag limits how
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- many temporary registers are available for register renaming purposes. A value
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- of zero for this flag means "unlimited number of temporary registers".
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+ many physical registers are available for register renaming purposes. A value
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+ of zero for this flag means "unlimited number of physical registers".
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.. option:: -iterations=<number of iterations>
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.. option:: -iterations=<number of iterations>
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@@ -431,7 +431,7 @@ Parallelism).
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In the dot-product example, there are anti-dependencies introduced by
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In the dot-product example, there are anti-dependencies introduced by
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instructions from different iterations. However, those dependencies can be
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instructions from different iterations. However, those dependencies can be
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removed at register renaming stage (at the cost of allocating register aliases,
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removed at register renaming stage (at the cost of allocating register aliases,
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-and therefore consuming temporary registers).
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+and therefore consuming physical registers).
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Table *Average Wait times* helps diagnose performance issues that are caused by
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Table *Average Wait times* helps diagnose performance issues that are caused by
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the presence of long latency instructions and potentially long data dependencies
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the presence of long latency instructions and potentially long data dependencies
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@@ -670,7 +670,7 @@ When instructions are executed, the retire control unit flags the
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instruction as "ready to retire."
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instruction as "ready to retire."
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Instructions are retired in program order. The register file is notified of
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Instructions are retired in program order. The register file is notified of
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-the retirement so that it can free the temporary registers that were allocated
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+the retirement so that it can free the physical registers that were allocated
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for the instruction during the register renaming stage.
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for the instruction during the register renaming stage.
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Load/Store Unit and Memory Consistency Model
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Load/Store Unit and Memory Consistency Model
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