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@@ -674,8 +674,8 @@ def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
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Requires<[HasFP16]>,
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Sched<[WriteFPCVT]>;
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-def : Pat<(f32 (fpextend HPR:$Sm)),
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- (VCVTBHS (COPY_TO_REGCLASS HPR:$Sm, SPR))>;
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+def : FullFP16Pat<(f32 (fpextend HPR:$Sm)),
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+ (VCVTBHS (COPY_TO_REGCLASS HPR:$Sm, SPR))>;
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def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
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/* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm",
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@@ -750,17 +750,17 @@ def VCVTTDH : ADuI<0b11101, 0b11, 0b0011, 0b11, 0,
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let Inst{5} = Dm{4};
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}
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-def : Pat<(fp_to_f16 SPR:$a),
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- (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
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+def : FP16Pat<(fp_to_f16 SPR:$a),
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+ (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
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-def : Pat<(fp_to_f16 (f64 DPR:$a)),
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- (i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))>;
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+def : FP16Pat<(fp_to_f16 (f64 DPR:$a)),
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+ (i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))>;
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-def : Pat<(f16_to_fp GPR:$a),
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- (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
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+def : FP16Pat<(f16_to_fp GPR:$a),
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+ (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
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-def : Pat<(f64 (f16_to_fp GPR:$a)),
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- (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>;
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+def : FP16Pat<(f64 (f16_to_fp GPR:$a)),
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+ (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>;
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multiclass vcvt_inst<string opc, bits<2> rm,
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SDPatternOperator node = null_frag> {
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