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@@ -1,4 +1,4 @@
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-//===- DFAPacketizerEmitter.cpp - Packetization DFA for a VLIW machine-----===//
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+//===- DFAPacketizerEmitter.cpp - Packetization DFA for a VLIW machine ----===//
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//
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//
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// The LLVM Compiler Infrastructure
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// The LLVM Compiler Infrastructure
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//
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//
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@@ -28,6 +28,7 @@
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#include <map>
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#include <map>
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#include <string>
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#include <string>
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#include <queue>
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#include <queue>
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+
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using namespace llvm;
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using namespace llvm;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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@@ -73,7 +74,8 @@ namespace {
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InsnInput = addDFAFuncUnits(InsnInput, U);
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InsnInput = addDFAFuncUnits(InsnInput, U);
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return InsnInput;
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return InsnInput;
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}
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}
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-}
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+} // end anonymous namespace
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+
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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#ifndef NDEBUG
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#ifndef NDEBUG
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@@ -149,7 +151,7 @@ public:
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void run(raw_ostream &OS);
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void run(raw_ostream &OS);
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};
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};
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-} // End anonymous namespace.
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+} // end anonymous namespace
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//
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//
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//
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//
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@@ -234,7 +236,7 @@ class State {
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//
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//
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bool hasTransition(std::vector<unsigned> InsnClass) const;
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bool hasTransition(std::vector<unsigned> InsnClass) const;
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};
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};
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-} // End anonymous namespace.
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+} // end anonymous namespace
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//
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//
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// class DFA: deterministic finite automaton for processor resource tracking.
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// class DFA: deterministic finite automaton for processor resource tracking.
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@@ -262,7 +264,7 @@ public:
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int numInsnClasses = 0,
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int numInsnClasses = 0,
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int maxResources = 0, int numCombos = 0, int maxStages = 0);
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int maxResources = 0, int numCombos = 0, int maxStages = 0);
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};
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};
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-} // End anonymous namespace.
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+} // end anonymous namespace
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#ifndef NDEBUG
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#ifndef NDEBUG
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// To enable debugging, run llvm-tblgen with: "-debug-only dfa-emitter".
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// To enable debugging, run llvm-tblgen with: "-debug-only dfa-emitter".
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@@ -305,7 +307,7 @@ void dbgsIndent(unsigned indent) {
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DEBUG(dbgs() << " ");
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DEBUG(dbgs() << " ");
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}
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}
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}
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}
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-#endif
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+#endif // NDEBUG
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//
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//
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// Constructors and destructors for State and DFA
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// Constructors and destructors for State and DFA
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@@ -454,7 +456,6 @@ void State::AddInsnClassStages(std::vector<unsigned> &InsnClass,
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}
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}
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}
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}
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-
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//
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//
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// canMaybeAddInsnClass - Quickly verifies if an instruction of type InsnClass
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// canMaybeAddInsnClass - Quickly verifies if an instruction of type InsnClass
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// may be a valid transition from this state i.e., can an instruction of type
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// may be a valid transition from this state i.e., can an instruction of type
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@@ -505,7 +506,6 @@ bool State::canMaybeAddInsnClass(std::vector<unsigned> &InsnClass,
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return false;
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return false;
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}
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}
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-
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const State &DFA::newState() {
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const State &DFA::newState() {
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auto IterPair = states.insert(State());
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auto IterPair = states.insert(State());
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assert(IterPair.second && "State already exists");
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assert(IterPair.second && "State already exists");
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@@ -518,7 +518,6 @@ DFAPacketizerEmitter::DFAPacketizerEmitter(RecordKeeper &R):
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TargetName(CodeGenTarget(R).getName()),
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TargetName(CodeGenTarget(R).getName()),
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allInsnClasses(), Records(R) {}
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allInsnClasses(), Records(R) {}
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-
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//
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//
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// writeTableAndAPI - Print out a table representing the DFA and the
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// writeTableAndAPI - Print out a table representing the DFA and the
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// associated API to create a DFA packetizer.
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// associated API to create a DFA packetizer.
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@@ -626,7 +625,6 @@ void DFA::writeTableAndAPI(raw_ostream &OS, const std::string &TargetName,
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OS << "};\n";
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OS << "};\n";
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OS << "} // namespace\n";
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OS << "} // namespace\n";
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-
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//
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//
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// Emit DFA Packetizer tables if the target is a VLIW machine.
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// Emit DFA Packetizer tables if the target is a VLIW machine.
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//
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//
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@@ -640,7 +638,6 @@ void DFA::writeTableAndAPI(raw_ostream &OS, const std::string &TargetName,
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OS << "} // End llvm namespace \n";
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OS << "} // End llvm namespace \n";
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}
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}
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-
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//
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//
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// collectAllFuncUnits - Construct a map of function unit names to bits.
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// collectAllFuncUnits - Construct a map of function unit names to bits.
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//
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//
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@@ -735,7 +732,6 @@ int DFAPacketizerEmitter::collectAllComboFuncs(
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return numCombos;
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return numCombos;
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}
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}
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-
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//
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//
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// collectOneInsnClass - Populate allInsnClasses with one instruction class
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// collectOneInsnClass - Populate allInsnClasses with one instruction class
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//
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//
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@@ -940,7 +936,7 @@ void DFAPacketizerEmitter::run(raw_ostream &OS) {
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//
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//
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if (!current->hasTransition(InsnClass) &&
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if (!current->hasTransition(InsnClass) &&
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current->canMaybeAddInsnClass(InsnClass, ComboBitToBitsMap)) {
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current->canMaybeAddInsnClass(InsnClass, ComboBitToBitsMap)) {
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- const State *NewState = NULL;
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+ const State *NewState = nullptr;
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current->AddInsnClass(InsnClass, ComboBitToBitsMap, NewStateResources);
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current->AddInsnClass(InsnClass, ComboBitToBitsMap, NewStateResources);
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if (NewStateResources.size() == 0) {
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if (NewStateResources.size() == 0) {
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DEBUG(dbgs() << " Skipped - no new states generated\n");
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DEBUG(dbgs() << " Skipped - no new states generated\n");
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@@ -994,4 +990,4 @@ void EmitDFAPacketizer(RecordKeeper &RK, raw_ostream &OS) {
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DFAPacketizerEmitter(RK).run(OS);
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DFAPacketizerEmitter(RK).run(OS);
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}
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}
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-} // End llvm namespace
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+} // end namespaec llvm
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