[mips] Use reg-exp in tests to tolerate register indexes changing. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361966 91177308-0d34-0410-b5e6-96231b3b80d8

test/CodeGen/Mips/llvm-ir/fptosi.ll

@@ -39,123 +39,123 @@ define i32 @test1(float %t) {
 ; M32-LABEL: test1:
 ; M32:       # %bb.0: # %entry
 ; M32-NEXT:    trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
-; M32-NEXT:    # <MCOperand Reg:147>
-; M32-NEXT:    # <MCOperand Reg:159>>
+; M32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; M32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
-; M32-NEXT:    # <MCOperand Reg:19>>
+; M32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; M32-NEXT:    mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
-; M32-NEXT:    # <MCOperand Reg:321>
-; M32-NEXT:    # <MCOperand Reg:147>>
+; M32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ;
 ; M32R2-FP64-LABEL: test1:
 ; M32R2-FP64:       # %bb.0: # %entry
 ; M32R2-FP64-NEXT:    trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
-; M32R2-FP64-NEXT:    # <MCOperand Reg:147>
-; M32R2-FP64-NEXT:    # <MCOperand Reg:159>>
+; M32R2-FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M32R2-FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; M32R2-FP64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
-; M32R2-FP64-NEXT:    # <MCOperand Reg:19>>
+; M32R2-FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; M32R2-FP64-NEXT:    mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
-; M32R2-FP64-NEXT:    # <MCOperand Reg:321>
-; M32R2-FP64-NEXT:    # <MCOperand Reg:147>>
+; M32R2-FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M32R2-FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ;
 ; M32R2-SF-LABEL: test1:
 ; M32R2-SF:       # %bb.0: # %entry
 ; M32R2-SF-NEXT:    addiu $sp, $sp, -24 # <MCInst #{{[0-9]+}} ADDiu
-; M32R2-SF-NEXT:    # <MCOperand Reg:20>
-; M32R2-SF-NEXT:    # <MCOperand Reg:20>
+; M32R2-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M32R2-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; M32R2-SF-NEXT:    # <MCOperand Imm:-24>>
 ; M32R2-SF-NEXT:    .cfi_def_cfa_offset 24
 ; M32R2-SF-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
 ; M32R2-SF-NEXT:    # <MCInst #{{[0-9]+}} SW
-; M32R2-SF-NEXT:    # <MCOperand Reg:19>
-; M32R2-SF-NEXT:    # <MCOperand Reg:20>
+; M32R2-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M32R2-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; M32R2-SF-NEXT:    # <MCOperand Imm:20>>
 ; M32R2-SF-NEXT:    .cfi_offset 31, -4
 ; M32R2-SF-NEXT:    jal __fixsfsi # <MCInst #{{[0-9]+}} JAL
 ; M32R2-SF-NEXT:    # <MCOperand Expr:(__fixsfsi)>>
 ; M32R2-SF-NEXT:    nop # <MCInst #{{[0-9]+}} SLL
-; M32R2-SF-NEXT:    # <MCOperand Reg:21>
-; M32R2-SF-NEXT:    # <MCOperand Reg:21>
+; M32R2-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M32R2-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; M32R2-SF-NEXT:    # <MCOperand Imm:0>>
 ; M32R2-SF-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
 ; M32R2-SF-NEXT:    # <MCInst #{{[0-9]+}} LW
-; M32R2-SF-NEXT:    # <MCOperand Reg:19>
-; M32R2-SF-NEXT:    # <MCOperand Reg:20>
+; M32R2-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M32R2-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; M32R2-SF-NEXT:    # <MCOperand Imm:20>>
 ; M32R2-SF-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
-; M32R2-SF-NEXT:    # <MCOperand Reg:19>>
+; M32R2-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; M32R2-SF-NEXT:    addiu $sp, $sp, 24 # <MCInst #{{[0-9]+}} ADDiu
-; M32R2-SF-NEXT:    # <MCOperand Reg:20>
-; M32R2-SF-NEXT:    # <MCOperand Reg:20>
+; M32R2-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M32R2-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; M32R2-SF-NEXT:    # <MCOperand Imm:24>>
 ;
 ; M32R3R5-LABEL: test1:
 ; M32R3R5:       # %bb.0: # %entry
 ; M32R3R5-NEXT:    trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
-; M32R3R5-NEXT:    # <MCOperand Reg:147>
-; M32R3R5-NEXT:    # <MCOperand Reg:159>>
+; M32R3R5-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M32R3R5-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; M32R3R5-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
-; M32R3R5-NEXT:    # <MCOperand Reg:19>>
+; M32R3R5-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; M32R3R5-NEXT:    mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
-; M32R3R5-NEXT:    # <MCOperand Reg:321>
-; M32R3R5-NEXT:    # <MCOperand Reg:147>>
+; M32R3R5-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M32R3R5-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ;
 ; M32R6-LABEL: test1:
 ; M32R6:       # %bb.0: # %entry
 ; M32R6-NEXT:    trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
-; M32R6-NEXT:    # <MCOperand Reg:147>
-; M32R6-NEXT:    # <MCOperand Reg:159>>
+; M32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; M32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
-; M32R6-NEXT:    # <MCOperand Reg:21>
-; M32R6-NEXT:    # <MCOperand Reg:19>>
+; M32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; M32R6-NEXT:    mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
-; M32R6-NEXT:    # <MCOperand Reg:321>
-; M32R6-NEXT:    # <MCOperand Reg:147>>
+; M32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ;
 ; M64-LABEL: test1:
 ; M64:       # %bb.0: # %entry
 ; M64-NEXT:    trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
-; M64-NEXT:    # <MCOperand Reg:147>
-; M64-NEXT:    # <MCOperand Reg:159>>
+; M64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; M64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
-; M64-NEXT:    # <MCOperand Reg:301>>
+; M64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; M64-NEXT:    mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
-; M64-NEXT:    # <MCOperand Reg:321>
-; M64-NEXT:    # <MCOperand Reg:147>>
+; M64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ;
 ; M64R6-LABEL: test1:
 ; M64R6:       # %bb.0: # %entry
 ; M64R6-NEXT:    trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
-; M64R6-NEXT:    # <MCOperand Reg:147>
-; M64R6-NEXT:    # <MCOperand Reg:159>>
+; M64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; M64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
-; M64R6-NEXT:    # <MCOperand Reg:355>
-; M64R6-NEXT:    # <MCOperand Reg:301>>
+; M64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; M64R6-NEXT:    mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
-; M64R6-NEXT:    # <MCOperand Reg:321>
-; M64R6-NEXT:    # <MCOperand Reg:147>>
+; M64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ;
 ; MMR2-FP32-LABEL: test1:
 ; MMR2-FP32:       # %bb.0: # %entry
 ; MMR2-FP32-NEXT:    trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S_MM
-; MMR2-FP32-NEXT:    # <MCOperand Reg:147>
-; MMR2-FP32-NEXT:    # <MCOperand Reg:159>>
+; MMR2-FP32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR2-FP32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MMR2-FP32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR2-FP32-NEXT:    # <MCOperand Reg:19>>
+; MMR2-FP32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MMR2-FP32-NEXT:    mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1_MM
-; MMR2-FP32-NEXT:    # <MCOperand Reg:321>
-; MMR2-FP32-NEXT:    # <MCOperand Reg:147>>
+; MMR2-FP32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR2-FP32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ;
 ; MMR2-FP64-LABEL: test1:
 ; MMR2-FP64:       # %bb.0: # %entry
 ; MMR2-FP64-NEXT:    trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S_MM
-; MMR2-FP64-NEXT:    # <MCOperand Reg:147>
-; MMR2-FP64-NEXT:    # <MCOperand Reg:159>>
+; MMR2-FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR2-FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MMR2-FP64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR2-FP64-NEXT:    # <MCOperand Reg:19>>
+; MMR2-FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MMR2-FP64-NEXT:    mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1_MM
-; MMR2-FP64-NEXT:    # <MCOperand Reg:321>
-; MMR2-FP64-NEXT:    # <MCOperand Reg:147>>
+; MMR2-FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR2-FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ;
 ; MMR2-SF-LABEL: test1:
 ; MMR2-SF:       # %bb.0: # %entry
@@ -164,63 +164,63 @@ define i32 @test1(float %t) {
 ; MMR2-SF-NEXT:    .cfi_def_cfa_offset 24
 ; MMR2-SF-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
 ; MMR2-SF-NEXT:    # <MCInst #{{[0-9]+}} SWSP_MM
-; MMR2-SF-NEXT:    # <MCOperand Reg:19>
-; MMR2-SF-NEXT:    # <MCOperand Reg:20>
+; MMR2-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR2-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR2-SF-NEXT:    # <MCOperand Imm:20>>
 ; MMR2-SF-NEXT:    .cfi_offset 31, -4
 ; MMR2-SF-NEXT:    jal __fixsfsi # <MCInst #{{[0-9]+}} JAL_MM
 ; MMR2-SF-NEXT:    # <MCOperand Expr:(__fixsfsi)>>
 ; MMR2-SF-NEXT:    nop # <MCInst #{{[0-9]+}} SLL
-; MMR2-SF-NEXT:    # <MCOperand Reg:21>
-; MMR2-SF-NEXT:    # <MCOperand Reg:21>
+; MMR2-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR2-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR2-SF-NEXT:    # <MCOperand Imm:0>>
 ; MMR2-SF-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
 ; MMR2-SF-NEXT:    # <MCInst #{{[0-9]+}} LWSP_MM
-; MMR2-SF-NEXT:    # <MCOperand Reg:19>
-; MMR2-SF-NEXT:    # <MCOperand Reg:20>
+; MMR2-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR2-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR2-SF-NEXT:    # <MCOperand Imm:20>>
 ; MMR2-SF-NEXT:    addiusp 24 # <MCInst #{{[0-9]+}} ADDIUSP_MM
 ; MMR2-SF-NEXT:    # <MCOperand Imm:24>>
 ; MMR2-SF-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
-; MMR2-SF-NEXT:    # <MCOperand Reg:19>>
+; MMR2-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ;
 ; MMR6-LABEL: test1:
 ; MMR6:       # %bb.0: # %entry
 ; MMR6-NEXT:    trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S_MMR6
-; MMR6-NEXT:    # <MCOperand Reg:147>
-; MMR6-NEXT:    # <MCOperand Reg:159>>
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MMR6-NEXT:    mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1_MM
-; MMR6-NEXT:    # <MCOperand Reg:321>
-; MMR6-NEXT:    # <MCOperand Reg:147>>
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
-; MMR6-NEXT:    # <MCOperand Reg:19>>
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ;
 ; MMR6-SF-LABEL: test1:
 ; MMR6-SF:       # %bb.0: # %entry
 ; MMR6-SF-NEXT:    addiu $sp, $sp, -24 # <MCInst #{{[0-9]+}} ADDiu
-; MMR6-SF-NEXT:    # <MCOperand Reg:20>
-; MMR6-SF-NEXT:    # <MCOperand Reg:20>
+; MMR6-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-SF-NEXT:    # <MCOperand Imm:-24>>
 ; MMR6-SF-NEXT:    .cfi_def_cfa_offset 24
 ; MMR6-SF-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
 ; MMR6-SF-NEXT:    # <MCInst #{{[0-9]+}} SW
-; MMR6-SF-NEXT:    # <MCOperand Reg:19>
-; MMR6-SF-NEXT:    # <MCOperand Reg:20>
+; MMR6-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-SF-NEXT:    # <MCOperand Imm:20>>
 ; MMR6-SF-NEXT:    .cfi_offset 31, -4
 ; MMR6-SF-NEXT:    jalr __fixsfsi # <MCInst #{{[0-9]+}} JALRC16_MMR6
 ; MMR6-SF-NEXT:    # <MCOperand Expr:(__fixsfsi)>>
 ; MMR6-SF-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
 ; MMR6-SF-NEXT:    # <MCInst #{{[0-9]+}} LW
-; MMR6-SF-NEXT:    # <MCOperand Reg:19>
-; MMR6-SF-NEXT:    # <MCOperand Reg:20>
+; MMR6-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-SF-NEXT:    # <MCOperand Imm:20>>
 ; MMR6-SF-NEXT:    addiu $sp, $sp, 24 # <MCInst #{{[0-9]+}} ADDiu
-; MMR6-SF-NEXT:    # <MCOperand Reg:20>
-; MMR6-SF-NEXT:    # <MCOperand Reg:20>
+; MMR6-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-SF-NEXT:    # <MCOperand Imm:24>>
 ; MMR6-SF-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
-; MMR6-SF-NEXT:    # <MCOperand Reg:19>>
+; MMR6-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 entry:
   %conv = fptosi float %t to i32
   ret i32 %conv
@@ -230,123 +230,123 @@ define i32 @test2(double %t) {
 ; M32-LABEL: test2:
 ; M32:       # %bb.0: # %entry
 ; M32-NEXT:    trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D32
-; M32-NEXT:    # <MCOperand Reg:147>
-; M32-NEXT:    # <MCOperand Reg:133>>
+; M32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; M32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
-; M32-NEXT:    # <MCOperand Reg:19>>
+; M32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; M32-NEXT:    mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
-; M32-NEXT:    # <MCOperand Reg:321>
-; M32-NEXT:    # <MCOperand Reg:147>>
+; M32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ;
 ; M32R2-FP64-LABEL: test2:
 ; M32R2-FP64:       # %bb.0: # %entry
 ; M32R2-FP64-NEXT:    trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D64
-; M32R2-FP64-NEXT:    # <MCOperand Reg:147>
-; M32R2-FP64-NEXT:    # <MCOperand Reg:373>>
+; M32R2-FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M32R2-FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; M32R2-FP64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
-; M32R2-FP64-NEXT:    # <MCOperand Reg:19>>
+; M32R2-FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; M32R2-FP64-NEXT:    mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
-; M32R2-FP64-NEXT:    # <MCOperand Reg:321>
-; M32R2-FP64-NEXT:    # <MCOperand Reg:147>>
+; M32R2-FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M32R2-FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ;
 ; M32R2-SF-LABEL: test2:
 ; M32R2-SF:       # %bb.0: # %entry
 ; M32R2-SF-NEXT:    addiu $sp, $sp, -24 # <MCInst #{{[0-9]+}} ADDiu
-; M32R2-SF-NEXT:    # <MCOperand Reg:20>
-; M32R2-SF-NEXT:    # <MCOperand Reg:20>
+; M32R2-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M32R2-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; M32R2-SF-NEXT:    # <MCOperand Imm:-24>>
 ; M32R2-SF-NEXT:    .cfi_def_cfa_offset 24
 ; M32R2-SF-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
 ; M32R2-SF-NEXT:    # <MCInst #{{[0-9]+}} SW
-; M32R2-SF-NEXT:    # <MCOperand Reg:19>
-; M32R2-SF-NEXT:    # <MCOperand Reg:20>
+; M32R2-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M32R2-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; M32R2-SF-NEXT:    # <MCOperand Imm:20>>
 ; M32R2-SF-NEXT:    .cfi_offset 31, -4
 ; M32R2-SF-NEXT:    jal __fixdfsi # <MCInst #{{[0-9]+}} JAL
 ; M32R2-SF-NEXT:    # <MCOperand Expr:(__fixdfsi)>>
 ; M32R2-SF-NEXT:    nop # <MCInst #{{[0-9]+}} SLL
-; M32R2-SF-NEXT:    # <MCOperand Reg:21>
-; M32R2-SF-NEXT:    # <MCOperand Reg:21>
+; M32R2-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M32R2-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; M32R2-SF-NEXT:    # <MCOperand Imm:0>>
 ; M32R2-SF-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
 ; M32R2-SF-NEXT:    # <MCInst #{{[0-9]+}} LW
-; M32R2-SF-NEXT:    # <MCOperand Reg:19>
-; M32R2-SF-NEXT:    # <MCOperand Reg:20>
+; M32R2-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M32R2-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; M32R2-SF-NEXT:    # <MCOperand Imm:20>>
 ; M32R2-SF-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
-; M32R2-SF-NEXT:    # <MCOperand Reg:19>>
+; M32R2-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; M32R2-SF-NEXT:    addiu $sp, $sp, 24 # <MCInst #{{[0-9]+}} ADDiu
-; M32R2-SF-NEXT:    # <MCOperand Reg:20>
-; M32R2-SF-NEXT:    # <MCOperand Reg:20>
+; M32R2-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M32R2-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; M32R2-SF-NEXT:    # <MCOperand Imm:24>>
 ;
 ; M32R3R5-LABEL: test2:
 ; M32R3R5:       # %bb.0: # %entry
 ; M32R3R5-NEXT:    trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D32
-; M32R3R5-NEXT:    # <MCOperand Reg:147>
-; M32R3R5-NEXT:    # <MCOperand Reg:133>>
+; M32R3R5-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M32R3R5-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; M32R3R5-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
-; M32R3R5-NEXT:    # <MCOperand Reg:19>>
+; M32R3R5-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; M32R3R5-NEXT:    mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
-; M32R3R5-NEXT:    # <MCOperand Reg:321>
-; M32R3R5-NEXT:    # <MCOperand Reg:147>>
+; M32R3R5-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M32R3R5-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ;
 ; M32R6-LABEL: test2:
 ; M32R6:       # %bb.0: # %entry
 ; M32R6-NEXT:    trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D64
-; M32R6-NEXT:    # <MCOperand Reg:147>
-; M32R6-NEXT:    # <MCOperand Reg:373>>
+; M32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; M32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
-; M32R6-NEXT:    # <MCOperand Reg:21>
-; M32R6-NEXT:    # <MCOperand Reg:19>>
+; M32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; M32R6-NEXT:    mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
-; M32R6-NEXT:    # <MCOperand Reg:321>
-; M32R6-NEXT:    # <MCOperand Reg:147>>
+; M32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ;
 ; M64-LABEL: test2:
 ; M64:       # %bb.0: # %entry
 ; M64-NEXT:    trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D64
-; M64-NEXT:    # <MCOperand Reg:147>
-; M64-NEXT:    # <MCOperand Reg:373>>
+; M64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; M64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
-; M64-NEXT:    # <MCOperand Reg:301>>
+; M64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; M64-NEXT:    mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
-; M64-NEXT:    # <MCOperand Reg:321>
-; M64-NEXT:    # <MCOperand Reg:147>>
+; M64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ;
 ; M64R6-LABEL: test2:
 ; M64R6:       # %bb.0: # %entry
 ; M64R6-NEXT:    trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D64
-; M64R6-NEXT:    # <MCOperand Reg:147>
-; M64R6-NEXT:    # <MCOperand Reg:373>>
+; M64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; M64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
-; M64R6-NEXT:    # <MCOperand Reg:355>
-; M64R6-NEXT:    # <MCOperand Reg:301>>
+; M64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; M64R6-NEXT:    mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
-; M64R6-NEXT:    # <MCOperand Reg:321>
-; M64R6-NEXT:    # <MCOperand Reg:147>>
+; M64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; M64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ;
 ; MMR2-FP32-LABEL: test2:
 ; MMR2-FP32:       # %bb.0: # %entry
 ; MMR2-FP32-NEXT:    trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_MM
-; MMR2-FP32-NEXT:    # <MCOperand Reg:147>
-; MMR2-FP32-NEXT:    # <MCOperand Reg:133>>
+; MMR2-FP32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR2-FP32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MMR2-FP32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR2-FP32-NEXT:    # <MCOperand Reg:19>>
+; MMR2-FP32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MMR2-FP32-NEXT:    mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1_MM
-; MMR2-FP32-NEXT:    # <MCOperand Reg:321>
-; MMR2-FP32-NEXT:    # <MCOperand Reg:147>>
+; MMR2-FP32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR2-FP32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ;
 ; MMR2-FP64-LABEL: test2:
 ; MMR2-FP64:       # %bb.0: # %entry
 ; MMR2-FP64-NEXT:    cvt.w.d $f0, $f12 # <MCInst #{{[0-9]+}} CVT_W_D64_MM
-; MMR2-FP64-NEXT:    # <MCOperand Reg:147>
-; MMR2-FP64-NEXT:    # <MCOperand Reg:373>>
+; MMR2-FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR2-FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MMR2-FP64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR2-FP64-NEXT:    # <MCOperand Reg:19>>
+; MMR2-FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MMR2-FP64-NEXT:    mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1_MM
-; MMR2-FP64-NEXT:    # <MCOperand Reg:321>
-; MMR2-FP64-NEXT:    # <MCOperand Reg:147>>
+; MMR2-FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR2-FP64-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ;
 ; MMR2-SF-LABEL: test2:
 ; MMR2-SF:       # %bb.0: # %entry
@@ -355,63 +355,63 @@ define i32 @test2(double %t) {
 ; MMR2-SF-NEXT:    .cfi_def_cfa_offset 24
 ; MMR2-SF-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
 ; MMR2-SF-NEXT:    # <MCInst #{{[0-9]+}} SWSP_MM
-; MMR2-SF-NEXT:    # <MCOperand Reg:19>
-; MMR2-SF-NEXT:    # <MCOperand Reg:20>
+; MMR2-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR2-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR2-SF-NEXT:    # <MCOperand Imm:20>>
 ; MMR2-SF-NEXT:    .cfi_offset 31, -4
 ; MMR2-SF-NEXT:    jal __fixdfsi # <MCInst #{{[0-9]+}} JAL_MM
 ; MMR2-SF-NEXT:    # <MCOperand Expr:(__fixdfsi)>>
 ; MMR2-SF-NEXT:    nop # <MCInst #{{[0-9]+}} SLL
-; MMR2-SF-NEXT:    # <MCOperand Reg:21>
-; MMR2-SF-NEXT:    # <MCOperand Reg:21>
+; MMR2-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR2-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR2-SF-NEXT:    # <MCOperand Imm:0>>
 ; MMR2-SF-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
 ; MMR2-SF-NEXT:    # <MCInst #{{[0-9]+}} LWSP_MM
-; MMR2-SF-NEXT:    # <MCOperand Reg:19>
-; MMR2-SF-NEXT:    # <MCOperand Reg:20>
+; MMR2-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR2-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR2-SF-NEXT:    # <MCOperand Imm:20>>
 ; MMR2-SF-NEXT:    addiusp 24 # <MCInst #{{[0-9]+}} ADDIUSP_MM
 ; MMR2-SF-NEXT:    # <MCOperand Imm:24>>
 ; MMR2-SF-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
-; MMR2-SF-NEXT:    # <MCOperand Reg:19>>
+; MMR2-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ;
 ; MMR6-LABEL: test2:
 ; MMR6:       # %bb.0: # %entry
 ; MMR6-NEXT:    trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D_MMR6
-; MMR6-NEXT:    # <MCOperand Reg:147>
-; MMR6-NEXT:    # <MCOperand Reg:373>>
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MMR6-NEXT:    mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1_MM
-; MMR6-NEXT:    # <MCOperand Reg:321>
-; MMR6-NEXT:    # <MCOperand Reg:147>>
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
-; MMR6-NEXT:    # <MCOperand Reg:19>>
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ;
 ; MMR6-SF-LABEL: test2:
 ; MMR6-SF:       # %bb.0: # %entry
 ; MMR6-SF-NEXT:    addiu $sp, $sp, -24 # <MCInst #{{[0-9]+}} ADDiu
-; MMR6-SF-NEXT:    # <MCOperand Reg:20>
-; MMR6-SF-NEXT:    # <MCOperand Reg:20>
+; MMR6-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-SF-NEXT:    # <MCOperand Imm:-24>>
 ; MMR6-SF-NEXT:    .cfi_def_cfa_offset 24
 ; MMR6-SF-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
 ; MMR6-SF-NEXT:    # <MCInst #{{[0-9]+}} SW
-; MMR6-SF-NEXT:    # <MCOperand Reg:19>
-; MMR6-SF-NEXT:    # <MCOperand Reg:20>
+; MMR6-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-SF-NEXT:    # <MCOperand Imm:20>>
 ; MMR6-SF-NEXT:    .cfi_offset 31, -4
 ; MMR6-SF-NEXT:    jalr __fixdfsi # <MCInst #{{[0-9]+}} JALRC16_MMR6
 ; MMR6-SF-NEXT:    # <MCOperand Expr:(__fixdfsi)>>
 ; MMR6-SF-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
 ; MMR6-SF-NEXT:    # <MCInst #{{[0-9]+}} LW
-; MMR6-SF-NEXT:    # <MCOperand Reg:19>
-; MMR6-SF-NEXT:    # <MCOperand Reg:20>
+; MMR6-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-SF-NEXT:    # <MCOperand Imm:20>>
 ; MMR6-SF-NEXT:    addiu $sp, $sp, 24 # <MCInst #{{[0-9]+}} ADDiu
-; MMR6-SF-NEXT:    # <MCOperand Reg:20>
-; MMR6-SF-NEXT:    # <MCOperand Reg:20>
+; MMR6-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-SF-NEXT:    # <MCOperand Imm:24>>
 ; MMR6-SF-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
-; MMR6-SF-NEXT:    # <MCOperand Reg:19>>
+; MMR6-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 entry:
   %conv = fptosi double %t to i32
   ret i32 %conv

test/CodeGen/Mips/llvm-ir/store.ll

@@ -17,107 +17,107 @@ define void @f1(i8 %a) {
 ; MIPS32-LABEL: f1:
 ; MIPS32:       # %bb.0:
 ; MIPS32-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
-; MIPS32-NEXT:    # <MCOperand Reg:1>
+; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS32-NEXT:    # <MCOperand Expr:(%hi(a))>>
 ; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS32-NEXT:    # <MCOperand Reg:19>>
+; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MIPS32-NEXT:    sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB
-; MIPS32-NEXT:    # <MCOperand Reg:22>
-; MIPS32-NEXT:    # <MCOperand Reg:1>
+; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS32-NEXT:    # <MCOperand Expr:(%lo(a))>>
 ;
 ; MMR3-LABEL: f1:
 ; MMR3:       # %bb.0:
 ; MMR3-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
-; MMR3-NEXT:    # <MCOperand Reg:1>
+; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR3-NEXT:    # <MCOperand Expr:(%hi(a))>>
 ; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR3-NEXT:    # <MCOperand Reg:19>>
+; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MMR3-NEXT:    sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB_MM
-; MMR3-NEXT:    # <MCOperand Reg:22>
-; MMR3-NEXT:    # <MCOperand Reg:1>
+; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR3-NEXT:    # <MCOperand Expr:(%lo(a))>>
 ;
 ; MIPS32R6-LABEL: f1:
 ; MIPS32R6:       # %bb.0:
 ; MIPS32R6-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
-; MIPS32R6-NEXT:    # <MCOperand Reg:1>
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(a))>>
 ; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
-; MIPS32R6-NEXT:    # <MCOperand Reg:21>
-; MIPS32R6-NEXT:    # <MCOperand Reg:19>>
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MIPS32R6-NEXT:    sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB
-; MIPS32R6-NEXT:    # <MCOperand Reg:22>
-; MIPS32R6-NEXT:    # <MCOperand Reg:1>
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(a))>>
 ;
 ; MMR6-LABEL: f1:
 ; MMR6:       # %bb.0:
 ; MMR6-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
-; MMR6-NEXT:    # <MCOperand Reg:1>
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-NEXT:    # <MCOperand Expr:(%hi(a))>>
 ; MMR6-NEXT:    sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB_MM
-; MMR6-NEXT:    # <MCOperand Reg:22>
-; MMR6-NEXT:    # <MCOperand Reg:1>
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-NEXT:    # <MCOperand Expr:(%lo(a))>>
 ; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
-; MMR6-NEXT:    # <MCOperand Reg:19>>
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ;
 ; MIPS4-LABEL: f1:
 ; MIPS4:       # %bb.0:
 ; MIPS4-NEXT:    lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
-; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS4-NEXT:    # <MCOperand Expr:(%highest(a))>>
 ; MIPS4-NEXT:    daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS4-NEXT:    # <MCOperand Reg:30>
-; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS4-NEXT:    # <MCOperand Expr:(%higher(a))>>
 ; MIPS4-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS4-NEXT:    # <MCOperand Reg:30>
-; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS4-NEXT:    # <MCOperand Imm:16>>
 ; MIPS4-NEXT:    daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS4-NEXT:    # <MCOperand Reg:30>
-; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS4-NEXT:    # <MCOperand Expr:(%hi(a))>>
 ; MIPS4-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS4-NEXT:    # <MCOperand Reg:30>
-; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS4-NEXT:    # <MCOperand Imm:16>>
 ; MIPS4-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS4-NEXT:    # <MCOperand Reg:301>>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MIPS4-NEXT:    sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB64
-; MIPS4-NEXT:    # <MCOperand Reg:356>
-; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS4-NEXT:    # <MCOperand Expr:(%lo(a))>>
 ;
 ; MIPS64R6-LABEL: f1:
 ; MIPS64R6:       # %bb.0:
 ; MIPS64R6-NEXT:    lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
-; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(a))>>
 ; MIPS64R6-NEXT:    daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT:    # <MCOperand Reg:30>
-; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(a))>>
 ; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT:    # <MCOperand Reg:30>
-; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
 ; MIPS64R6-NEXT:    daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT:    # <MCOperand Reg:30>
-; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(a))>>
 ; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT:    # <MCOperand Reg:30>
-; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
 ; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
-; MIPS64R6-NEXT:    # <MCOperand Reg:355>
-; MIPS64R6-NEXT:    # <MCOperand Reg:301>>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MIPS64R6-NEXT:    sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB64
-; MIPS64R6-NEXT:    # <MCOperand Reg:356>
-; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(a))>>
   store i8 %a, i8 * @a
   ret void
@@ -127,107 +127,107 @@ define void @f2(i16 %a) {
 ; MIPS32-LABEL: f2:
 ; MIPS32:       # %bb.0:
 ; MIPS32-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
-; MIPS32-NEXT:    # <MCOperand Reg:1>
+; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS32-NEXT:    # <MCOperand Expr:(%hi(b))>>
 ; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS32-NEXT:    # <MCOperand Reg:19>>
+; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MIPS32-NEXT:    sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH
-; MIPS32-NEXT:    # <MCOperand Reg:22>
-; MIPS32-NEXT:    # <MCOperand Reg:1>
+; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS32-NEXT:    # <MCOperand Expr:(%lo(b))>>
 ;
 ; MMR3-LABEL: f2:
 ; MMR3:       # %bb.0:
 ; MMR3-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
-; MMR3-NEXT:    # <MCOperand Reg:1>
+; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR3-NEXT:    # <MCOperand Expr:(%hi(b))>>
 ; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR3-NEXT:    # <MCOperand Reg:19>>
+; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MMR3-NEXT:    sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH_MM
-; MMR3-NEXT:    # <MCOperand Reg:22>
-; MMR3-NEXT:    # <MCOperand Reg:1>
+; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR3-NEXT:    # <MCOperand Expr:(%lo(b))>>
 ;
 ; MIPS32R6-LABEL: f2:
 ; MIPS32R6:       # %bb.0:
 ; MIPS32R6-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
-; MIPS32R6-NEXT:    # <MCOperand Reg:1>
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(b))>>
 ; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
-; MIPS32R6-NEXT:    # <MCOperand Reg:21>
-; MIPS32R6-NEXT:    # <MCOperand Reg:19>>
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MIPS32R6-NEXT:    sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH
-; MIPS32R6-NEXT:    # <MCOperand Reg:22>
-; MIPS32R6-NEXT:    # <MCOperand Reg:1>
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(b))>>
 ;
 ; MMR6-LABEL: f2:
 ; MMR6:       # %bb.0:
 ; MMR6-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
-; MMR6-NEXT:    # <MCOperand Reg:1>
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-NEXT:    # <MCOperand Expr:(%hi(b))>>
 ; MMR6-NEXT:    sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH_MM
-; MMR6-NEXT:    # <MCOperand Reg:22>
-; MMR6-NEXT:    # <MCOperand Reg:1>
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-NEXT:    # <MCOperand Expr:(%lo(b))>>
 ; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
-; MMR6-NEXT:    # <MCOperand Reg:19>>
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ;
 ; MIPS4-LABEL: f2:
 ; MIPS4:       # %bb.0:
 ; MIPS4-NEXT:    lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
-; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS4-NEXT:    # <MCOperand Expr:(%highest(b))>>
 ; MIPS4-NEXT:    daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS4-NEXT:    # <MCOperand Reg:30>
-; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS4-NEXT:    # <MCOperand Expr:(%higher(b))>>
 ; MIPS4-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS4-NEXT:    # <MCOperand Reg:30>
-; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS4-NEXT:    # <MCOperand Imm:16>>
 ; MIPS4-NEXT:    daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS4-NEXT:    # <MCOperand Reg:30>
-; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS4-NEXT:    # <MCOperand Expr:(%hi(b))>>
 ; MIPS4-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS4-NEXT:    # <MCOperand Reg:30>
-; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS4-NEXT:    # <MCOperand Imm:16>>
 ; MIPS4-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS4-NEXT:    # <MCOperand Reg:301>>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MIPS4-NEXT:    sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH64
-; MIPS4-NEXT:    # <MCOperand Reg:356>
-; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS4-NEXT:    # <MCOperand Expr:(%lo(b))>>
 ;
 ; MIPS64R6-LABEL: f2:
 ; MIPS64R6:       # %bb.0:
 ; MIPS64R6-NEXT:    lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
-; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(b))>>
 ; MIPS64R6-NEXT:    daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT:    # <MCOperand Reg:30>
-; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(b))>>
 ; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT:    # <MCOperand Reg:30>
-; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
 ; MIPS64R6-NEXT:    daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT:    # <MCOperand Reg:30>
-; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(b))>>
 ; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT:    # <MCOperand Reg:30>
-; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
 ; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
-; MIPS64R6-NEXT:    # <MCOperand Reg:355>
-; MIPS64R6-NEXT:    # <MCOperand Reg:301>>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MIPS64R6-NEXT:    sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH64
-; MIPS64R6-NEXT:    # <MCOperand Reg:356>
-; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(b))>>
   store i16 %a, i16 * @b
   ret void
@@ -237,115 +237,115 @@ define void @f3(i32 %a) {
 ; MIPS32-LABEL: f3:
 ; MIPS32:       # %bb.0:
 ; MIPS32-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
-; MIPS32-NEXT:    # <MCOperand Reg:1>
+; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS32-NEXT:    # <MCOperand Expr:(%hi(c))>>
 ; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS32-NEXT:    # <MCOperand Reg:19>>
+; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MIPS32-NEXT:    sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW
-; MIPS32-NEXT:    # <MCOperand Reg:22>
-; MIPS32-NEXT:    # <MCOperand Reg:1>
+; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS32-NEXT:    # <MCOperand Expr:(%lo(c))>>
 ;
 ; MMR3-LABEL: f3:
 ; MMR3:       # %bb.0:
 ; MMR3-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
-; MMR3-NEXT:    # <MCOperand Reg:1>
+; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR3-NEXT:    # <MCOperand Expr:(%hi(c))>>
 ; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR3-NEXT:    # <MCOperand Reg:19>>
+; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MMR3-NEXT:    sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW_MM
-; MMR3-NEXT:    # <MCOperand Reg:22>
-; MMR3-NEXT:    # <MCOperand Reg:1>
+; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR3-NEXT:    # <MCOperand Expr:(%lo(c))>>
 ;
 ; MIPS32R6-LABEL: f3:
 ; MIPS32R6:       # %bb.0:
 ; MIPS32R6-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
-; MIPS32R6-NEXT:    # <MCOperand Reg:1>
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(c))>>
 ; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
-; MIPS32R6-NEXT:    # <MCOperand Reg:21>
-; MIPS32R6-NEXT:    # <MCOperand Reg:19>>
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MIPS32R6-NEXT:    sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW
-; MIPS32R6-NEXT:    # <MCOperand Reg:22>
-; MIPS32R6-NEXT:    # <MCOperand Reg:1>
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(c))>>
 ;
 ; MMR6-LABEL: f3:
 ; MMR6:       # %bb.0:
 ; MMR6-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
-; MMR6-NEXT:    # <MCOperand Reg:1>
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-NEXT:    # <MCOperand Expr:(%hi(c))>>
 ; MMR6-NEXT:    sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW_MM
-; MMR6-NEXT:    # <MCOperand Reg:22>
-; MMR6-NEXT:    # <MCOperand Reg:1>
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-NEXT:    # <MCOperand Expr:(%lo(c))>>
 ; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
-; MMR6-NEXT:    # <MCOperand Reg:19>>
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ;
 ; MIPS4-LABEL: f3:
 ; MIPS4:       # %bb.0:
 ; MIPS4-NEXT:    sll $1, $4, 0 # <MCInst #{{[0-9]+}} SLL
-; MIPS4-NEXT:    # <MCOperand Reg:1>
-; MIPS4-NEXT:    # <MCOperand Reg:22>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS4-NEXT:    # <MCOperand Imm:0>>
 ; MIPS4-NEXT:    lui $2, %highest(c) # <MCInst #{{[0-9]+}} LUi64
-; MIPS4-NEXT:    # <MCOperand Reg:416>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS4-NEXT:    # <MCOperand Expr:(%highest(c))>>
 ; MIPS4-NEXT:    daddiu $2, $2, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS4-NEXT:    # <MCOperand Reg:416>
-; MIPS4-NEXT:    # <MCOperand Reg:416>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS4-NEXT:    # <MCOperand Expr:(%higher(c))>>
 ; MIPS4-NEXT:    dsll $2, $2, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS4-NEXT:    # <MCOperand Reg:416>
-; MIPS4-NEXT:    # <MCOperand Reg:416>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS4-NEXT:    # <MCOperand Imm:16>>
 ; MIPS4-NEXT:    daddiu $2, $2, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS4-NEXT:    # <MCOperand Reg:416>
-; MIPS4-NEXT:    # <MCOperand Reg:416>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS4-NEXT:    # <MCOperand Expr:(%hi(c))>>
 ; MIPS4-NEXT:    dsll $2, $2, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS4-NEXT:    # <MCOperand Reg:416>
-; MIPS4-NEXT:    # <MCOperand Reg:416>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS4-NEXT:    # <MCOperand Imm:16>>
 ; MIPS4-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS4-NEXT:    # <MCOperand Reg:301>>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MIPS4-NEXT:    sw $1, %lo(c)($2) # <MCInst #{{[0-9]+}} SW
-; MIPS4-NEXT:    # <MCOperand Reg:1>
-; MIPS4-NEXT:    # <MCOperand Reg:416>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS4-NEXT:    # <MCOperand Expr:(%lo(c))>>
 ;
 ; MIPS64R6-LABEL: f3:
 ; MIPS64R6:       # %bb.0:
 ; MIPS64R6-NEXT:    sll $1, $4, 0 # <MCInst #{{[0-9]+}} SLL
-; MIPS64R6-NEXT:    # <MCOperand Reg:1>
-; MIPS64R6-NEXT:    # <MCOperand Reg:22>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Imm:0>>
 ; MIPS64R6-NEXT:    lui $2, %highest(c) # <MCInst #{{[0-9]+}} LUi64
-; MIPS64R6-NEXT:    # <MCOperand Reg:416>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(c))>>
 ; MIPS64R6-NEXT:    daddiu $2, $2, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT:    # <MCOperand Reg:416>
-; MIPS64R6-NEXT:    # <MCOperand Reg:416>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(c))>>
 ; MIPS64R6-NEXT:    dsll $2, $2, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT:    # <MCOperand Reg:416>
-; MIPS64R6-NEXT:    # <MCOperand Reg:416>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
 ; MIPS64R6-NEXT:    daddiu $2, $2, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT:    # <MCOperand Reg:416>
-; MIPS64R6-NEXT:    # <MCOperand Reg:416>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(c))>>
 ; MIPS64R6-NEXT:    dsll $2, $2, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT:    # <MCOperand Reg:416>
-; MIPS64R6-NEXT:    # <MCOperand Reg:416>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
 ; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
-; MIPS64R6-NEXT:    # <MCOperand Reg:355>
-; MIPS64R6-NEXT:    # <MCOperand Reg:301>>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MIPS64R6-NEXT:    sw $1, %lo(c)($2) # <MCInst #{{[0-9]+}} SW
-; MIPS64R6-NEXT:    # <MCOperand Reg:1>
-; MIPS64R6-NEXT:    # <MCOperand Reg:416>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(c))>>
   store i32 %a, i32 * @c
   ret void
@@ -355,139 +355,139 @@ define void @f4(i64 %a) {
 ; MIPS32-LABEL: f4:
 ; MIPS32:       # %bb.0:
 ; MIPS32-NEXT:    lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi
-; MIPS32-NEXT:    # <MCOperand Reg:1>
+; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS32-NEXT:    # <MCOperand Expr:(%hi(d))>>
 ; MIPS32-NEXT:    sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW
-; MIPS32-NEXT:    # <MCOperand Reg:22>
-; MIPS32-NEXT:    # <MCOperand Reg:1>
+; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS32-NEXT:    # <MCOperand Expr:(%lo(d))>>
 ; MIPS32-NEXT:    addiu $1, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu
-; MIPS32-NEXT:    # <MCOperand Reg:1>
-; MIPS32-NEXT:    # <MCOperand Reg:1>
+; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS32-NEXT:    # <MCOperand Expr:(%lo(d))>>
 ; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS32-NEXT:    # <MCOperand Reg:19>>
+; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MIPS32-NEXT:    sw $5, 4($1) # <MCInst #{{[0-9]+}} SW
-; MIPS32-NEXT:    # <MCOperand Reg:23>
-; MIPS32-NEXT:    # <MCOperand Reg:1>
+; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS32-NEXT:    # <MCOperand Imm:4>>
 ;
 ; MMR3-LABEL: f4:
 ; MMR3:       # %bb.0:
 ; MMR3-NEXT:    lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi
-; MMR3-NEXT:    # <MCOperand Reg:1>
+; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR3-NEXT:    # <MCOperand Expr:(%hi(d))>>
 ; MMR3-NEXT:    sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW_MM
-; MMR3-NEXT:    # <MCOperand Reg:22>
-; MMR3-NEXT:    # <MCOperand Reg:1>
+; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR3-NEXT:    # <MCOperand Expr:(%lo(d))>>
 ; MMR3-NEXT:    addiu $2, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu
-; MMR3-NEXT:    # <MCOperand Reg:321>
-; MMR3-NEXT:    # <MCOperand Reg:1>
+; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR3-NEXT:    # <MCOperand Expr:(%lo(d))>>
 ; MMR3-NEXT:    sw16 $5, 4($2) # <MCInst #{{[0-9]+}} SW16_MM
-; MMR3-NEXT:    # <MCOperand Reg:23>
-; MMR3-NEXT:    # <MCOperand Reg:321>
+; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR3-NEXT:    # <MCOperand Imm:4>>
 ; MMR3-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
-; MMR3-NEXT:    # <MCOperand Reg:19>>
+; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ;
 ; MIPS32R6-LABEL: f4:
 ; MIPS32R6:       # %bb.0:
 ; MIPS32R6-NEXT:    lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi
-; MIPS32R6-NEXT:    # <MCOperand Reg:1>
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(d))>>
 ; MIPS32R6-NEXT:    sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW
-; MIPS32R6-NEXT:    # <MCOperand Reg:22>
-; MIPS32R6-NEXT:    # <MCOperand Reg:1>
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(d))>>
 ; MIPS32R6-NEXT:    addiu $1, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu
-; MIPS32R6-NEXT:    # <MCOperand Reg:1>
-; MIPS32R6-NEXT:    # <MCOperand Reg:1>
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(d))>>
 ; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
-; MIPS32R6-NEXT:    # <MCOperand Reg:21>
-; MIPS32R6-NEXT:    # <MCOperand Reg:19>>
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MIPS32R6-NEXT:    sw $5, 4($1) # <MCInst #{{[0-9]+}} SW
-; MIPS32R6-NEXT:    # <MCOperand Reg:23>
-; MIPS32R6-NEXT:    # <MCOperand Reg:1>
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS32R6-NEXT:    # <MCOperand Imm:4>>
 ;
 ; MMR6-LABEL: f4:
 ; MMR6:       # %bb.0:
 ; MMR6-NEXT:    lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi
-; MMR6-NEXT:    # <MCOperand Reg:1>
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-NEXT:    # <MCOperand Expr:(%hi(d))>>
 ; MMR6-NEXT:    sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW_MM
-; MMR6-NEXT:    # <MCOperand Reg:22>
-; MMR6-NEXT:    # <MCOperand Reg:1>
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-NEXT:    # <MCOperand Expr:(%lo(d))>>
 ; MMR6-NEXT:    addiu $2, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu
-; MMR6-NEXT:    # <MCOperand Reg:321>
-; MMR6-NEXT:    # <MCOperand Reg:1>
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-NEXT:    # <MCOperand Expr:(%lo(d))>>
 ; MMR6-NEXT:    sw16 $5, 4($2) # <MCInst #{{[0-9]+}} SW16_MM
-; MMR6-NEXT:    # <MCOperand Reg:23>
-; MMR6-NEXT:    # <MCOperand Reg:321>
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-NEXT:    # <MCOperand Imm:4>>
 ; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
-; MMR6-NEXT:    # <MCOperand Reg:19>>
+; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ;
 ; MIPS4-LABEL: f4:
 ; MIPS4:       # %bb.0:
 ; MIPS4-NEXT:    lui $1, %highest(d) # <MCInst #{{[0-9]+}} LUi64
-; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS4-NEXT:    # <MCOperand Expr:(%highest(d))>>
 ; MIPS4-NEXT:    daddiu $1, $1, %higher(d) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS4-NEXT:    # <MCOperand Reg:30>
-; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS4-NEXT:    # <MCOperand Expr:(%higher(d))>>
 ; MIPS4-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS4-NEXT:    # <MCOperand Reg:30>
-; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS4-NEXT:    # <MCOperand Imm:16>>
 ; MIPS4-NEXT:    daddiu $1, $1, %hi(d) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS4-NEXT:    # <MCOperand Reg:30>
-; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS4-NEXT:    # <MCOperand Expr:(%hi(d))>>
 ; MIPS4-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS4-NEXT:    # <MCOperand Reg:30>
-; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS4-NEXT:    # <MCOperand Imm:16>>
 ; MIPS4-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS4-NEXT:    # <MCOperand Reg:301>>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MIPS4-NEXT:    sd $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SD
-; MIPS4-NEXT:    # <MCOperand Reg:356>
-; MIPS4-NEXT:    # <MCOperand Reg:30>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS4-NEXT:    # <MCOperand Expr:(%lo(d))>>
 ;
 ; MIPS64R6-LABEL: f4:
 ; MIPS64R6:       # %bb.0:
 ; MIPS64R6-NEXT:    lui $1, %highest(d) # <MCInst #{{[0-9]+}} LUi64
-; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(d))>>
 ; MIPS64R6-NEXT:    daddiu $1, $1, %higher(d) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT:    # <MCOperand Reg:30>
-; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(d))>>
 ; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT:    # <MCOperand Reg:30>
-; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
 ; MIPS64R6-NEXT:    daddiu $1, $1, %hi(d) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT:    # <MCOperand Reg:30>
-; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(d))>>
 ; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT:    # <MCOperand Reg:30>
-; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
 ; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
-; MIPS64R6-NEXT:    # <MCOperand Reg:355>
-; MIPS64R6-NEXT:    # <MCOperand Reg:301>>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MIPS64R6-NEXT:    sd $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SD
-; MIPS64R6-NEXT:    # <MCOperand Reg:356>
-; MIPS64R6-NEXT:    # <MCOperand Reg:30>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(d))>>
   store i64 %a, i64 * @d
   ret void

test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll

@@ -8,52 +8,52 @@ define i64 @test(i32 signext %a, i32 signext %b) {
 ; MMR2-LABEL: test:
 ; MMR2:       # %bb.0: # %entry
 ; MMR2-NEXT:    li16 $2, 0 # <MCInst #{{[0-9]+}} LI16_MM
-; MMR2-NEXT:    # <MCOperand Reg:321>
+; MMR2-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR2-NEXT:    # <MCOperand Imm:0>>
 ; MMR2-NEXT:    li16 $3, 1 # <MCInst #{{[0-9]+}} LI16_MM
-; MMR2-NEXT:    # <MCOperand Reg:322>
+; MMR2-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR2-NEXT:    # <MCOperand Imm:1>>
 ; MMR2-NEXT:    mtlo $3 # <MCInst #{{[0-9]+}} MTLO_MM
-; MMR2-NEXT:    # <MCOperand Reg:322>>
+; MMR2-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MMR2-NEXT:    mthi $2 # <MCInst #{{[0-9]+}} MTHI_MM
-; MMR2-NEXT:    # <MCOperand Reg:321>>
+; MMR2-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MMR2-NEXT:    madd $4, $5 # <MCInst #{{[0-9]+}} MADD
-; MMR2-NEXT:    # <MCOperand Reg:22>
-; MMR2-NEXT:    # <MCOperand Reg:23>>
+; MMR2-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR2-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MMR2-NEXT:    mflo16 $2 # <MCInst #{{[0-9]+}} MFLO16_MM
-; MMR2-NEXT:    # <MCOperand Reg:321>>
+; MMR2-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MMR2-NEXT:    mfhi16 $3 # <MCInst #{{[0-9]+}} MFHI16_MM
-; MMR2-NEXT:    # <MCOperand Reg:322>>
+; MMR2-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MMR2-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
-; MMR2-NEXT:    # <MCOperand Reg:19>>
+; MMR2-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ;
 ; MMR2-DSP-LABEL: test:
 ; MMR2-DSP:       # %bb.0: # %entry
 ; MMR2-DSP-NEXT:    li16 $2, 0 # <MCInst #{{[0-9]+}} LI16_MM
-; MMR2-DSP-NEXT:    # <MCOperand Reg:321>
+; MMR2-DSP-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR2-DSP-NEXT:    # <MCOperand Imm:0>>
 ; MMR2-DSP-NEXT:    li16 $3, 1 # <MCInst #{{[0-9]+}} LI16_MM
-; MMR2-DSP-NEXT:    # <MCOperand Reg:322>
+; MMR2-DSP-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR2-DSP-NEXT:    # <MCOperand Imm:1>>
 ; MMR2-DSP-NEXT:    mtlo $3, $ac0 # <MCInst #{{[0-9]+}} MTLO_DSP
-; MMR2-DSP-NEXT:    # <MCOperand Reg:291>
-; MMR2-DSP-NEXT:    # <MCOperand Reg:322>>
+; MMR2-DSP-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR2-DSP-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MMR2-DSP-NEXT:    mthi $2, $ac0 # <MCInst #{{[0-9]+}} MTHI_DSP
-; MMR2-DSP-NEXT:    # <MCOperand Reg:253>
-; MMR2-DSP-NEXT:    # <MCOperand Reg:321>>
+; MMR2-DSP-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR2-DSP-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MMR2-DSP-NEXT:    madd $ac0, $4, $5 # <MCInst #{{[0-9]+}} MADD_DSP
-; MMR2-DSP-NEXT:    # <MCOperand Reg:26>
-; MMR2-DSP-NEXT:    # <MCOperand Reg:22>
-; MMR2-DSP-NEXT:    # <MCOperand Reg:23>
-; MMR2-DSP-NEXT:    # <MCOperand Reg:26>>
+; MMR2-DSP-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR2-DSP-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR2-DSP-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR2-DSP-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MMR2-DSP-NEXT:    mflo $2, $ac0 # <MCInst #{{[0-9]+}} MFLO_DSP
-; MMR2-DSP-NEXT:    # <MCOperand Reg:321>
-; MMR2-DSP-NEXT:    # <MCOperand Reg:26>>
+; MMR2-DSP-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR2-DSP-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MMR2-DSP-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR2-DSP-NEXT:    # <MCOperand Reg:19>>
+; MMR2-DSP-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 ; MMR2-DSP-NEXT:    mfhi $3, $ac0 # <MCInst #{{[0-9]+}} MFHI_DSP
-; MMR2-DSP-NEXT:    # <MCOperand Reg:322>
-; MMR2-DSP-NEXT:    # <MCOperand Reg:26>>
+; MMR2-DSP-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
+; MMR2-DSP-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 entry:
   %conv = sext i32 %a to i64
   %conv1 = sext i32 %b to i64