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@@ -12,30 +12,67 @@
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//
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//===----------------------------------------------------------------------===//
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-#include "llvm/CodeGen/MachineScheduler.h"
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+#include "llvm/ADT/ArrayRef.h"
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+#include "llvm/ADT/BitVector.h"
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+#include "llvm/ADT/DenseMap.h"
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+#include "llvm/ADT/iterator_range.h"
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#include "llvm/ADT/PriorityQueue.h"
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+#include "llvm/ADT/SmallVector.h"
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+#include "llvm/ADT/STLExtras.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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+#include "llvm/CodeGen/LiveInterval.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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+#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineDominators.h"
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+#include "llvm/CodeGen/MachineFunction.h"
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+#include "llvm/CodeGen/MachineFunctionPass.h"
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+#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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+#include "llvm/CodeGen/MachineOperand.h"
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+#include "llvm/CodeGen/MachinePassRegistry.h"
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+#include "llvm/CodeGen/RegisterPressure.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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+#include "llvm/CodeGen/MachineScheduler.h"
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+#include "llvm/CodeGen/MachineValueType.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/RegisterClassInfo.h"
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+#include "llvm/CodeGen/ScheduleDAG.h"
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+#include "llvm/CodeGen/ScheduleDAGInstrs.h"
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+#include "llvm/CodeGen/ScheduleDAGMutation.h"
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#include "llvm/CodeGen/ScheduleDFS.h"
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#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
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+#include "llvm/CodeGen/SlotIndexes.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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+#include "llvm/CodeGen/TargetSchedule.h"
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+#include "llvm/MC/LaneBitmask.h"
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+#include "llvm/Pass.h"
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#include "llvm/Support/CommandLine.h"
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+#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/GraphWriter.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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+#include "llvm/Target/TargetLowering.h"
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+#include "llvm/Target/TargetRegisterInfo.h"
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+#include "llvm/Target/TargetSubtargetInfo.h"
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+#include <algorithm>
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+#include <cassert>
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+#include <cstdint>
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+#include <iterator>
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+#include <limits>
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+#include <memory>
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+#include <string>
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+#include <tuple>
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+#include <utility>
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+#include <vector>
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using namespace llvm;
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#define DEBUG_TYPE "misched"
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namespace llvm {
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+
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cl::opt<bool> ForceTopDown("misched-topdown", cl::Hidden,
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cl::desc("Force top-down list scheduling"));
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cl::opt<bool> ForceBottomUp("misched-bottomup", cl::Hidden,
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@@ -43,7 +80,8 @@ cl::opt<bool> ForceBottomUp("misched-bottomup", cl::Hidden,
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cl::opt<bool>
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DumpCriticalPathLength("misched-dcpl", cl::Hidden,
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cl::desc("Print critical path length to stdout"));
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-}
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+
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+} // end namespace llvm
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#ifndef NDEBUG
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static cl::opt<bool> ViewMISchedDAGs("view-misched-dags", cl::Hidden,
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@@ -88,14 +126,14 @@ static const unsigned MinSubtreeSize = 8;
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// Pin the vtables to this file.
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void MachineSchedStrategy::anchor() {}
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+
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void ScheduleDAGMutation::anchor() {}
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//===----------------------------------------------------------------------===//
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// Machine Instruction Scheduling Pass and Registry
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//===----------------------------------------------------------------------===//
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-MachineSchedContext::MachineSchedContext():
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- MF(nullptr), MLI(nullptr), MDT(nullptr), PassConfig(nullptr), AA(nullptr), LIS(nullptr) {
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+MachineSchedContext::MachineSchedContext() {
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RegClassInfo = new RegisterClassInfo();
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}
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@@ -104,6 +142,7 @@ MachineSchedContext::~MachineSchedContext() {
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}
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namespace {
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+
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/// Base class for a machine scheduler class that can run at any point.
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class MachineSchedulerBase : public MachineSchedContext,
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public MachineFunctionPass {
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@@ -145,7 +184,8 @@ public:
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protected:
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ScheduleDAGInstrs *createPostMachineScheduler();
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};
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-} // namespace
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+
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+} // end anonymous namespace
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char MachineScheduler::ID = 0;
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@@ -207,7 +247,7 @@ static ScheduleDAGInstrs *useDefaultMachineSched(MachineSchedContext *C) {
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/// MachineSchedOpt allows command line selection of the scheduler.
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static cl::opt<MachineSchedRegistry::ScheduleDAGCtor, false,
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- RegisterPassParser<MachineSchedRegistry> >
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+ RegisterPassParser<MachineSchedRegistry>>
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MachineSchedOpt("misched",
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cl::init(&useDefaultMachineSched), cl::Hidden,
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cl::desc("Machine instruction scheduler to use"));
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@@ -444,7 +484,7 @@ void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler,
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// instruction stream until we find the nearest boundary.
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unsigned NumRegionInstrs = 0;
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MachineBasicBlock::iterator I = RegionEnd;
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- for (;I != MBB->begin(); --I) {
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+ for (; I != MBB->begin(); --I) {
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MachineInstr &MI = *std::prev(I);
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if (isSchedBoundary(&MI, &*MBB, MF, TII))
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break;
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@@ -516,8 +556,7 @@ LLVM_DUMP_METHOD void ReadyQueue::dump() {
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// ===----------------------------------------------------------------------===/
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// Provide a vtable anchor.
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-ScheduleDAGMI::~ScheduleDAGMI() {
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-}
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+ScheduleDAGMI::~ScheduleDAGMI() = default;
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bool ScheduleDAGMI::canAddEdge(SUnit *SuccSU, SUnit *PredSU) {
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return SuccSU == &ExitSU || !Topo.IsReachable(PredSU, SuccSU);
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@@ -822,7 +861,7 @@ void ScheduleDAGMI::placeDebugValues() {
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RegionBegin = FirstDbgValue;
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}
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- for (std::vector<std::pair<MachineInstr *, MachineInstr *> >::iterator
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+ for (std::vector<std::pair<MachineInstr *, MachineInstr *>>::iterator
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DI = DbgValues.end(), DE = DbgValues.begin(); DI != DE; --DI) {
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std::pair<MachineInstr *, MachineInstr *> P = *std::prev(DI);
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MachineInstr *DbgValue = P.first;
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@@ -1009,7 +1048,7 @@ updateScheduledPressure(const SUnit *SU,
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++CritIdx;
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if (CritIdx != CritEnd && RegionCriticalPSets[CritIdx].getPSet() == ID) {
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if ((int)NewMaxPressure[ID] > RegionCriticalPSets[CritIdx].getUnitInc()
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- && NewMaxPressure[ID] <= INT16_MAX)
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+ && NewMaxPressure[ID] <= std::numeric_limits<int16_t>::max())
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RegionCriticalPSets[CritIdx].setUnitInc(NewMaxPressure[ID]);
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}
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unsigned Limit = RegClassInfo->getRegPressureSetLimit(ID);
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@@ -1393,6 +1432,7 @@ void ScheduleDAGMILive::scheduleMI(SUnit *SU, bool IsTopNode) {
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//===----------------------------------------------------------------------===//
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namespace {
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+
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/// \brief Post-process the DAG to create cluster edges between neighboring
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/// loads or between neighboring stores.
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class BaseMemOpClusterMutation : public ScheduleDAGMutation {
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@@ -1400,6 +1440,7 @@ class BaseMemOpClusterMutation : public ScheduleDAGMutation {
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SUnit *SU;
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unsigned BaseReg;
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int64_t Offset;
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+
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MemOpInfo(SUnit *su, unsigned reg, int64_t ofs)
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: SU(su), BaseReg(reg), Offset(ofs) {}
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@@ -1436,25 +1477,26 @@ public:
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LoadClusterMutation(const TargetInstrInfo *tii, const TargetRegisterInfo *tri)
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: BaseMemOpClusterMutation(tii, tri, true) {}
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};
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-} // anonymous
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+
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+} // end anonymous namespace
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namespace llvm {
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std::unique_ptr<ScheduleDAGMutation>
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createLoadClusterDAGMutation(const TargetInstrInfo *TII,
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const TargetRegisterInfo *TRI) {
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- return EnableMemOpCluster ? make_unique<LoadClusterMutation>(TII, TRI)
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+ return EnableMemOpCluster ? llvm::make_unique<LoadClusterMutation>(TII, TRI)
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: nullptr;
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}
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std::unique_ptr<ScheduleDAGMutation>
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createStoreClusterDAGMutation(const TargetInstrInfo *TII,
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const TargetRegisterInfo *TRI) {
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- return EnableMemOpCluster ? make_unique<StoreClusterMutation>(TII, TRI)
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+ return EnableMemOpCluster ? llvm::make_unique<StoreClusterMutation>(TII, TRI)
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: nullptr;
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}
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-} // namespace llvm
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+} // end namespace llvm
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void BaseMemOpClusterMutation::clusterNeighboringMemOps(
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ArrayRef<SUnit *> MemOps, ScheduleDAGMI *DAG) {
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@@ -1544,6 +1586,7 @@ void BaseMemOpClusterMutation::apply(ScheduleDAGInstrs *DAGInstrs) {
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//===----------------------------------------------------------------------===//
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namespace {
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+
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/// \brief Post-process the DAG to create weak edges from all uses of a copy to
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/// the one use that defines the copy's source vreg, most likely an induction
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/// variable increment.
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@@ -1553,6 +1596,7 @@ class CopyConstrain : public ScheduleDAGMutation {
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// RegionEndIdx is the slot index of the last non-debug instruction in the
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// scheduling region. So we may have RegionBeginIdx == RegionEndIdx.
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SlotIndex RegionEndIdx;
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+
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public:
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CopyConstrain(const TargetInstrInfo *, const TargetRegisterInfo *) {}
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@@ -1561,17 +1605,18 @@ public:
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protected:
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void constrainLocalCopy(SUnit *CopySU, ScheduleDAGMILive *DAG);
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};
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-} // anonymous
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+
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+} // end anonymous namespace
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namespace llvm {
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std::unique_ptr<ScheduleDAGMutation>
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createCopyConstrainDAGMutation(const TargetInstrInfo *TII,
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- const TargetRegisterInfo *TRI) {
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- return make_unique<CopyConstrain>(TII, TRI);
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+ const TargetRegisterInfo *TRI) {
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+ return llvm::make_unique<CopyConstrain>(TII, TRI);
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}
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-} // namespace llvm
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+} // end namespace llvm
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/// constrainLocalCopy handles two possibilities:
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/// 1) Local src:
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@@ -1763,7 +1808,7 @@ void SchedBoundary::reset() {
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CheckPending = false;
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CurrCycle = 0;
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CurrMOps = 0;
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- MinReadyCycle = UINT_MAX;
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+ MinReadyCycle = std::numeric_limits<unsigned>::max();
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ExpectedLatency = 0;
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DependentLatency = 0;
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RetiredMOps = 0;
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@@ -1966,7 +2011,8 @@ void SchedBoundary::releaseNode(SUnit *SU, unsigned ReadyCycle) {
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/// Move the boundary of scheduled code by one cycle.
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void SchedBoundary::bumpCycle(unsigned NextCycle) {
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if (SchedModel->getMicroOpBufferSize() == 0) {
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- assert(MinReadyCycle < UINT_MAX && "MinReadyCycle uninitialized");
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+ assert(MinReadyCycle < std::numeric_limits<unsigned>::max() &&
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+ "MinReadyCycle uninitialized");
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if (MinReadyCycle > NextCycle)
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NextCycle = MinReadyCycle;
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}
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@@ -2177,7 +2223,7 @@ void SchedBoundary::bumpNode(SUnit *SU) {
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void SchedBoundary::releasePending() {
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// If the available queue is empty, it is safe to reset MinReadyCycle.
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if (Available.empty())
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- MinReadyCycle = UINT_MAX;
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+ MinReadyCycle = std::numeric_limits<unsigned>::max();
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// Check to see if any of the pending instructions are ready to issue. If
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// so, add them to the available queue.
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@@ -3036,7 +3082,6 @@ SUnit *GenericScheduler::pickNode(bool &IsTopNode) {
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}
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void GenericScheduler::reschedulePhysRegCopies(SUnit *SU, bool isTop) {
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-
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MachineBasicBlock::iterator InsertPos = SU->getInstr();
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if (!isTop)
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++InsertPos;
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@@ -3084,7 +3129,8 @@ void GenericScheduler::schedNode(SUnit *SU, bool IsTopNode) {
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/// Create the standard converging machine scheduler. This will be used as the
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/// default scheduler if the target does not set a default.
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ScheduleDAGMILive *llvm::createGenericSchedLive(MachineSchedContext *C) {
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- ScheduleDAGMILive *DAG = new ScheduleDAGMILive(C, make_unique<GenericScheduler>(C));
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+ ScheduleDAGMILive *DAG =
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+ new ScheduleDAGMILive(C, llvm::make_unique<GenericScheduler>(C));
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// Register DAG post-processors.
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//
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// FIXME: extend the mutation API to allow earlier mutations to instantiate
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@@ -3125,7 +3171,6 @@ void PostGenericScheduler::initialize(ScheduleDAGMI *Dag) {
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}
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}
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-
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void PostGenericScheduler::registerRoots() {
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Rem.CriticalPath = DAG->ExitSU.getDepth();
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@@ -3232,7 +3277,7 @@ void PostGenericScheduler::schedNode(SUnit *SU, bool IsTopNode) {
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}
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ScheduleDAGMI *llvm::createGenericSchedPostRA(MachineSchedContext *C) {
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- return new ScheduleDAGMI(C, make_unique<PostGenericScheduler>(C),
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+ return new ScheduleDAGMI(C, llvm::make_unique<PostGenericScheduler>(C),
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/*RemoveKillFlags=*/true);
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}
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@@ -3241,14 +3286,14 @@ ScheduleDAGMI *llvm::createGenericSchedPostRA(MachineSchedContext *C) {
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//===----------------------------------------------------------------------===//
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namespace {
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+
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/// \brief Order nodes by the ILP metric.
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struct ILPOrder {
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- const SchedDFSResult *DFSResult;
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- const BitVector *ScheduledTrees;
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+ const SchedDFSResult *DFSResult = nullptr;
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+ const BitVector *ScheduledTrees = nullptr;
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bool MaximizeILP;
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- ILPOrder(bool MaxILP)
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- : DFSResult(nullptr), ScheduledTrees(nullptr), MaximizeILP(MaxILP) {}
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+ ILPOrder(bool MaxILP) : MaximizeILP(MaxILP) {}
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/// \brief Apply a less-than relation on node priority.
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///
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@@ -3277,12 +3322,13 @@ struct ILPOrder {
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/// \brief Schedule based on the ILP metric.
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class ILPScheduler : public MachineSchedStrategy {
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- ScheduleDAGMILive *DAG;
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+ ScheduleDAGMILive *DAG = nullptr;
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ILPOrder Cmp;
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std::vector<SUnit*> ReadyQ;
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+
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public:
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- ILPScheduler(bool MaximizeILP): DAG(nullptr), Cmp(MaximizeILP) {}
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+ ILPScheduler(bool MaximizeILP) : Cmp(MaximizeILP) {}
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void initialize(ScheduleDAGMI *dag) override {
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assert(dag->hasVRegLiveness() && "ILPScheduler needs vreg liveness");
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@@ -3335,14 +3381,16 @@ public:
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std::push_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
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}
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};
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-} // namespace
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+
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+} // end anonymous namespace
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static ScheduleDAGInstrs *createILPMaxScheduler(MachineSchedContext *C) {
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- return new ScheduleDAGMILive(C, make_unique<ILPScheduler>(true));
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+ return new ScheduleDAGMILive(C, llvm::make_unique<ILPScheduler>(true));
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}
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static ScheduleDAGInstrs *createILPMinScheduler(MachineSchedContext *C) {
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- return new ScheduleDAGMILive(C, make_unique<ILPScheduler>(false));
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+ return new ScheduleDAGMILive(C, llvm::make_unique<ILPScheduler>(false));
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}
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+
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static MachineSchedRegistry ILPMaxRegistry(
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"ilpmax", "Schedule bottom-up for max ILP", createILPMaxScheduler);
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static MachineSchedRegistry ILPMinRegistry(
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@@ -3354,6 +3402,7 @@ static MachineSchedRegistry ILPMinRegistry(
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#ifndef NDEBUG
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namespace {
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+
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/// Apply a less-than relation on the node order, which corresponds to the
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/// instruction order prior to scheduling. IsReverse implements greater-than.
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template<bool IsReverse>
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@@ -3374,11 +3423,12 @@ class InstructionShuffler : public MachineSchedStrategy {
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// Using a less-than relation (SUnitOrder<false>) for the TopQ priority
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// gives nodes with a higher number higher priority causing the latest
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// instructions to be scheduled first.
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- PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<false> >
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+ PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<false>>
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TopQ;
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// When scheduling bottom-up, use greater-than as the queue priority.
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- PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<true> >
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+ PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<true>>
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BottomQ;
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+
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public:
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InstructionShuffler(bool alternate, bool topdown)
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: IsAlternating(alternate), IsTopDown(topdown) {}
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@@ -3422,15 +3472,18 @@ public:
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BottomQ.push(SU);
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}
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};
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-} // namespace
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+
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+} // end anonymous namespace
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|
|
|
|
|
static ScheduleDAGInstrs *createInstructionShuffler(MachineSchedContext *C) {
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bool Alternate = !ForceTopDown && !ForceBottomUp;
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bool TopDown = !ForceBottomUp;
|
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assert((TopDown || !ForceTopDown) &&
|
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|
"-misched-topdown incompatible with -misched-bottomup");
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|
- return new ScheduleDAGMILive(C, make_unique<InstructionShuffler>(Alternate, TopDown));
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|
+ return new ScheduleDAGMILive(
|
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|
+ C, llvm::make_unique<InstructionShuffler>(Alternate, TopDown));
|
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|
}
|
|
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+
|
|
|
static MachineSchedRegistry ShufflerRegistry(
|
|
|
"shuffle", "Shuffle machine instructions alternating directions",
|
|
|
createInstructionShuffler);
|
|
|
@@ -3448,8 +3501,7 @@ template<> struct GraphTraits<
|
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|
|
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|
template<>
|
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|
struct DOTGraphTraits<ScheduleDAGMI*> : public DefaultDOTGraphTraits {
|
|
|
-
|
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|
- DOTGraphTraits (bool isSimple=false) : DefaultDOTGraphTraits(isSimple) {}
|
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|
+ DOTGraphTraits(bool isSimple = false) : DefaultDOTGraphTraits(isSimple) {}
|
|
|
|
|
|
static std::string getGraphName(const ScheduleDAG *G) {
|
|
|
return G->MF.getName();
|
|
|
@@ -3506,7 +3558,8 @@ struct DOTGraphTraits<ScheduleDAGMI*> : public DefaultDOTGraphTraits {
|
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|
return Str;
|
|
|
}
|
|
|
};
|
|
|
-} // namespace llvm
|
|
|
+
|
|
|
+} // end namespace llvm
|
|
|
#endif // NDEBUG
|
|
|
|
|
|
/// viewGraph - Pop up a ghostview window with the reachable parts of the DAG
|
Eugene Zelenko