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@@ -1264,6 +1264,12 @@ void test1() {
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// CHECK: [[T1:%.+]] = and <4 x i32>
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// CHECK: xor <4 x i32> [[T1]], <i32 -1, i32 -1, i32 -1, i32 -1>
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// CHECK-LE: [[T1:%.+]] = and <4 x i32>
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+// CHECK-LE: xor <4 x i32> [[T1]], <i32 -1, i32 -1, i32 -1, i32 -1>
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+
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+ res_vf = vec_nand(vfa, vfa);
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+// CHECK: [[T1:%.+]] = and <4 x i32>
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+// CHECK: xor <4 x i32> [[T1]], <i32 -1, i32 -1, i32 -1, i32 -1>
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+// CHECK-LE: [[T1:%.+]] = and <4 x i32>
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// CHECK-LE: xor <4 x i32> [[T1]], <i32 -1, i32 -1, i32 -1, i32 -1>
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res_vsll = vec_nand(vsll, vsll);
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@@ -1282,6 +1288,12 @@ void test1() {
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// CHECK: [[T1:%.+]] = and <2 x i64>
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// CHECK: xor <2 x i64> [[T1]], <i64 -1, i64 -1>
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// CHECK-LE: [[T1:%.+]] = and <2 x i64>
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+// CHECK-LE: xor <2 x i64> [[T1]], <i64 -1, i64 -1>
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+
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+ res_vd = vec_nand(vda, vda);
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+// CHECK: [[T1:%.+]] = and <2 x i64>
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+// CHECK: xor <2 x i64> [[T1]], <i64 -1, i64 -1>
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+// CHECK-LE: [[T1:%.+]] = and <2 x i64>
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// CHECK-LE: xor <2 x i64> [[T1]], <i64 -1, i64 -1>
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/* vec_orc */
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@@ -1410,6 +1422,18 @@ void test1() {
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// CHECK: [[T1:%.+]] = xor <4 x i32> {{%.+}}, <i32 -1, i32 -1, i32 -1, i32 -1>
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// CHECK: or <4 x i32> {{%.+}}, [[T1]]
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// CHECK-LE: [[T1:%.+]] = xor <4 x i32> {{%.+}}, <i32 -1, i32 -1, i32 -1, i32 -1>
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+// CHECK-LE: or <4 x i32> {{%.+}}, [[T1]]
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+
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+ res_vf = vec_orc(vbi, vfa);
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+// CHECK: [[T1:%.+]] = xor <4 x i32> {{%.+}}, <i32 -1, i32 -1, i32 -1, i32 -1>
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+// CHECK: or <4 x i32> {{%.+}}, [[T1]]
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+// CHECK-LE: [[T1:%.+]] = xor <4 x i32> {{%.+}}, <i32 -1, i32 -1, i32 -1, i32 -1>
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+// CHECK-LE: or <4 x i32> {{%.+}}, [[T1]]
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+
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+ res_vf = vec_orc(vfa, vbi);
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+// CHECK: [[T1:%.+]] = xor <4 x i32> {{%.+}}, <i32 -1, i32 -1, i32 -1, i32 -1>
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+// CHECK: or <4 x i32> {{%.+}}, [[T1]]
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+// CHECK-LE: [[T1:%.+]] = xor <4 x i32> {{%.+}}, <i32 -1, i32 -1, i32 -1, i32 -1>
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// CHECK-LE: or <4 x i32> {{%.+}}, [[T1]]
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res_vsll = vec_orc(vsll, vsll);
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@@ -1452,6 +1476,18 @@ void test1() {
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// CHECK: [[T1:%.+]] = xor <2 x i64> {{%.+}}, <i64 -1, i64 -1>
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// CHECK: or <2 x i64> {{%.+}}, [[T1]]
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// CHECK-LE: [[T1:%.+]] = xor <2 x i64> {{%.+}}, <i64 -1, i64 -1>
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+// CHECK-LE: or <2 x i64> {{%.+}}, [[T1]]
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+
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+ res_vd = vec_orc(vbll, vda);
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+// CHECK: [[T1:%.+]] = xor <2 x i64> {{%.+}}, <i64 -1, i64 -1>
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+// CHECK: or <2 x i64> {{%.+}}, [[T1]]
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+// CHECK-LE: [[T1:%.+]] = xor <2 x i64> {{%.+}}, <i64 -1, i64 -1>
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+// CHECK-LE: or <2 x i64> {{%.+}}, [[T1]]
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+
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+ res_vd = vec_orc(vda, vbll);
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+// CHECK: [[T1:%.+]] = xor <2 x i64> {{%.+}}, <i64 -1, i64 -1>
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+// CHECK: or <2 x i64> {{%.+}}, [[T1]]
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+// CHECK-LE: [[T1:%.+]] = xor <2 x i64> {{%.+}}, <i64 -1, i64 -1>
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// CHECK-LE: or <2 x i64> {{%.+}}, [[T1]]
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/* vec_sub */
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