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@@ -337,3 +337,59 @@ index 63e10cc6df..1e1b553795 100644
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2.41.0
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2.41.0
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+From 0f1d6606c28d0ae81a1b311972c5c54e5e867bf0 Mon Sep 17 00:00:00 2001
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+From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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+Date: Wed, 11 Jun 2025 14:03:15 +0100
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+Subject: [PATCH] target/i386: fix TB exit logic in gen_movl_seg() when writing
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+ to SS
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+
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+Before commit e54ef98c8a ("target/i386: do not trigger IRQ shadow for LSS"), any
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+write to SS in gen_movl_seg() would cause a TB exit. The changes introduced by
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+this commit were intended to restrict the DISAS_EOB_INHIBIT_IRQ exit to the case
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+where inhibit_irq is true, but missed that a DISAS_EOB_NEXT exit can still be
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+required when writing to SS and inhibit_irq is false.
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+
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+Comparing the PE(s) && !VM86(s) section with the logic in x86_update_hflags(), we
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+can see that the DISAS_EOB_NEXT exit is still required for the !CODE32 case when
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+writing to SS in gen_movl_seg() because any change to the SS flags can affect
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+hflags. Similarly we can see that the existing CODE32 case is still correct since
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+a change to any of DS, ES and SS can affect hflags. Finally for the
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+gen_op_movl_seg_real() case an explicit TB exit is not needed because the segment
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+register selector does not affect hflags.
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+
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+Update the logic in gen_movl_seg() so that a write to SS with inhibit_irq set to
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+false where PE(s) && !VM86(s) will generate a DISAS_EOB_NEXT exit along with the
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+inline comment. This has the effect of allowing Win98SE to boot in QEMU once
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+again.
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+
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+Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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+Fixes: e54ef98c8a ("target/i386: do not trigger IRQ shadow for LSS")
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+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2987
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+Link: https://lore.kernel.org/r/20250611130315.383151-1-mark.cave-ayland@ilande.co.uk
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+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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+Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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+---
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+ target/i386/tcg/translate.c | 7 +++++--
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+ 1 file changed, 5 insertions(+), 2 deletions(-)
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+
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+diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
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+index 0fcddc2ec0..0cb87d0201 100644
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+--- a/target/i386/tcg/translate.c
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++++ b/target/i386/tcg/translate.c
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+@@ -2033,8 +2033,11 @@ static void gen_movl_seg(DisasContext *s, X86Seg seg_reg, TCGv src, bool inhibit
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+ tcg_gen_trunc_tl_i32(sel, src);
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+ gen_helper_load_seg(tcg_env, tcg_constant_i32(seg_reg), sel);
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+
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+- /* For move to DS/ES/SS, the addseg or ss32 flags may change. */
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+- if (CODE32(s) && seg_reg < R_FS) {
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++ /*
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++ * For moves to SS, the SS32 flag may change. For CODE32 only, changes
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++ * to SS, DS and ES may change the ADDSEG flags.
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++ */
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++ if (seg_reg == R_SS || (CODE32(s) && seg_reg < R_FS)) {
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+ s->base.is_jmp = DISAS_EOB_NEXT;
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+ }
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+ } else {
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+--
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+2.41.0
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+
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osy